CN108231886A - 制造半导体器件的方法以及半导体器件 - Google Patents

制造半导体器件的方法以及半导体器件 Download PDF

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CN108231886A
CN108231886A CN201710518181.0A CN201710518181A CN108231886A CN 108231886 A CN108231886 A CN 108231886A CN 201710518181 A CN201710518181 A CN 201710518181A CN 108231886 A CN108231886 A CN 108231886A
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seed layer
conducting terminal
terminal
silicon area
crystal silicon
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CN108231886B (zh
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L·利韦拉
P·科尔帕尼
P·蒙杰罗法雷洛
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STMicroelectronics SRL
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Abstract

本申请涉及制造半导体器件的方法以及半导体器件。一种制造竖直导电半导体器件的方法，该方法包括以下步骤：在单晶硅衬底内形成凹部；在该凹部中形成氧化硅晶种层；在该衬底上进行硅的外延生长，同时在该晶种层中生长多晶硅区以及在该衬底的围绕该晶种层的表面区中生长单晶硅区；以及在该多晶硅区中注入掺杂剂种类以形成导电路径，以便使该第二导电端子可从该竖直导电半导体器件的前侧电接入。

Description

制造半导体器件的方法以及半导体器件
技术领域
本发明涉及一种制造集成了竖直导电晶体管的半导体器件的方法，以及涉及一种竖直导电器件。
背景技术
众所周知，术语“竖直沟槽MOS”(VTMOS)一般用于定义一种用于使功率器件能够维持高电压的体系结构。可例如参考图1，根据已知类型的实施例，图1是集成了VTMOS器件3的裸片1的一部分的示意图。VTMOS的一个或多个控制(栅极)区5在单晶硅半导体本体2中在深度方向上延伸，从而使能够在使用中形成竖直导电沟道4(电流i’和i”在其中流动)。为此，源极区7和漏极区9形成在半导体本体2的对应相反表面2a、2b中。漏极区9是形成在半导体本体2的表面2b上的掺杂区。注入区在半导体本体2的表面2a与2b之间的单晶区中延伸、与漏极区9电接触，以形成将使表面1a上的漏极端子的电接触成为可能的导电路径8。以这种方式，VTMOS器件3在同一表面2a上具有栅极G、源极S和漏极D的电接触端子，从而简化了接触步骤(这些接触步骤可以例如经由引线键合来执行)。
裸片1的形成于其中的在使用中作为竖直导电沟道4的部分是VTMOS器件3的有源区域。存在于导电路径8与有源区域之间的是场板沟槽6，该场板沟槽以已知的方式在半导体本体2中在深度方向上延伸。
导电路径8是通过注入并随后热扩散掺杂剂种类形成的，并且沿着VTMOS器件的有源区域的边和在其外部延伸。导电路径8是低电阻路径并且通常被称为“漏极沉降区”。
半导体本体2通常包括例如由单晶硅制成的半导体衬底，在该半导体衬底上延伸的是厚度为几微米(例如，3μm至6μm)的外延层。导电路径8在外延层中贯穿其厚度延伸，而漏极区9基本上在衬底与外延层之间的交界处延伸。
根据外延层的厚度，导电路径8是通过利用对应的注入能量执行的一个或多个连续注入获得的，以便到达漏极区9，从而形成与其的电接触。然而，对于外延层2的较大厚度(具体地，大于3-4μm)而言，注入区可能会在到达漏极区9上遇到一些困难，或根本无法到达该漏极区9。其后果是形成了具有高电阻率的导电路径8(甚至等于VTMOS 3的通态电阻RON的30％)。
以SGS-ATES COMPONENTI ELETTRONICI S.P.A的名义提交的意大利专利文献第1101183号描述了一种制造多晶硅的集电极深扩散(沉降)的方法，该文献中多晶被视为是用于获得掺杂剂种类快速扩散的手段。为此，多晶硅柱在具有多晶硅晶种的单晶硅衬底上外延地生长。在外延生长的过程期间，在多晶硅晶种周围存在柱的显著形成(具有基本上梯形形状)，并且在剩余衬底部分中形成单晶硅。过渡区存在于多晶硅柱与单晶区之间。然而，由专利第1101183号所授的实施例呈现了一些缺点。用于外延层生长的温度(700℃与800℃之间)在与高产量兼容的时间内不足够用于厚层(例如，5μm与10μm之间)的生长。例如，为了在与高产量兼容的时间内保证具有足够维持几十伏工作电压的厚度(例如，具有大约6μm的厚度)的外延层的生长，将有必要使用高于1100℃的生长温度。然而，在这些温度条件下，多晶硅晶种不会导致多晶硅柱的形成，而是导致高度缺陷的单晶硅区的形成，这对于本公开的目的而言是不期望的。此外，本申请人发现：由专利第1101183号所授的实施例导致在顶表面(图2中的表面12a)上形成挠曲区域，该挠曲区域是由于多晶硅晶种上以及围绕其的单晶硅上的多晶硅柱的外延生长速率不同而引起的。
因此，有必要提供针对上述问题的解决方案。
发明内容
根据本发明，如所附权利要求书中所定义的，提供了一种制造集成了竖直导电晶体管的半导体器件的方法以及一种竖直导电器件。
附图说明
为了更好地理解本发明，现在仅通过非限制性示例的方式、参照所附附图来描述本发明的优选实施例，在附图中：
-图1以横向截面图示出了根据已知类型的实施例的VTMOS器件的一部分；
-图2以横向截面图示出了根据本公开的实施例的竖直导电器件的一部分；以及
-图3至图9以横向截面图示出了制造图2的竖直导电器件的方法的步骤。
具体实施方式
根据本公开的一个方面，图2展示了在半导体本体12中制成的、集成了竖直沟道电子器件11(例如，VTMOS)的裸片10的一部分。
具体地，本公开的一个方面涉及一种获得替代图1中所展示的并且由参考号8标示的漏极沉降的漏极沉降(即，深度扩散区)13的方法，其之前已经被描述过了。更具体地，根据本公开的一个方面，产生漏极沉降包括形成多晶区，在该多晶区中，掺杂剂种类的扩散更快并且使得能够获得比单晶硅中发生扩散分布更均匀的扩散分布。根据本公开的进一步方面，多晶区与单晶区同时外延地生长，其中，在后续处理步骤中，电子器件的有源区域将会扩展。根据本公开的进一步方面，多晶区的外延生长是从凹部中延伸的氧化硅晶种开始执行的。使用氧化硅作为晶种用于外延可实现在高温下进行加工(使加工效率最大化)，而氧化硅晶种的凹处使得具有多晶区以及单晶区的良好表面匀称性(由于多晶和单晶的生长速率不同而引起的无凹陷)的最终外延被获得。
更具体地，参考图2，半导体本体12包括衬底30以及生长在衬底30的顶部上并且具有包括在3μm与10μm之间的厚度(例如，大约5μm至6μm)的外延层42。有源区域15在半导体本体12中横向地相对于漏极沉降13延伸。有源区域15的形成不形成本公开的主题；因此，将不会对其进行详细描述。在这个背景下，有源区域15包括单晶硅区以及沟道区，该单晶硅区容纳电子器件11的一个或多个源极区14以及一个或多个栅极区16，在该沟道区中在使用时建立竖直导电沟道18。具体地，图2的电子器件11的导电沟道18在Z方向上形成源极区14与公共漏极区22之间的导电路径。漏极区22在半导体本体12的表面12b上延伸，该表面12b沿着Z方向与源极区14在其中延伸的相应表面12a相反。
根据本公开的一个方面，漏极沉降13是掺杂剂种类的注入和扩散区，该注入和扩散区在半导体本体12中在方向Z上延伸并且包括多晶硅区24。
根据本公开的实施例，多晶硅区24具有沿着Z的主延伸并且延伸穿过半导体本体12的总厚度的一部分。多晶硅区24具有帮助和促使注入掺杂剂种类均匀扩散的功能，该掺杂剂种类部分地形成了漏极沉降13。
在多晶硅区24与形成有源区域15的单晶硅区之间延伸的过渡区26由于结晶晶格从多晶到单晶的逐步调节而具有不完全的多晶结构。在电子器件11的制造背景下，此过渡区26可以被认为是缺陷区域，在该缺陷区域中最好不要形成有源区域15。
如以下所展示的，过渡区26的形成是制造工艺的结果。同样地，因为根据本公开的制造工艺设想了从氧化硅晶种开始形成多晶硅区24，所以氧化硅区28(具有用于多晶体外延生长的晶种的功能)在多晶硅区24下面延伸。漏极沉降13以及具体地多晶硅区24延伸远至漏极区22，从而使得在漏极区22与(掺杂的)多晶硅区24之间存在电接触。
现在接着是对漏极沉降13的实施例的描述。
参考图3至图9，展示了根据本公开的方面的用于形成图2漏极沉降13的步骤。
参考图3，提供了包括半导体衬底30的晶片100，该半导体衬底具体地由单晶硅制成、具有顶表面30a。P型硅衬底30已经配备有N+掺杂的掩埋层。此掩埋层形成了漏极区22。此方面以自身已知的方式属于现有技术并且在此不作进一步讨论。
交界层32形成在衬底30的顶表面30a上。交界层32具体地由热生长氧化硅制成并且具有若干纳米的厚度，例如包括在10nm与15nm之间(例如13nm)。在一个实施例中，在有氧气存在的大气压环境中、在800℃的温度下执行此交界层的热生长。
掩模层34然后例如由氮化硅形成，其厚度包括在100nm与150nm之间(例如120nm)。例如，在存在二氯甲硅烷(DCS)和氨气(NH3)时、在750℃下、在压力为230mTorr的环境中沉积掩模层34。
在这个背景下，交界层32具有减小界面应力的功能，该功能将在衬底30(Si)上直接沉积掩模层34(SiN)的情况下出现。
进一步形成在掩模层34上的是光致抗蚀剂层36，其厚度包括在1μm与2μm之间，用于通过光刻法限定晶片100的后续步骤。
然后，图2，在光致抗蚀剂层36的光刻限定之后，执行一个或多个化学蚀刻步骤(例如，RIE)以移除在晶片100的在其中将形成图2的漏极沉降13的区中的掩模层34、交界层32、和衬底30的选择部分。
根据一个实施例，掩模层34、交界层32、以及衬底30的一部分被移除，以便形成在平面XY的视图中具有圆形或者四边形形状的沟槽38，该沟槽的直径包括在大约0.5μm与2μm之间。沟槽38在衬底30内在沿着Z从衬底30的顶表面30a开始测量的十几或几十纳米(例如，50nm)的深度处终止。
接下来(图5)，光致抗蚀剂层36被移除，并且在晶片100上执行热生长氧化硅(SiO2)的步骤。具体地，氧化硅在衬底30的暴露区中、在沟槽38内生长。为了形成氧化硅晶种层40(其厚度包括在大约60nm与100nm之间)，在有水蒸气的环境中、在大约1000°下执行热氧化物的生长。
然后(图6)，从晶片100移除掩模层34和交界层32。此步骤可能是经由湿法蚀刻执行的，使用H3PO4来选择性地移除掩模层34的氮化硅，并且使用HF来移除交界层32的氧化物。HF蚀刻步骤也部分地移除晶种层40，使其变薄。本申请人发现：晶种层40在蚀刻交界层32的步骤之后，具有几十纳米(例如，30nm至100nm)的厚度，该厚度足够用于本公开的目的。晶种层40的厚度在任何情况下都不是关键参数。
在制造步骤(图6)之后没有立即执行外延生长的后续步骤的情况下，本征氧化层41以已知的方式形成(图7)在衬底30上。为了移除该本征氧化层，在有氢气(H2)的环境下执行热退火步骤。此步骤在大约1100℃的温度下执行了若干秒(例如，15-20秒)，以便有效地移除本征氧化物而不移除晶种层40。本申请人发现：上述退火步骤对于晶种层40的厚度没有显著影响。
然后(图8)，在晶片100上执行外延生长步骤。具体地，在温度包括在1000℃与1200℃之间(例如，1125℃)、具有三氯甲硅烷和氢气的环境中生长具有N掺杂的外延层。浓度约为2.5·1016cm-3的磷化氢(PH3)被用作掺杂气体。
晶种层40中的外延生长产生由多晶硅(多晶区24)制成的向上变尖的柱；具体地，多晶区24在横向截面图中具有基本上呈梯形的形状，具有在晶种层40中的长边以及相对的短边。换句话说，随着外延的厚度增加，多晶区24的生长前沿趋于闭合。在衬底30的表面区30a(如已所述的，其由单晶硅制成)中，单晶外延层有显著的外延生长。生长的两种前沿(单晶和多晶)按各自的速率继续并且产生过渡区26，该过渡区源自生长的两种前沿之间的相遇以及随之发生的晶格调节。因此，过渡区26既不是完全的单晶区域也不是完全的多晶区域，并且在本公开的背景下在共同形成漏极沉降13的掺杂剂种类的注入和扩散步骤期间被使用和采用。在横截面图中，过渡区26具有基本上倒置的梯形形状(图8仅示出了过渡区26的一半)，即，具有在晶种层40中的短边以及相对的长边。过渡区26由结晶平面<111>侧向地界定。
考虑到具有沿着X约为650nm的边长以及沿着Z约为50nm厚度的方形晶种层40，本申请人发现：使用先前提到的参数的外延生长导致形成具有沿着Z约2μm至3μm的延伸的多晶硅区24。外延生长被调整以形成外延层42，该外延层的厚度沿着Z包括在大约5μm与6μm之间(例如，5.8μm)。
一般而言，晶种层40的厚度对多晶硅区24沿着Z的延伸不具有影响。而是，在平面XY中的延伸决定了其最大高度。在平面XY中，使用直径包括在1.5μm与2.5μm之间的晶种层40，多晶硅区24沿着Z的延伸通常包括在1.5μm与2.5μm之间；如果生长具有包括在5μm与6μm之间的厚度的外延层，则没有显著的表面凹陷被注意到(外延表面基本上是平整的)。
下一步骤(图9)是在多晶硅区24中注入掺杂剂种类。换句话说，按顺序执行注入以便形成在外延层42中在对应深度处延伸的多个注入区44a、44b、44c，这些注入区在Z方向上彼此对准并且与多晶硅区24对准。
在一个实施例中，N型注入物(例如，通过磷注入)的剂量大约5·1013cm-2并且对应的注入能量大约为300keV(注入区44a)、1.5keV(注入区44b)、和3.2keV(注入区44c)。使用上述参数，本申请人发现：注入区44c在外延层42中在大约3μm的深度处延伸。在任何情况下，注入能量可以被调节为外延层42的厚度与多晶硅区24沿着Z的延伸的函数，从而使得至少最深的注入区(这里，区44c)至少部分地在多晶硅区24内延伸。
接下来，执行热退火步骤以便有助于扩散在先前步骤中注入的掺杂剂种类。根据一个实施例，在1000℃的温度下执行退火达2h的时间。
如由本申请人验证的，掺杂剂种类在多晶硅区24内的扩散分布示出了掺杂剂种类在多晶硅中的扩散深度，该扩散深度大约是出现在(参考图1描述的类型的)单晶硅区中的深度的三倍。同样地，另外，掺杂剂种类在过渡区26内的扩散分布更好。因此，获得漏极沉降区13，在该漏极沉降区中，掺杂剂种类的分布贯穿外延层的整个厚度呈现良好的均匀性。
因此，给定沿着Z相同的延伸，漏极沉降13由比图1的漏极沉降8更低的电阻率表征。
制造方法然后通过形成源极区14和栅极区16的已知步骤以及通过形成场板6继续，如图2中所展示的。如已所述的，优选的是在外延层42的单晶部分中形成源极区14和栅极区16，即，横向地相对于过渡区26。相比而言，场板沟槽6可以完全地或者部分地形成在过渡区26内，因为其不积极参与电传导过程。
通过检查根据本公开获得的本发明的特性，其提供的优点是明显的。
具体地，根据本公开的方法使得漏极沉降中掺杂剂的高浓度成为可能，并且使掺杂剂的扩散深度比已知技术更大。类似的优点可在根据之前的描述获得的器件中被发现。因此，该器件的通态电阻RON的值被减小，随之带来改善的性能、更低的功耗、以及更少的热耗散。
最终，明显的是可以对本文的描述和示出内容进行修改和改变而不由此背离本发明的如在所附权利要求书中限定的范围。

Claims (14)

1.一种制造半导体器件的方法，所述半导体器件集成了至少一个竖直导电晶体管(11)，所述竖直导电晶体管具有在第一侧(12a)处的第一导电端子(14)、在与所述第一侧(12a)相反的第二侧(12b)处的第二导电端子(22)、以及控制端子(16)，所述竖直导电晶体管可以被偏置用于在所述第一与第二导电端子之间产生导电沟道(18)，所述方法包括以下步骤：
-在单晶硅衬底(30)中形成凹部(38)；
-在所述凹部(38)中形成氧化硅晶种层(40)；
-在所述衬底(30)上进行硅的外延生长，同时在所述晶种层(40)处生长多晶硅区(24)以及在所述衬底(30)的围绕所述晶种层(40)的表面区处生长单晶硅区(42)；
-在所述多晶硅区(24)中注入掺杂剂种类以用于形成至少部分地穿过所述多晶硅区(24)的导电路径(13)；以及
-将所述第二导电端子(22)电耦合至所述导电路径(13)，从而使得所述第二导电端子(22)可经由导电路径(13)从所述第一侧(12a)电接入。
2.根据权利要求1所述的方法，其中，形成所述晶种层(40)的所述步骤包括选择性地在所述凹部(38)中生长氧化硅，并且从而使得所述晶种层(40)被完全包含在所述凹部(38)内。
3.根据权利要求1或权利要求2所述的方法，其中，形成所述晶种层(40)的所述步骤包括：在所述凹部(38)中形成具有包括在500nm与2μm之间的基圆直径、以及包括在30nm与100nm之间的厚度的氧化硅层。
4.根据以上权利要求中任一项所述的方法，其中，形成所述凹部(38)的所述步骤包括在所述第二导电端子(22)处对所述衬底进行蚀刻，并且形成所述晶种层(40)的所述步骤包括形成嵌入地在所述第二导通端子(22)中的所述晶种层(40)。
5.根据以上权利要求中任一项所述的方法，其中，外延生长硅的所述步骤是在高于1000℃的温度下进行的。
6.根据以上权利要求中任一项所述的方法，其中，生长所述多晶硅区区(24)的所述步骤包括外延生长朝所述第一侧(12a)逐渐变尖的柱区。
7.根据以上权利要求中任一项所述的方法，其中，注入掺杂剂种类包括利用对应的注入能量进行多个注入，以便形成在对应深度处延伸的对应的多个注入区(44a-44c)。
8.根据权利要求7所述的方法，其中，所述注入区(44a-44c)中的至少一个到达所述多晶硅区(24)。
9.根据以上权利要求中任一项所述的方法，其中，将所述第二导电端子(22)电耦合至所述导电路径(13)的所述步骤包括进行热退火以用于扩散所述掺杂剂种类。
10.一种竖直导电器件(11)，包括：
-半导体本体(12)；
-第一导电端子(14)，所述第一导电端子在所述半导体本体(12)的第一侧(12a)处延伸；
-第二导电端子(22)，所述第二导电端子在所述半导体本体(12)的与所述第一侧(12a)相反的第二侧(12b)处延伸；
-控制端子(16)，所述控制端子可以被偏置用于在所述第一与第二导电端子(14，22)之间产生导电沟道(18)；
-氧化硅晶种层(40)；
-多晶硅区(24)，所述多晶硅区与所述晶种层(40)相接触地并在所述晶种层之上延伸；
-单晶硅区(42)，所述单晶硅区围绕所述晶种层(40)；以及
-注入区，所述注入区在所述半导体本体中在所述多晶硅区(24)中延伸，并且在所述器件(11)的所述第一侧与所述第二导电端子(22)之间形成导电路径(13)。
11.根据权利要求10所述的竖直导电器件，其中，所述第一导电端子是源极端子，所述第二导电端子是漏极端子，并且所述控制端子是所述器件(11)的栅极端子，
所述导电路径(13)是所述器件(11)的深度漏极扩散或漏极沉降。
12.根据权利要求10或权利要求11所述的竖直导电器件，其中，所述晶种层(40)在所述第二导电端子(22)内延伸。
13.根据权利要求10至12中任一项所述的竖直导电器件，其中，所述多晶硅区(24)具有朝所述第一侧(12a)逐渐变尖的柱形状。
14.根据权利要求10至13中任一项所述的竖直导电器件，其中，所述注入区在所述多晶硅区(24)内延伸。
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