GB2037487A - Method for producing an integrated semiconductor device - Google Patents
Method for producing an integrated semiconductor device Download PDFInfo
- Publication number
- GB2037487A GB2037487A GB7941857A GB7941857A GB2037487A GB 2037487 A GB2037487 A GB 2037487A GB 7941857 A GB7941857 A GB 7941857A GB 7941857 A GB7941857 A GB 7941857A GB 2037487 A GB2037487 A GB 2037487A
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- GB
- United Kingdom
- Prior art keywords
- stage
- substrate
- insulation
- zones
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- 239000010703 silicon Substances 0.000 claims abstract description 5
- 238000009413 insulation Methods 0.000 claims description 25
- 239000002019 doping agent Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 11
- 239000003153 chemical reaction reagent Substances 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- SYQQWGGBOQFINV-FBWHQHKGSA-N 4-[2-[(2s,8s,9s,10r,13r,14s,17r)-10,13-dimethyl-17-[(2r)-6-methylheptan-2-yl]-3-oxo-1,2,6,7,8,9,11,12,14,15,16,17-dodecahydrocyclopenta[a]phenanthren-2-yl]ethoxy]-4-oxobutanoic acid Chemical compound C1CC2=CC(=O)[C@H](CCOC(=O)CCC(O)=O)C[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2 SYQQWGGBOQFINV-FBWHQHKGSA-N 0.000 claims 1
- 238000002955 isolation Methods 0.000 abstract 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 6
- 229910052906 cristobalite Inorganic materials 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 229910052682 stishovite Inorganic materials 0.000 description 6
- 229910052905 tridymite Inorganic materials 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 101100434502 Oryza sativa subsp. japonica AGO7 gene Proteins 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000009027 insemination Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000006722 reduction reaction Methods 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02576—N-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Bipolar Transistors (AREA)
Abstract
In a method for producing an integrated semiconductor device which contains a vertical epitaxial planar NPN bipolar transistor and isolation columns on an epitaxially grown P-type substrate 1 of (100) orientation, a layer is provided which comprises semiconducting regions of polycrystalline silicon for isolation zones 7 and collector connector zones 8, and monocrystalline type silicon for the remaining parts. The polycrystalline and epitaxial layers are grown in three separate stages using chemical vapour deposition. In the first stage, collector connector zones 8 and isolation zones 7 are grown to a thickness of about 6000 ANGSTROM -8000 ANGSTROM , Fig. 5, at a growth rate of about 1 000 ANGSTROM /minute. The second layer extends beyond the areas already grown in the first stage to the remaining areas of the substrate, Fig. 6, to produce a layer 10 of about 30,000 ANGSTROM , thickness, at a growth rate of 2000 to 3000 ANGSTROM /minute. In the third growth stage, Fig. 7, a layer 12 is grown at a rate of 10,000 to 15,000 ANGSTROM /minute. <IMAGE>
Description
SPECIFICATION
Production method for integrated semiconductor devices
This invention relates to a production method for integrated semiconductor device which comprises at least one vertical NPN epitaxial bipolar transistor and a plurality of similar insulated junction elements on a substrate of
P conductivity and < 100 > crystallographic orientation, grown epitaxially with semiconductor regions of polycrystalline and moncrystalline type.
The improvement according to the invention relates in particular to the epitaxial growth stages.
The term "epitaxial growth" is substantially equivalent to growth from the vapour phase, and signifies the chemical reduction of a silicon compound by hydrogen at a determined temperature. The object of the invention is to enable a transistor of the aforesaid type to be designed which has its V(BR)CEO breakdown voltage fixed within the limit of 120 volts and its ICBO current and hFE current gain fixed at standard values.
The V(BR)CEO is known to be in direct ratio to the V(BR)CBOI and this is in direct ratio to the resistivity (p) of the useful epitaxial thickness in the collector zone, i.e. that lying between the maximum penetration of the base diffusion and the buried layer, and also in direct ratio to the effective value of this thickness.
Said thickness is substantially reduced, together with the resultant V(BR)CEO by the outdiffusion of the buried layer, which is the phenomenon by which this penetrates into the epitaxial layer. This penetration is greater the higher the temperature to which the assembly of semiconducting parts is raised during the epitaxial growth, and the higher the temperature of the subsequent diffusions thereto in accordance with the known planar method, and also the longer the duration of these diffusions. These diffusions must notably also include that for the junction insulation. It follows that the most rational method for obtaining maximum useful epitaxial thickness of the collector zone with a minimum of epitaxial thickness lost by out-diffusion is to reduce the diffusion times by increasing the speed of the diffusions in those zones where it is possible.Some processes based on the use of polycrystal for the collector deep diffusion (sinker) and insulation zones are known, in which the polycrystal is itself considered a means for obtaining rapid diffusions within these zones, and the principle is also known of epitaxially obtaining the polycrystal by previous insemination of polycrystalline nuclei using the method of growth in the vapour phase, and epitaxially growing the polycrystal and monocrystal together.
There are however actual difficulties in the simultaneous growth of the polycrystal and monocrystal, because of which the latter is of problematical and inferior quality, and thus of low production yield, because of the presence of various defects (stacking faults). Within the main aforesaid object, the present invention also has the object of increasing to a maximum the diffusion rate of the doping agents in the polycrystalline zones, by the effect of a method which enables a crystallographic orientation correlated with this maximum rate to be reproduced on an industrial scale, and allows a clean growth in the monocrystalline zones, i.e. without stacking faults, so obtaining the useful epitaxial thickness for the collector zone with a minimum of epitaxial thickness lost by out-diffusion.
According to one aspect of this invention there is provided a method for producing an integrated semiconductor device which contains at least one vertical epitaxial planar NPN bipolar transistor and junction insulation columns on an epitaxially grown substrate of P conductivity and < 100 > orientation with semiconducting regions of silicon which is of polycrystalline type with the same conductivity as the substrate for the insulation and collector sinker zones, and of monocrystalline type of opposite conductivity to the substrate for the remaining parts and a plurality of similar insulated junction elements, the epitaxial growth being split into three separate stages stabilised at three different temperatures, the first stage being limited in surface to the insulation and collector sinker areas and in thickness to about 6000A-8000A, obtained in the absence of a doping agent and at the first temperature of between 700 C and 800*C, the reagents being SiH4 and H in the proportion of 1/200 by volume and the growth rate about 1 000A/minute, the second stage extending beyond the areas already grown in the first stage to the remaining areas of the substrate, limited in thickness to about 30,000A, and carried out in the presence of a PH3 doping agent at the second temperature of about 11 00'C, the reagents being SiCI4 and H, and the growth rate 2000-3000A/ minute, the third stage, to the thickness fixed by the design requirements, being carried out at the third temperature of about 1 200 C with reagents of the same type as used for the second stage, but with a SiCI4 concentration greater than that of the second stage, to give a a growth rate of between 10,000 and 1 5,000A/minute, the second and third stages being spaced apart by only the time necessary for the epitaxial reactor to pass from the second to the third stabilised reaction temperature.
According to another aspect of this invention there is provided an integrated semiconductor device produced by the stated method.
A method according to this invention will now be described, by way of example, with reference to the accompanying drawings of which only Figs. 4, 6 and 7 relate to the novel part of the method. The dimensions of the layers and of the apertures shown on the figures are not to scale. In the Figures::~
Figure 1 shows the insulation mask;
Figure 2 shows the insulation predoping;
Figure 3 shows the sinker aperture;
Figure 4 shows the first stage of the epitaxiat deposit according to the invention;
Figure 5 shows the definition of the geometrical outlines set by the first stage;
Figure 6 shows the second stage of the epitaxial deposit according to the invention;
Figure 7 shows the third stage of the epitaxial deposit according to the invention;
Figure 8 shows the upper doping of the insulation columns;
Figure 9 shows the diffusion of the insulation doping agent;
Figure 10 shows the formation of the base zone;
Figure II shows the formation of the emitter zone and the completion of the sinker.
Fig. 1~The substrate 1 formed from P silicon is already prepared with a N + doped buried layer 2 and with a SiO2 mask 3 provided with apertures 4 only in the monocrys tal zones for the formation of the insulation.
This is the known art.
Fig. 2~The substrate is P+ predoped at the base 5 of the insulation columns through the apertures 4 shown in Fig. 1. This is the known art.
Fig. 3 - Opening the sinker geometrical outline 6 through the SiO2 mask 3 within the buried layer area 2. This is the known art.
Fig. 4 - Epitaxial deposition (first stage) of the polycrystalline silicon over the entire surface comprising the mask 3 with apertures 4 and 6. The general concept of the operation is the known art, but the conditions with a view to obtaining the dominant < 110 > orientation in the polycrystal for effecting the invention in association with the subsequent operations are as follows: thickness between 6000A-8000A, temperature between 7Q0 C and 800 C, reagents SiH4 and H in the proportion of 1/200 by volume, and growth rate 1000W/minute.
Fig. 5 - Defination of the geometrical outlines set by the first stage. The figure shows only the result of the operations. All the poly silicon obtained by the operation shown in
Fig. 4 is covered with Six2', this second oxide is masked with photoresist in order to protect the zones of the second SiO2 overlying the polysilicon contained in the apertures 4 and 6; the second oxide is chemically attacked and is elimated from the areas not protected by the photoresist, the polycrystal is chemically attacked and eliminated, and thus becomes uncovered; the photoresist is removed and the entire remaining oxide is chemically attacked until it is totally removed. At the end, the geometrical outlines of the insulation 7 and sinker 8 remain in relief of the substrate.
All the indicated operations are the known art.
Only the nature of the < 110 > orientated polycrystal with a thickness of between 6000 and 8000 , 9, deriving from the operation indicated as the first stage, relates to the invention.
Fig. 6 - Epitaxial deposition (second stage).
This is an epitaxial growth 10 limited to a finished thickness of about 3O,000A (measured on the monocrystal) over both the areas on which the polycrystal has to grow, and the areas on which the monocrystal has to grow. The growth conditions are: reaction temperature about 1100"C, reagents SiC14 and H, with PH3 as doping agent, growth rate 2000-3000A/minute.
This limited growth, with its reaction conditions, is a component of the invention in view of the subsequent growth with different reaction conditions. During this stage, the diffusion of the insulation zones 7 and sinker zone 8 begin, with a partial out-diffusion of the buried layer, as shown in Fig. 11.
Fig. 7 - Epitaxial deposition (third stage).
This is a limited epitaxial growth 12 between the thickness of about 30,000A already obtained with the second stage, and the total thickness necessary for the device. By way of example, in a device having a minimum V(BR)CEO of 100 Volts, this thickness would have to be 210,000-250,000 in total. The growth conditions for this third stage are quite different from those of the second. The temperature rises to about 1200'C and the growth rate to 10,000-15,000 /minute, not only because of the increased temperature but also because of an increase in the content of SiC14 relative to H, in comparison with that of the preceding stage (second epitaxial growth) but, with the same doping agent.In this third stage there is further diffusion in the insulation zones 7 and sinker zone 8, with further out-diffusion of the buried layer. The special growth conditions for the third stage are also an essential component of the invention. Passage from the second to the third stage of epitaxial growth takes place over the strictly necessary time required by the epitaxial reactor to reach the new stabilised temperature required for the third stage.
Fig. 8~Upper doping of the insulation columns. This operation is carried out following the known art. The figure shows only the intermediate stage, in which the P doping agent applied to the apertures 7' has not yet diffused. The figure shows these apertures provided in a layer 13 of SiO2, which is prepared after the third epitaxial growth, then masked with a photoresist and then chemically attacked. This SiO2 layer is formed thermally.
Fig. 9~Diffusion of the insulation doping agent. The method is the known art. Only the predominating presence of < 100 > orientation in the polycrystal obtained with the three epitaxial growth stages on the < 100 > substrate relates to the invention. Fig. 9 shows how the diffusion of the various zones and the out-diffusion of the buried layer proceed. Not only does the doping agent applied at the top of the insulation columns move towards the substrate, but the doping agent P applied previously in position 5 of Fig. 2 also moves towards the zone lying immediately below the apertures 7'. The diffusion of the sinker also extends into its own polycrystal column, and the out-diffusion of the buried layer 14 extends into the monocrystal.The apertures 7' become closed by the effect of the oxidising atmosphere in which the operation according to the known art takes place.
Fig. 10~Formation of the base zone. This step is also carried out in accordance with the known art, by photoresist masking and chemical attack of the oxide in order to open the upper layer 13 of SHO2 on the base zone 15, then P surface doping and diffusing this doping agent. Simultaneously with the opening of the aperture 15, the apertures 7', which were closed during the insulation diffusion, are reopened to allow a further charge of P doping agent into the insulation columns. Fig. 10 shows the diffused base zone 16 obtained on termination of the base diffusion.
Fig 11~Formation of the emitter zone and completion of the sinker. The upper SiO2 layer is closed over the base and insulation areas by the known method, and is then reopened at the polycrystalline sinker column 17 and at the emitter zone 18. A N+ doping agent, introduced through the apertures 17, 18, is then diffused in order to form the emitter zone 19 and to complete the sinker 20. The figures do not show any of the subsequent operational steps necessary for completing the device in accordance with the known art before its assembly in the package, i.e. formation of contacts, metallisation of contacts, or the protection of all active zones against superficial degradation.
Claims (5)
1. A method for producing an integrated semiconductor device which contains at least one vertical epitaxial planar NPN bipolar transistor and junction insulation columns on an epitaxially grown substrate of P conductivity and < 100 > orientation with semiconducting regions of silicon which is of polycrystalline type with the same conductivity as the substrate for the insulation and collector sinker zones, and of monocrystalline type of opposite conductivity to the substrate for the remaining parts, and a plurality of similar insulated junction elements, the epitaxial growth being split into three separate stages stabilised at three different temperatures, the first stage being limited in surface to the insulation and collector sinker areas and in thickness to about 6000A-8000A, obtained in the absence of a doping agent and at the first temperature of between 700 C and 800 C, the reagents being SiH4 and H in the proportion of 1/200 by volume and the growth rate about 1 000A/mi- nute, the second stage extending beyond the areas already grown in the first stage to the remaining area of the substrate, limited in thickness to about 30,OOOA, and carried out in the presence of a PH3 doping agent at the second temperature of about 1100 C, the reagents being SiCI4 and H, and the growth rate 2000-3000 /minute, the third stage, to the thickness fixed by the design requirements, being carried out at the third temperature of about 1200 C with reagents of the same type as used for the second stage, but with a SiCI4 concentration greater than that of the second stage, to give a growth rate of between 10,000 and 1 5,000A/minute, the second and third stages being spaced apart by only the time necessary for the epitaxial reactor to pass from the second to the third stabilised reaction temperature.
2. A method for producing an integrated semiconductor device which contains at least one vertical epitaxial planar NPN bipolar trans- istor and junction insulation columns substantially as hereinbefore described with reference to the accompanying drawings.
3. An integrated semiconductor device produced by a method as claimed in claim 1 or claim 2.
4. A device as claimed in claim 3, wherein the polycrystalline silicon of the insulation and collector sinker zones has predominating < 110 > crystallographic orientation, and the substrate silicon is of < 100 > orientation.
5. An integrated semiconductor device substantially as hereinbefore described with reference to Fig. 11 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT30507/78A IT1101183B (en) | 1978-12-04 | 1978-12-04 | IMPROVEMENT IN THE PRODUCTION PROCESS FOR BIPOLAR TRANSISTORS INTAGRATED WITH HIGH BREAKDOWN VOLTAGE COLLECTOR-EMITTER AND RESULTING PRODUCT |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2037487A true GB2037487A (en) | 1980-07-09 |
Family
ID=11229874
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB7941857A Withdrawn GB2037487A (en) | 1978-12-04 | 1979-12-04 | Method for producing an integrated semiconductor device |
Country Status (5)
| Country | Link |
|---|---|
| DE (1) | DE2948800A1 (en) |
| FR (1) | FR2443742A1 (en) |
| GB (1) | GB2037487A (en) |
| IT (1) | IT1101183B (en) |
| SE (1) | SE454631B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT201600130185A1 (en) * | 2016-12-22 | 2018-06-22 | St Microelectronics Srl | PROCESS OF MANUFACTURING A SEMICONDUCTOR DEVICE INTEGRATING A VERTICAL CONDUCTIVE TRANSISTOR, AND SEMICONDUCTOR DEVICE |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1300768A (en) * | 1969-07-29 | 1972-12-20 | Fairchild Camera Instr Co | Improvements in or relating to semiconductor structures |
-
1978
- 1978-12-04 IT IT30507/78A patent/IT1101183B/en active
-
1979
- 1979-12-03 SE SE7909953A patent/SE454631B/en not_active IP Right Cessation
- 1979-12-04 GB GB7941857A patent/GB2037487A/en not_active Withdrawn
- 1979-12-04 DE DE19792948800 patent/DE2948800A1/en not_active Withdrawn
- 1979-12-04 FR FR7929737A patent/FR2443742A1/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT201600130185A1 (en) * | 2016-12-22 | 2018-06-22 | St Microelectronics Srl | PROCESS OF MANUFACTURING A SEMICONDUCTOR DEVICE INTEGRATING A VERTICAL CONDUCTIVE TRANSISTOR, AND SEMICONDUCTOR DEVICE |
| CN108231886A (en) * | 2016-12-22 | 2018-06-29 | 意法半导体股份有限公司 | Manufacture the method and semiconductor devices of semiconductor devices |
| US10141422B2 (en) | 2016-12-22 | 2018-11-27 | Stmicroelectronics S.R.L. | Method of manufacturing a semiconductor device integrating a vertical conduction transistor, and semiconductor device |
| CN108231886B (en) * | 2016-12-22 | 2021-06-04 | 意法半导体股份有限公司 | Method of manufacturing semiconductor device and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| DE2948800A1 (en) | 1980-06-19 |
| FR2443742A1 (en) | 1980-07-04 |
| IT7830507A0 (en) | 1978-12-04 |
| SE454631B (en) | 1988-05-16 |
| FR2443742B1 (en) | 1985-03-08 |
| SE7909953L (en) | 1980-06-05 |
| IT1101183B (en) | 1985-09-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |