CN108231595A - 薄膜晶体管及其制备方法、阵列基板、显示装置 - Google Patents

薄膜晶体管及其制备方法、阵列基板、显示装置 Download PDF

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CN108231595A
CN108231595A CN201810001897.8A CN201810001897A CN108231595A CN 108231595 A CN108231595 A CN 108231595A CN 201810001897 A CN201810001897 A CN 201810001897A CN 108231595 A CN108231595 A CN 108231595A
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insulating layer
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CN108231595B (zh
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班圣光
曹占锋
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BOE Technology Group Co Ltd
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Abstract

本申请公开了一种薄膜晶体管及其制备方法、阵列基板、显示装置。该薄膜晶体管，包括：遮光图案，第一绝缘层，有源层图案，第二绝缘层，栅极图案，层间绝缘层，与有源层图案分别连接的源极和漏极；源极和漏极还与遮光图案连接。根据本申请实施例的技术方案，通过源极和漏极与遮光图案连接，将遮光图案感生的电荷传导至外部电路，可以排除遮光图案感生电荷的影响，提升阈值电压的稳定性，改善薄膜晶体管的特征。

Description

薄膜晶体管及其制备方法、阵列基板、显示装置
技术领域
本公开涉及显示技术领域，尤其涉及一种薄膜晶体管及其制备方法、阵列基板、显示装置。
背景技术
随着显示技术的发展，低温多晶硅(Low Temperature Poly-silicon，LTPS)技术越来越受到广泛的重视。LTPS技术由于其高迁移率以及可以实现阵列基板栅极驱动(GateDriver on Array，GOA)的原因，使得基于该技术的显示面板相比于非晶硅(a-Si)技术的显示面板在开口率、亮度及反应速度等方面具有更加优良的显示效果。
发明内容
现有的LTPS工艺中，需要制作遮光层来避免有源层接受到光照，进而影响薄膜晶体管的开关性能。然而，发明人发现，遮光层在薄膜晶体管工作时会受到栅极电压的影响，在靠近栅极的表面产生感应电荷，而遮光层在阵列基板上呈孤岛设置，感应电荷无法消除，从而会影响薄膜晶体管有源层的沟道区域正常工作，造成薄膜晶体管阈值电压漂移。
鉴于现有技术中的上述缺陷或不足，期望提供一种薄膜晶体管及其制备方法、阵列基板、显示装置，既可以有效排除遮光层的感应电荷，改善薄膜晶体管特性，又具有较低的制备成本。
第一方面，本申请实施例提供了一种薄膜晶体管，包括：
遮光图案，
第一绝缘层，
有源层图案，
第二绝缘层，
栅极图案，
层间绝缘层，
与有源层图案分别连接的源极和漏极；
源极和漏极还与遮光图案连接。
第二方面，本申请实施例还提供了一种薄膜晶体管的制备方法，包括：
形成遮光层、第一绝缘层和有源层的多层结构；
通过一次构图工艺对所述多层结构进行图案化处理，形成遮光图案和有源层图案；
形成第二绝缘层；
形成栅极图案；
形成层间绝缘层；
形成贯穿层间绝缘层、第二绝缘层、有源层图案、第一绝缘层的第一过孔和第二过孔；
形成源极和漏极，源极和漏极分别通过第一过孔和第二过孔与第一有源层以及遮光图案连接。
第三方面，本申请实施例还提供了一种阵列基板，包括多个阵列设置的本申请各实施例提供的薄膜晶体管。
第四方面，本申请实施例还提供了一种显示装置，该显示装置包括本申请各实施例提供的阵列基板。
本申请实施例提供的薄膜晶体管，通过源极和漏极与遮光图案连接，将遮光图案感生的电荷传导至外部电路，可以排除遮光图案感生电荷的影响，提升阈值电压的稳定性，改善薄膜晶体管的特征。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显：
图1示出了根据本申请实施例的薄膜晶体管的结构示意图；
图2示出了根据本申请一实施例的薄膜晶体管的结构示意图；
图3示出了根据本申请一实施例的薄膜晶体管的结构示意图；以及
图4示出了根据本申请实施例的薄膜晶体管制备方法的示例性流程图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关发明，而非对该发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与发明相关的部分。
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性连接或信号连接，不管是直接的还是间接的。
图1示出了根据本申请实施例的液晶光栅的结构示意图。
如图1所示，一种薄膜晶体管，包括：
遮光图案12，
第一绝缘层13，
有源层图案14，
第二绝缘层15，
栅极图案16，
层间绝缘层17，
与有源层图案14分别连接的源极18和漏极19；
源极18和漏极19还与遮光图案12连接。
本实施例中，遮光图案12、第一绝缘层13、有源层图案14、第二绝缘层15、栅极图案16、层间绝缘层17、源极18和漏极19各个层均位于基板11上，各个层之间的位置关系并不局限于图1所示的顶栅结构，也可以是底栅结构或其他结构的薄膜晶体管。第一绝缘层13、第二绝缘层15及层间绝缘层17可以包括氧化硅、氮化硅以及两者的混合物等透明绝缘材料。
在薄膜晶体管工作过程中，对栅极图案加电压后，有源层图案靠近栅极图案侧的一面感应出负电荷，远离栅极图案侧的一面感应出正电荷。而遮光图案与有源层图案之间的绝缘层厚度较小，因此遮光图案靠近有源层图案侧的一面感应出负电荷，从而影响下次加薄膜晶体管工作时有源层图案的电荷分配，使得阈值电压偏负。
本实施例中，由于源漏电极与有源层图案连接的同时还与遮光图案相连接，可以将遮光图案的感应电荷导出去，从而可以避免遮光图案感生电荷对薄膜晶体管的影响，提升薄膜晶体管阈值电压的稳定性，改善薄膜晶体管的特征。
进一步地，遮光图案的材料为硅单质或氧化物半导体。
具体地，硅单质可以为单晶硅、非晶硅等非透明硅单质材料，氧化物半导体可以为氧化铝、氧化钛等非透明氧化物半导体材料。
源漏电极与有源层图案连接的同时还与遮光图案相连接，可以让有源层图案和源漏电极处于同一电势，可以提升薄膜晶体管的稳定性。
进一步地，遮光图案的材料为非晶硅，由于源漏电极和非晶硅遮光层图案连接，由于非晶硅的阻值很大，且其与源漏电极接触的表面并没有形成欧姆接触，所以非晶硅不会形成沟道。此外，薄膜晶体管关闭后，关闭电流在E-12量级，非晶硅遮光层图案的存在不会造成薄膜晶体管的漏电。
进一步地，有源层图案的材料为多晶硅。
进一步地，第一绝缘层位于遮光图案上；
有源层图案位于第一绝缘层上；
第二绝缘层位于有源层图案上；
栅极图案位于所示第二绝缘层上；
层间绝缘层位于栅极图案上；
源极和漏极分别通过过孔与有源层图案和遮光图案连接；
过孔贯穿层间绝缘层、第二绝缘层、有源层图案和第一绝缘层。
本申请实施例中，遮光图案12、第一绝缘层13、有源层图案14、第二绝缘层15、栅极图案16、层间绝缘层17、源极18和漏极19可以形成如图1所示由下而上的层叠位置关系，也就是说可以是顶栅结构。过孔可以为任意贯穿层间绝缘层、第二绝缘层、有源层图案和第一绝缘层的结构。
图2示出了根据本申请一实施例的薄膜晶体管的结构示意图。
如图2所示，进一步地，每个过孔28(29)可以包括第一子过孔281(291)和第二子过孔282(292)，其中，第一子过孔281(291)贯穿层间绝缘层和第二绝缘层，第二子过孔282(292)贯穿有源层图案和第一绝缘层。本实施例中，每个过孔实际上包括两个子过孔，可以减小工艺难度，同时增大源极和漏极与有源层图案的接触面积，改善薄膜晶体管的特性。
图3示出了根据本申请一实施例的薄膜晶体管的结构示意图。
如图3所示，进一步地，第一绝缘层33位于栅极图案32上；
有源层图案34位于第一绝缘层33上；
第二绝缘层35位于有源层图案34上；
遮光图案36位于所示第二绝缘层35上；
层间绝缘层37位于遮光图案36上；
源极38和漏极39分别通过过孔与有源层图案34和遮光图案36连接；
过孔贯穿层间绝缘层37、遮光图案36和第二绝缘层35。
本申请实施例中，栅极图案32、第一绝缘层33、有源层图案34、第二绝缘层35、遮光图案36、层间绝缘层37、源极38和漏极39可以形成如图3所示由下而上的层叠位置关系，也就是说可以是底栅结构。过孔可以为任意贯穿层间绝缘层、第二绝缘层、有源层图案和第一绝缘层的结构。可以理解的是，过孔可以包括两个或多个子过孔。
图4示出了本申请实施例提供的一种薄膜晶体管的制备方法，包括：
步骤S10：形成遮光层、第一绝缘层和有源层的多层结构。
本步骤中，可以在基板上采用PECVD(Plasma Enhanced Chemical VaporDeposition，等离子体增强化学的气相沉积)方法形成遮光层；同样可采用PEVCD方法在遮光层上依次形成第一绝缘层和有源层。
步骤S20：通过一次构图工艺对所述多层结构进行图案化处理，形成遮光图案和有源层图案。
本步骤中，可以对上步所形成的多层结构通过一次构图工艺进行刻蚀，使遮光层形成遮光图案，有源层形成有源层图案。
步骤S30：形成第二绝缘层。
本步骤中，可以在有源图案上采用PECVD方法形成第二绝缘层。
步骤S40：形成栅极图案。
本步骤中，可以先在第二绝缘层上通过溅射形成栅极层，再通过一次构图工艺形成栅极图案。
步骤S50：形成层间绝缘层。
在本步骤中，可以在栅极图案上采用PECVD方法形成层间绝缘层。
步骤S60：形成贯穿层间绝缘层、第二绝缘层、有源层图案、第一绝缘层的第一过孔和第二过孔。
本步骤中，第一过孔和第二过孔可以通过一步刻蚀形成，也可以通过多步刻蚀形成。具体地，多步刻蚀可以为先通过刻蚀形成贯穿层间绝缘层、第二绝缘层、有源层图案、第一绝缘层的第一过孔和第二过孔，再通过刻蚀对贯穿层间绝缘层和第二绝缘层部分的过孔进行拓宽，从而实现增大源极和漏极与有源层图案的接触面积的效果。
进一步地，步骤S60还包括：
形成贯穿层间绝缘层和第二绝缘层的两个第一子过孔后，再形成差贯穿有源层图案和第一绝缘层的两个第二子过孔。
步骤S70：形成源极和漏极，源极和漏极分别通过第一过孔和第二过孔与第一有源层以及遮光图案连接。
上述实施例中，通过步骤S10和S20，将遮光层和有源层整合在一起，并通过一次构图工艺形成遮光图案和有源层图案，减少了一次构图工艺，降低了生成成本；同时，通过形成贯穿层间绝缘层、第二绝缘层、有源层图案、第一绝缘层的第一过孔和第二过孔，使得源极和漏极与遮光图案连接，将遮光图案感生的电荷传导至外部电路，可以排除遮光图案感生电荷的影响，提升阈值电压的稳定性，改善薄膜晶体管的特征。
进一步地，本申请实施例还提供了一种阵列基板，包括多个阵列设置的本申请各实施例提供的薄膜晶体管。
进一步地，本申请实施例还提供了一种显示装置，该显示装置包括本申请各实施例提供的阵列基板。
以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本申请中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (9)

1.一种薄膜晶体管，其特征在于，包括：
遮光图案，
第一绝缘层，
有源层图案，
第二绝缘层，
栅极图案，
层间绝缘层，
与所述有源层图案分别连接的源极和漏极；
所述源极和所述漏极还与所述遮光图案连接。
2.根据权利要求1所述的薄膜晶体管，其特征在于，所述遮光图案的材料为非晶硅。
3.根据权利要求1所述的薄膜晶体管，其特征在于，所述有源层图案的材料为多晶硅。
4.根据权利要求3所述的薄膜晶体管，其特征在于，所述第一绝缘层位于所述遮光图案上；
所述有源层图案位于所述第一绝缘层上；
所述第二绝缘层位于所述有源层图案上；
所述栅极图案位于所示第二绝缘层上；
所述层间绝缘层位于所述栅极图案上；
所述源极和所述漏极分别通过过孔与所述有源层图案和所述遮光图案连接；
所述过孔贯穿所述层间绝缘层、所述第二绝缘层、所述有源层图案和所述第一绝缘层。
5.根据权利要求3所述的薄膜晶体管，其特征在于，所述第一绝缘层位于所述栅极图案上；
所述有源层图案位于所述第一绝缘层上；
所述第二绝缘层位于所述有源层图案上；
所述遮光图案位于所示第二绝缘层上；
所述层间绝缘层位于所述遮光图案上；
所述源极和所述漏极分别通过过孔与所述有源层图案和所述遮光图案连接；
所述过孔贯穿所述层间绝缘层、所述遮光图案和所述第二绝缘层。
6.一种薄膜晶体管的制备方法，其特征在于，包括：
形成遮光层、第一绝缘层和有源层的多层结构；
通过一次构图工艺对所述多层结构进行图案化处理，形成遮光图案和有源层图案；
形成第二绝缘层；
形成栅极图案；
形成层间绝缘层；
形成贯穿所述层间绝缘层、所述第二绝缘层、所述有源层图案、所述第一绝缘层的第一过孔和第二过孔；
形成源极和漏极，所述源极和所述漏极分别通过所述第一过孔和所述第二过孔与所述有源层图案以及遮光图案连接。
7.根据权利要求6所述的制备方法，其特征在于，所述形成贯穿所述层间绝缘层、所述第二绝缘层、所述有源层图案、所述第一绝缘层的第一过孔和第二过孔，包括：
形成贯穿所述层间绝缘层和所述第二绝缘层的两个第一子过孔后，再形成贯穿所述有源层图案和所述第一绝缘层的两个第二子过孔。
8.一种阵列基板，其特征在于，包括多个阵列设置的所述如权利要求1-5任一所述的薄膜晶体管。
9.一种显示装置，其特征在于，包括如权利要求8所述的阵列基板。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019134475A1 (zh) * 2018-01-02 2019-07-11 京东方科技集团股份有限公司 薄膜晶体管及其制备方法以及阵列基板和显示装置
CN110854140A (zh) * 2019-12-10 2020-02-28 京东方科技集团股份有限公司 一种阵列基板及其制备方法，显示面板、显示装置
US11094721B2 (en) 2018-06-28 2021-08-17 Boe Technology Group Co., Ltd. Method for manufacturing array substrate including forming via holes having different widths using single patterning process
CN113540123A (zh) * 2021-06-30 2021-10-22 厦门天马微电子有限公司 阵列基板、显示面板及显示装置
CN113782616A (zh) * 2019-01-10 2021-12-10 合肥鑫晟光电科技有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113327936B (zh) * 2021-05-24 2022-08-23 武汉华星光电技术有限公司 阵列基板及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102299163A (zh) * 2011-09-13 2011-12-28 上海中科高等研究院 图像传感器
CN105470267A (zh) * 2016-01-11 2016-04-06 武汉华星光电技术有限公司 一种阵列基板及其制备方法
KR20160080954A (ko) * 2014-12-30 2016-07-08 엘지디스플레이 주식회사 박막트랜지스터 어레이 기판 및 그의 제조방법
CN107068770A (zh) * 2017-05-04 2017-08-18 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示面板
KR20170135550A (ko) * 2016-05-31 2017-12-08 엘지디스플레이 주식회사 유기발광 표시장치 및 그의 제조방법

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3708637B2 (ja) * 1996-07-15 2005-10-19 株式会社半導体エネルギー研究所 液晶表示装置
CN108231595B (zh) * 2018-01-02 2020-05-01 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板、显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102299163A (zh) * 2011-09-13 2011-12-28 上海中科高等研究院 图像传感器
KR20160080954A (ko) * 2014-12-30 2016-07-08 엘지디스플레이 주식회사 박막트랜지스터 어레이 기판 및 그의 제조방법
CN105470267A (zh) * 2016-01-11 2016-04-06 武汉华星光电技术有限公司 一种阵列基板及其制备方法
KR20170135550A (ko) * 2016-05-31 2017-12-08 엘지디스플레이 주식회사 유기발광 표시장치 및 그의 제조방법
CN107068770A (zh) * 2017-05-04 2017-08-18 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示面板

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019134475A1 (zh) * 2018-01-02 2019-07-11 京东方科技集团股份有限公司 薄膜晶体管及其制备方法以及阵列基板和显示装置
US11094721B2 (en) 2018-06-28 2021-08-17 Boe Technology Group Co., Ltd. Method for manufacturing array substrate including forming via holes having different widths using single patterning process
CN113782616A (zh) * 2019-01-10 2021-12-10 合肥鑫晟光电科技有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置
CN113782616B (zh) * 2019-01-10 2024-01-16 合肥鑫晟光电科技有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置
CN110854140A (zh) * 2019-12-10 2020-02-28 京东方科技集团股份有限公司 一种阵列基板及其制备方法，显示面板、显示装置
CN110854140B (zh) * 2019-12-10 2022-06-03 京东方科技集团股份有限公司 一种阵列基板及其制备方法，显示面板、显示装置
CN113540123A (zh) * 2021-06-30 2021-10-22 厦门天马微电子有限公司 阵列基板、显示面板及显示装置

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