CN108230222A

CN108230222A - A kind of OpenGL shows list call circuit

Info

Publication number: CN108230222A
Application number: CN201711283982.XA
Authority: CN
Inventors: 郝冲; 牛少平; 邓艺; 魏艳艳; 韩鹏; 韩一鹏
Original assignee: Xian Aeronautics Computing Technique Research Institute of AVIC
Current assignee: Xian Aeronautics Computing Technique Research Institute of AVIC
Priority date: 2017-12-06
Filing date: 2017-12-06
Publication date: 2018-06-29

Abstract

The invention belongs to area of computer graphics, are related to a kind of OpenGL and show list call circuit, including：Pre-decode reads interface 1, reads buffering FIFO2, AXI logic interfacing 3；Pre-decode reads interface 1, the reading request signal sent for pre-decode unit 4 is detected, such as the reading request signal is effective, OpenGL is then set to show that it is effective to read list state in list call circuit, storage address and list byte-sized information of the list in DDR5 are obtained from pre-decode unit 4, and burst length when thus list byte-sized information determines to read DDR5；Buffering FIFO2 is read, when reading list state is effective, if pempty indication signals are effective, reading DDR5 sent and asks to AXI logic interfacings 3；When reading buffering FIFO2 non-emptys, pre-decode reads interface 1 and the table data that caching is read in FIFO2 is buffered from reading；AXI logic interfacings 3 carry out read access operation to DDR5 by standard AXI interfaces, generate table data and word corresponding with table data enables, and word is enabled and is written to reading buffering FIFO2 together with table data.

Description

A kind of OpenGL shows list call circuit

Technical field

The invention belongs to area of computer graphics, are related to a kind of display list call instruction processing circuit to OpenGL It realizes.

Background technology

In area of computer graphics, display list is to solve the problems, such as unnecessary repetition rendering, buffered from order One piece of precalculated data is taken out in area, they are responsible for performing the task of some repeatability, such as draw anchor ring, this block Data can copy back into command buffer at any time later, this block number is created according to required a large amount of function calls and compiling so as to save Expense.To display list call when because pre-decode unit 4 handle graph command be sequence perform, can only one by one into Row in order to avoid carrying out frequent read access to DDR buses, increases this display row between pre-decode unit 4 and DDR5 Table call circuit.

Invention content

The purpose of the present invention is：

The present invention provides a kind of OpenGL and shows list call circuit, for reading data from DDR, so as to being stored in Display table data in DDR is called.

The present invention technical solution be：

A kind of OpenGL shows list call circuit, including：Pre-decode reads interface 1, reads buffering FIFO2, AXI logic interfacing 3；

Pre-decode reads interface 1, and the reading request signal sent for pre-decode unit 4 is detected, such as the reading request signal Effectively, then OpenGL is set to show that it is effective to read list state in list call circuit, obtaining list from pre-decode unit 4 exists Storage address and list byte-sized information in DDR, and thus list byte-sized information determine read DDR when burst long Degree；

Read buffering FIFO2, read list state it is effective when, if pempty indication signals are effective, send read DDR ask to AXI logic interfacings 3；When reading buffering FIFO2 non-emptys, pre-decode reads interface 1 and the list number that caching is read in FIFO2 is buffered from reading According to；

AXI logic interfacings 3, by standard AXI interfaces to DDR carry out read access operation, generate table data and with list number It is enabled according to corresponding word, and word is enabled and is written to reading buffering FIFO2 together with table data.

It is 32b to read FIFO depth in buffering FIFO2, and data width 264b, pempty are set as 16；The high 8b conducts of data The word of low 256b enables.

The read access operation information of AXI logic interfacings 3 includes the reading address valid signal of 1b, 4b read channels ID, 30b read ground Location, the reading burst length of 4b；1b read channels ready signal is then included to the reading response of the read access operation information, 4b reads to lead to The rlast signals of the table data of road ID, 256b, the data valid signal of 1b and 1b.

It is as follows to read the method that address generates：First address of reading is generated by " base address "+" address offset that pre-decode is sent ", Thereafter address is updated according to the size length read every time.

The producing method for reading burst length is as follows：When being 0 for low 7 that read address, show that it is 512 bytes pair to read address Together, list_arlen is only related with the length clist_size of list at this time；If low 7 that read address are not 0, need first to read One segment length is the data of size_burst, and low 7 that read address are gathered as 0；Compare size_burst and clist_size Size, if read list length be more than size_burst, at this time list_arlen generated by size_burst；Otherwise it still uses Clist_size is generated.

It is an advantage of the invention that：The present invention provides a kind of circuit realizations that data and buffering are read for DDR, are used to implement It is read in the slave DDR5 of pre-decode unit 4 rapidly and efficiently and shows table data.

Description of the drawings

Fig. 1 is the method module map of the present invention.

Specific embodiment

In order to make the purpose , technical scheme and advantage of the present invention be clearer, below in conjunction with example, the present invention is made It is further described.It should be appreciated that specific example described herein is only used to explain the present invention, it is not used to limit this Invention.

Technical scheme of the present invention is described in further detail in the following with reference to the drawings and specific embodiments.

Pre-decode reads interface 1, and the reading request signal sent for pre-decode unit 4 is detected, such as the reading request signal Effectively, then OpenGL is set to show that it is effective to read list state in list call circuit, obtaining list from pre-decode unit 4 exists Storage address and list byte-sized information in DDR5, and thus list byte-sized information determine read DDR5 when burst Length；

Buffering FIFO2 is read, when reading list state is effective, if pempty indication signals are effective, send and reads DDR5 requests To AXI logic interfacings 3；When reading buffering FIFO2 non-emptys, pre-decode reads interface 1 and the list number that caching is read in FIFO2 is buffered from reading According to；

AXI logic interfacings 3 carry out read access operation to DDR5 by standard AXI interfaces, generate table data and and list The corresponding word of data enables, and word is enabled and is written to reading buffering FIFO2 together with table data.

It is as follows to read the method that address generates：First address of reading is by " base address "+" address offset that pre-decode unit 4 is sent " It generates, address thereafter is updated according to the size length read every time.

Embodiment

As shown in Figure 1, a kind of show that the circuit of list commands data is realized for reading in DDR5, possess pre-decode reading and connect Mouth 1 reads the part such as buffering FIFO2, AXI logic interfacing 3 composition.

A) pre-decode reads interface 1：When receiving the read request that pre-decode unit 4 is sent out, list state indication signal is read in setting Effectively, if reading buffering FIFO2 non-emptys at this time, the data read in buffering FIFO2 are output to pre-decode unit 4；If read list Read request is received when state is effective, it is known that occur list nesting in pre-decode unit 4, need to generate reading FIFO reset signals will Buffering FIFO2 is read to reset；

B) buffering FIFO2 is read：When reading list state indication signal is effective, if pempty is effective, initiate to read behaviour to DDR5 Make；If FIFO reset signals are effective, reading buffering FIFO2 is emptied；It, can be by pre-decode list when reading to buffer FIFO2 non-emptys Member 4 reads table data；

C) it according to the address offset of the offer of pre-decode unit 4 and the size clist_size of list size, determines to read Address and reading burst length；When the data read from DDR5 are effective, the number of buffering FIFO2 is read according to size and write-in, is determined Go out and enabled with the corresponding word of each data, and word is enabled into 264b write-ins spliced with data and reads buffering FIFO2；

It is as follows to read the method that address generates：First address of reading is by " base address "+" address offset that pre-decode unit 4 is sent " It generates, address thereafter is updated according to the size length read every time；

The producing method for reading burst length is as follows：To avoid the problem that across DDR5 address boundary, the length of burst is read It need to assist to determine according to current reading address.When being 0 for low 7 that read address, show that it is 512 byte-aligneds to read address, this When list_arlen only it is related with the length clist_size of list；If low 7 that read address are not 0, need first to read one section Length is the data of size_burst, and low 7 that read address are gathered as 0；Compare the big of size_burst and clist_size Small, if the length for reading list is more than size_burst, list_arlen is generated by size_burst at this time；Otherwise it still uses Clist_size is generated.

Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although The present invention is explained in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that：It still may be used To modify to the technical solution recorded in foregoing embodiments or carry out equivalent replacement to which part technical characteristic； And these modification or replace, various embodiments of the present invention technical solution that it does not separate the essence of the corresponding technical solution spirit and Range.

Claims

1. a kind of OpenGL shows list call circuit, which is characterized in that including：Pre-decode reads interface (1), reads buffering FIFO (2), AXI logic interfacings (3)；

Pre-decode reads interface (1), and the reading request signal sent for pre-decode unit (4) is detected, such as the reading request signal Effectively, then OpenGL is set to show that it is effective to read list state in list call circuit, obtaining list from pre-decode unit (4) exists Storage address and list byte-sized clist_size information in DDR (5), and thus list byte-sized information determines to read Burst length during DDR (5)；

Read buffering FIFO (2), read list state it is effective when, if pempty indication signals are effective, send read DDR ask to AXI logic interfacings (3)；When reading buffering FIFO (2) non-empty, pre-decode reads interface (1) and caching is read from reading buffering FIFO (2) Table data；

AXI logic interfacings (3) carry out read access operation to DDR by standard AXI interfaces, generate table data and and table data Corresponding word enables, and word is enabled and is written to reading buffering FIFO (2) together with table data.

2. a kind of OpenGL as described in claim 1 shows list call circuit, which is characterized in that

It is 32b to read FIFO depth in buffering FIFO (2), and data width 264b, pempty are set as 16；The high 8b of data is as low The word of 256b enables.

3. a kind of OpenGL as described in claim 1 shows list call circuit, which is characterized in that

The read access operation information of AXI logic interfacings (3) includes the reading address valid signal of 1b, 4b read channels ID, 30b read ground Location, the reading burst length list_arlen of 4b；The ready letter of 1b read channels is included to the reading response of the read access operation information Number, the rlast signals of the data valid signal of the table data of 4b read channels ID, 256b, 1b and 1b.

4. a kind of OpenGL as claimed in claim 3 shows list call circuit, which is characterized in that

It is as follows to read the method that address generates：First address of reading is generated by " base address "+" address offset that pre-decode is sent ", thereafter Address be updated according to the size length read every time.

5. a kind of OpenGL as claimed in claim 3 shows list call circuit, which is characterized in that

The producing method for reading burst length is as follows：When being 0 for low 7 that read address, show that it is 512 byte-aligneds to read address, this When list_arlen by list length clist_size generate；If low 7 that read address are not 0, need first to read one section long The data for size_burst are spent, low 7 that read address are gathered as 0；Compare the size of size_burst and clist_size, If the length for reading list is more than size_burst, list_arlen is generated by size_burst at this time；Otherwise clist_ is still used Size is generated.