CN111625281A - Data processing method, device, equipment and storage medium - Google Patents
Data processing method, device, equipment and storage medium Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F13/14—Handling requests for interconnection or transfer
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Abstract
The invention discloses a data processing method, a data processing device, data processing equipment and a storage medium. The method comprises the following steps: the first device acquires target data; the first device writes the target data to a target area of a memory; after the write operation is finished, the first device sends a write operation finishing instruction to the register or the interrupt so as to enable the register or the interrupt to send write operation finishing information to the second device, and the second device reads the target data in the target area according to the write operation finishing information.
Description
Technical Field
Embodiments of the present invention relate to computer technologies, and in particular, to a data processing method, an apparatus, a device, and a storage medium.
Background
In Data interaction between a conventional FPGA (Field-Programmable Gate Array) and an MPU (Micro Processor Unit), whenever the FPGA and the MPU interact with each other, the MPU needs to participate in copying Data from a register or a controller to a DDR (DDR SDRAM, a Memory) for processing Data by other software, or copying Data from the DDR to the register for taking away the FPGA. The traditional scheme needs the MPU to participate in each data transmission, when the data interaction is very frequent, the efficiency of the MPU frequently entering the copying operation is too low, or when the data volume is large, the occupation rate of the MPU is too high, or the data cannot be processed at all.
Disclosure of Invention
Embodiments of the present invention provide a data processing method, an apparatus, a device, and a storage medium, so as to implement that a first device and a second device share a DDR area, where data processed by the first device is placed in a specific DDR area, and the second device can be directly taken away without copying data by the second device, and only the second device needs to simply control a read-write state, thereby reducing an occupancy rate of the second device and improving operation efficiency.
In a first aspect, an embodiment of the present invention provides a data processing method, including:
the first device acquires target data;
the first device writes the target data to a target area of a memory;
and after the write operation is finished, the first device sends a write operation finishing instruction to a register or an interrupt so as to enable the register or the interrupt to send write operation finishing information to a second device, and the second device reads the target data in the target area according to the write operation finishing information.
In a second aspect, an embodiment of the present invention further provides a data processing apparatus, where the apparatus includes: a first device, the first device comprising:
the acquisition module is used for acquiring target data;
a write module for writing the target data into a target area of a memory;
and the sending module is used for sending a write operation ending instruction to a register or an interrupt after the write operation is ended so that the register or the interrupt sends write operation ending information to a second device, and the second device reads the target data in the target area according to the write operation ending information.
In a third aspect, embodiments of the present invention further provide an apparatus, which when run on a computer, causes the computer to execute the data processing method according to any one of the embodiments of the present invention.
In a fourth aspect, the embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the data processing method according to any one of the embodiments of the present invention.
The embodiment of the invention obtains target data through a first device; the first device writes the target data to a target area of a memory; after the write operation is finished, the first device sends a write operation finishing instruction to the register or the interrupt so as to enable the register or the interrupt to send write operation finishing information to the second device, the second device reads the target data in the target area according to the write operation finishing information, the first device and the second device can share one DDR area, the data processed by the first device is placed in a specific area of the DDR, the second device can be directly taken away, the second device is not required to copy the data, the read-write state is simply controlled by the second device, the occupancy rate of the second device is reduced, and the operation efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a flow chart of a data processing method according to a first embodiment of the present invention;
FIG. 2A is a flowchart of a data processing method according to a second embodiment of the present invention;
FIG. 2B is a flow chart of another data processing method according to the second embodiment of the present invention;
FIG. 2C is a block diagram of the hardware connection according to the second embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a data processing apparatus according to a second embodiment of the present invention;
fig. 4 is a schematic structural diagram of an apparatus in the fourth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
Example one
Fig. 1 is a flowchart of a data processing method according to an embodiment of the present invention, where the present embodiment is applicable to a data processing situation, and the method may be executed by a data processing apparatus according to an embodiment of the present invention, where the apparatus may be implemented in a software and/or hardware manner, as shown in fig. 1, the method specifically includes the following steps:
s110, the first device acquires target data.
The target data may be data acquired by the programmable gate array FPGA, data obtained after processing by the programmable gate array FPGA, data acquired by the microprocessor, or data obtained after processing by the microprocessor, which is not limited in this embodiment of the present invention.
The first device may be a programmable gate array FPGA or a microprocessor, which is not limited in this embodiment of the present invention.
Optionally, the target data includes: collected data and/or processed data.
S120, the first device writes the target data into a target area of a memory.
The target area is a DDR area which can be commonly used by a MPU (micro processing Unit) and an FPGA (field programmable Gate array), and the target area is an area pre-divided by the MPU.
The size of the target area may be set artificially, and for example, the size of the target area may be 1 GB.
Optionally, the size of the target area is 1 GB.
Specifically, the first device may write the target data into a target area of the Memory by sending a write instruction to a Synchronous Dynamic Random Access Memory (SDRAM) controller by a Field Programmable Gate Array (FPGA), where the SDRAM controller controls the FPGA to write the target data into the target area of the Memory through an FPGA2HPSSDRAM interface, or sending a write instruction to the SDRAM controller by a microprocessor, where the SDRAM controller controls the microprocessor to write the target data into the target area of the Memory through an interface.
Optionally, the writing, by the first device, the target data into the target area of the memory includes:
the first device sends a write instruction to a controller so that the controller controls the first device to write the target data into a target area of a memory through an interface.
Wherein the controller may be an SDRAM controller.
Optionally, before the first device writes the target data into the target area of the memory, the method further includes:
the microprocessor divides a target area in the memory, wherein the target area can be directly written in or read out by the first device or the second device.
Specifically, the microprocessor may divide the target area in the memory into a first area and a second area, and the first area is used as the target area, for example, the microprocessor may determine an area with a preset size as the first area, the area of the memory other than the first area is the second area, and the first area is used as the target area; the microprocessor may further divide the storage area into a first area, a second area, a third area, and the like as needed, which is not limited in this embodiment of the present invention.
Optionally, the microprocessor maps the target area to a virtual address directly used by the microprocessor in a memory mapping manner.
And S130, after the write operation is finished, the first device sends a write operation finishing instruction to a register or an interrupt so as to enable the register or the interrupt to send write operation finishing information to a second device, and the second device reads the target data in the target area according to the write operation finishing information.
Specifically, after the write operation is finished, a write operation end instruction is sent to the register or the interrupt, the register or the interrupt sends write operation end information to the second device, and the second device directly reads the target data according to the write operation end information.
According to the technical scheme of the embodiment, target data are obtained through a first device; the first device writes the target data to a target area of a memory; after the write operation is finished, the first device sends a write operation finishing instruction to the register or the interrupt so as to enable the register or the interrupt to send write operation finishing information to the second device, the second device reads the target data in the target area according to the write operation finishing information, the first device and the second device can share one DDR area, the data processed by the first device is placed in a specific area of the DDR, the second device can be directly taken away, the second device is not required to copy the data, the read-write state is simply controlled by the second device, the occupancy rate of the second device is reduced, and the operation efficiency is improved.
Example two
This embodiment is optimized based on the above embodiment, and in this embodiment, the first device includes: a microprocessor or Field Programmable Gate Array (FPGA), the second device comprising: a microprocessor or a field programmable gate array FPGA, the first device being different from the second device.
As shown in fig. 2A, the method of this embodiment may specifically include the following steps:
s210, the FPGA acquires target data.
S220, the FPGA writes the target data into a target area of a memory.
And S230, after the write operation is finished, the FPGA sends a write operation finishing instruction to a register or an interrupt so that the register or the interrupt sends write operation finishing information to a microprocessor, and the microprocessor reads the target data in the target area according to the write operation finishing information.
Optionally, the writing, by the field programmable gate array FPGA, the target data into the target area of the memory includes:
and the field programmable gate array FPGA sends a writing instruction to a controller so that the controller controls the field programmable gate array FPGA to write the target data into a target area of a memory through an interface.
Optionally, the target data includes: the data collected by the field programmable gate array FPGA and/or the data processed by the field programmable gate array FPGA.
Optionally, the size of the target area is 1 GB.
Optionally, the microprocessor maps the target area to a virtual address directly used by the microprocessor in a memory mapping manner.
In a specific example, the field programmable gate array FPGA obtains target data, and the target data includes: the data collected by the field programmable gate array FPGA and/or the data processed by the field programmable gate array FPGA. The method comprises the steps that a microprocessor divides a target area in a memory, wherein the target area can be used for the microprocessor or a Field Programmable Gate Array (FPGA) to directly write data in or read data out, the size of the target area is 1GB, and other sizes can be set; and after the write operation is finished, the FPGA sends a write operation finishing instruction to a register or an interrupt so as to enable the register or the interrupt to send write operation finishing information to the microprocessor, and the microprocessor reads the target data in the target area according to the write operation finishing information.
As shown in fig. 2B, the method of this embodiment may further include the following steps:
s310, the microprocessor acquires target data.
S320, the microprocessor writes the target data into a target area of a memory.
S330, after the write operation is finished, the microprocessor sends a write operation finishing instruction to a register or an interrupt so as to enable the register or the interrupt to send write operation finishing information to a field programmable gate array, and the field programmable gate array reads the target data in the target area according to the write operation finishing information.
Optionally, the writing, by the microprocessor, the target data into the target area of the memory includes:
and the microprocessor sends a writing instruction to a controller so that the controller controls the microprocessor to write the target data into a target area of a memory through an interface.
Optionally, the target data includes: data collected by the microprocessor and/or data processed by the microprocessor.
Optionally, the size of the target area is 1 GB.
Optionally, the microprocessor maps the target area to a virtual address directly used by the microprocessor in a memory mapping manner.
In one specific example, the microprocessor obtains target data, the target data including: the data collected by the microprocessor and/or the data processed by the microprocessor. The method comprises the following steps that a microprocessor divides a target area in a memory, wherein the target area can be used for the microprocessor or a field programmable gate array FPGA to directly write data or read data, the size of the target area is 1GB, and other sizes can be set; and after the write operation is finished, the microprocessor sends a write operation finishing instruction to the register or the interrupt so as to enable the register or the interrupt to send write operation finishing information to the field programmable gate array FPGA, and the field programmable gate array FPGA reads the target data in the target area according to the write operation finishing information.
In another specific example, the scheme adopts an FPGA + ARM single SOC chip of intel aria10 for development and verification, a linux operating system runs on ARM, a hardware connection main block diagram is shown in fig. 2C, data is collected by the FPGA and then processed by the ARM, the linux operating system on the ARM side sets the highest 1GB data as reserve data, it is ensured that the linux kernel disables the highest 1GB data area, and simultaneously the area with the highest 1GB is mapped into a virtual address which can be directly used by the application in a memory mapping mmap manner; data acquired by the FPGA or processed by the algorithm is directly written into the DDR through the SDRAM interface of the FPGA2HPS, and meanwhile, the MPU is informed of the completion of data preparation through a register or interruption and is readable; the ARM side linux operating system application program can directly use data written into the DDR by the FPGA, any copying operation is not needed, after the application program uses the data, the corresponding data is set to be dirty data through a register, and the FPGA is informed to be writable. The principle of ARM for transmitting data to FPGA is the same, the communication mode is adopted, the read-write data completely depends on the speeds of an SDRAM controller, a DDR and the FPGA, the actual speed and the theoretical speed can reach 100Gb/s, and the data communication method is far higher than other traditional data interaction modes.
According to the technical scheme, target data are obtained through a field programmable gate array FPGA, the field programmable gate array FPGA writes the target data into a target area of a memory, the field programmable gate array FPGA sends a write operation ending instruction to a register or an interrupt after write operation is finished so that the register or the interrupt sends write operation ending information to a microprocessor, the microprocessor reads the target data in the target area according to the write operation ending information or obtains the target data, the microprocessor writes the target data into the target area of the memory, the microprocessor sends the write operation ending instruction to the register or the interrupt after the write operation is finished so that the register or the interrupt sends the write operation ending information to the field programmable gate array FPGA, and the field programmable gate array FPGA reads the target data in the target area according to the write operation ending information Marking data, can realize that field programmable gate array FPGA and microprocessor use a DDR region jointly, the data that field programmable gate array FPGA handled the completion are put in the specific area of DDR, microprocessor can directly be taken away, do not need microprocessor copy data, only need the simple control read-write state of microprocessor, and then reduce microprocessor's occupancy, promote operating efficiency, the data that microprocessor handled the completion are put in the specific area of DDR, field programmable gate array FPGA can directly be taken away, do not need field programmable gate array FPGA copy data, only need the simple control read-write state of field programmable gate array FPGA, and then reduce field programmable gate array FPGA's occupancy, promote operating efficiency.
EXAMPLE III
Fig. 3 is a schematic structural diagram of a data processing apparatus according to a third embodiment of the present invention. The present embodiment may be applicable to the case of data processing, the apparatus may be implemented in a software and/or hardware manner, and the apparatus may be integrated in any device providing a data processing function, as shown in fig. 3, where the data processing apparatus specifically includes: a first device 4, the first device 4 comprising: an acquisition module 410, a write module 420, and a send module 430.
The obtaining module 410 is configured to obtain target data;
a write module 420 for writing the target data into a target area of a memory;
a sending module 430, configured to send a write operation end instruction to a register or an interrupt after the write operation is ended, so that the register or the interrupt sends write operation end information to a second device, and the second device reads the target data in the target area according to the write operation end information.
The product can execute the method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.
According to the technical scheme of the embodiment, target data are obtained through a first device; the first device writes the target data to a target area of a memory; after the write operation is finished, the first device sends a write operation finishing instruction to the register or the interrupt so as to enable the register or the interrupt to send write operation finishing information to the second device, the second device reads the target data in the target area according to the write operation finishing information, the first device and the second device can share one DDR area, the data processed by the first device is placed in a specific area of the DDR, the second device can be directly taken away, the second device is not required to copy the data, the read-write state is simply controlled by the second device, the occupancy rate of the second device is reduced, and the operation efficiency is improved.
Example four
Fig. 4 is a schematic structural diagram of a computer device in the fourth embodiment of the present invention. FIG. 4 illustrates a block diagram of an exemplary computer device 12 suitable for use in implementing embodiments of the present invention. The computer device 12 shown in FIG. 4 is only one example and should not bring any limitations to the functionality or scope of use of embodiments of the present invention.
As shown in FIG. 4, computer device 12 is in the form of a general purpose computing device. The components of computer device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 that couples various system components including the system memory 28 and the processing unit 16.
The system memory 28 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM)30 and/or cache memory 32. Computer device 12 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 34 may be used to read from and write to non-removable, nonvolatile magnetic media (not shown in FIG. 4, and commonly referred to as a "hard drive"). Although not shown in FIG. 4, a magnetic disk drive for reading from and writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 18 by one or more data media interfaces. Memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the invention.
A program/utility 40 having a set (at least one) of program modules 42 may be stored, for example, in memory 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which examples or some combination thereof may comprise an implementation of a network environment. Program modules 42 generally carry out the functions and/or methodologies of the described embodiments of the invention.
The processing unit 16 executes various functional applications and data processing by executing programs stored in the system memory 28, for example, implementing a data processing method provided by an embodiment of the present invention: the first device acquires target data; the first device writes the target data to a target area of a memory; and after the write operation is finished, the first device sends a write operation finishing instruction to a register or an interrupt so as to enable the register or the interrupt to send write operation finishing information to a second device, and the second device reads the target data in the target area according to the write operation finishing information.
EXAMPLE five
Fifth embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the data processing method provided in all the embodiments of the present invention: the first device acquires target data; the first device writes the target data to a target area of a memory; and after the write operation is finished, the first device sends a write operation finishing instruction to a register or an interrupt so as to enable the register or the interrupt to send write operation finishing information to a second device, and the second device reads the target data in the target area according to the write operation finishing information.
Any combination of one or more computer-readable media may be employed. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A data processing method, comprising:
the first device acquires target data;
the first device writes the target data to a target area of a memory;
and after the write operation is finished, the first device sends a write operation finishing instruction to a register or an interrupt so as to enable the register or the interrupt to send write operation finishing information to a second device, and the second device reads the target data in the target area according to the write operation finishing information.
2. The method of claim 1, wherein the first device writing the target data to a target area of memory comprises:
the first device sends a write instruction to a controller so that the controller controls the first device to write the target data into a target area of a memory through an interface.
3. The method of claim 1, wherein the target data comprises: collected data and/or processed data.
4. The method of claim 1, wherein the first device comprises: a microprocessor or Field Programmable Gate Array (FPGA), the second device comprising: a microprocessor or a field programmable gate array FPGA, the first device being different from the second device.
5. The method of claim 1, wherein prior to the first device writing the target data to the target region of memory, further comprising:
the microprocessor divides a target area in the memory, wherein the target area can be directly written in or read out by the first device or the second device.
6. The method of claim 5, wherein the target area size is 1 GB.
7. The method of claim 5, wherein the microprocessor maps the target area to a virtual address directly used by the microprocessor via a memory mapping.
8. A data processing apparatus, comprising: a first device, the first device comprising:
the acquisition module is used for acquiring target data;
a write module for writing the target data into a target area of a memory;
and the sending module is used for sending a write operation ending instruction to a register or an interrupt after the write operation is ended so that the register or the interrupt sends write operation ending information to a second device, and the second device reads the target data in the target area according to the write operation ending information.
9. An apparatus which, when run on a computer, causes the computer to perform the method of any one of claims 1-7.
10. A computer-readable storage medium comprising instructions which, when run on a computer, cause the computer to perform the method of any one of claims 1-7.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022110172A1 (en) * | 2020-11-30 | 2022-06-02 | 华为技术有限公司 | Data processing method and related device |
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