CN107958438A

CN107958438A - A kind of OpenGL creates display listing circuitry

Info

Publication number: CN107958438A
Application number: CN201711281040.8A
Authority: CN
Inventors: 郝冲; 牛少平; 邓艺; 魏艳艳; 韩鹏; 韩一鹏
Original assignee: Xian Aeronautics Computing Technique Research Institute of AVIC
Current assignee: Xian Aeronautics Computing Technique Research Institute of AVIC
Priority date: 2017-12-06
Filing date: 2017-12-06
Publication date: 2018-04-24

Abstract

The invention belongs to area of computer graphics, is related to a kind of OpenGL and creates display listing circuitry, including：Pre-decode writes interface 1, and the newly-built list enable signal sent to pre-decode unit 5 is detected, and when detecting that newly-built list enable signal is effective, sets newly-built list state effective；Newly-built table data and word of the list in DDR6 is obtained from pre-decode unit 5 enable information and be sent to write data splicing 2；Data splicing 2 is write, the table data received and word are enabled into information is assembled into the FIFO of 264b and write data, when 264b data assemblings finish or pre-decode unit 5 is decoded to and terminates the order of list, then the data of assembling are written to Write post FIFO3；Write post FIFO3, when newly-built list state is effective, if pfull indication signals are effective or pre-decode unit 5 is decoded to the order for terminating list, AXI logic interfacings 4 are sent to by the buffered data in Write post FIFO3；AXI logic interfacings 4, the buffered data from Write post FIFO3 is written in DDR6 according to AXI standard interfaces.

Description

A kind of OpenGL creates display listing circuitry

Technical field

The invention belongs to area of computer graphics, is related to a kind of newly-built display list commands data to OpenGL and stores electricity The realization on road.

Background technology

In area of computer graphics, display list is to solve the problems, such as that unnecessary repetition renders, and is buffered from order One piece of precalculated data is taken out in area, they are responsible for performing some repeated tasks, such as draw anchor ring, this block Data can copy back into command buffer at any time later, this block number is created according to required a large amount of function calls and compiling so as to save Expense.In newly-built display list, perform, can only carry out one by one because pre-decode unit processing graph command is order, In order to avoid carrying out frequent read access to DDR buses, this newly-built display is added between pre-decode and DDR access arbitrations Listing circuitry.

The content of the invention

The purpose of the present invention is：

The present invention provides a kind of OpenGL and creates display listing circuitry, for list commands data to be written in DDR Circuit, so as to fulfill this operating process of newly-built list.

The present invention technical solution be：

A kind of OpenGL creates display listing circuitry, including：Pre-decode writes interface 1, writes data splicing 2, Write post FIFO3, AXI logic interfacing 4；

Pre-decode writes interface 1, and the newly-built list enable signal sent for pre-decode unit 5 is detected, when detecting When newly-built list enable signal is effective, setting OpenGL to create, to create list state in display listing circuitry effective；From pre-decode Unit 5 obtains newly-built table data and word of the list in DDR6 and enables information, and table data and word are enabled information hair Give and write data splicing 2；

Data splicing 2 is write, the table data received and word are enabled into information is assembled into the FIFO of 264b and write data, when 264b data assemblings finish or pre-decode unit 5 is decoded to the order for terminating list, then are written to the data of assembling slow Rush FIFO3；

Write post FIFO3, when newly-built list state is effective, if pfull indication signals are effective or pre-decode unit 5 is translated Buffered data in Write post FIFO3 is then sent to AXI logic interfacings 4 by code to the order for terminating list；

AXI logic interfacings 4, the buffered data from Write post FIFO3 is written in DDR6 according to AXI standard interfaces.

The FIFO depth of Write post FIFO3 is 32b, and data width 264b's, pfull is dimensioned to 16；Data High 8b is enabled as the word of low 256b.

AXI logic interfacings 4 include the process in the data write-in DDR6 of assembling：

First AXI logic interfacings to DDR6 send the write address useful signal of 1b, 4b write access ID, 30b write address Information, 4b write burst length, after waiting the 1b write access ready signal response for receiving DDR6 replies, you can initiate one The data transfer of burst length, by 1b write useful signal, 8b write data word enable, the table data of 256b and 1b Write end signal and be sent to DDR6, DDR6 replys the ready signal of writing of 1b after receiving, completion is once transmitted.

The method that write address information produces is as follows：It is first read address by " base address "+" pre-decode unit send address it is inclined Move " produce, address thereafter is updated according to the burst length of last write-in DDR6.

The producing method for writing burst length is as follows：If the DDR that writes that pfull is initiated is asked, then burst length is 4' b1111；If being sent to the end of display list, burst length is remaining data amount check in Write post FIFO3.

The 128b data received and corresponding 4b words are enabled be assembled into 264b FIFO write data method it is as follows： When received nlist_wr_wden is effective, it is successively placed in the null field of wr_data_tmp, and is set at the same time corresponding Wr_data_wden be 1；, will when 8 the enabled of word are all 1, or the current command is the last item order in list Word, which is enabled, together writes Write post FIFO3 with data.

It is an advantage of the invention that：The present invention provides a kind of circuit realization that data and buffering are write for DDR, it is used for realization Pre-decode unit rapidly and efficiently will display table data be written in DDR.

Brief description of the drawings

Fig. 1 is the method module map of the present invention.

Fig. 2 is the schematic diagram that the present invention writes data splicing.

Embodiment

In order to make the purpose , technical scheme and advantage of the present invention be clearer, below in conjunction with example, the present invention is made It is further described.It should be appreciated that instantiation described herein is not used to limit this only to explain the present invention Invention.

Embodiment

As shown in Figure 1, a kind of circuit being used in newly-built display list commands write-in DDR6 is realized, possess pre-decode and write and connect Mouth 1, write the part such as data splicing 2, Write post FIFO3, AXI logic interfacing 4 composition.

A) pre-decode writes interface 1：When detecting that the newly-built list of pre-decode unit is enabled, list state instruction letter is write in setting Number effectively, and when it is 0 that data, which effectively indicate data_valid, table data renewal will be write to nlist_data；

B) data splicing 2 is write：Because the data bit width handled in pre-decode is 128b, and AXI buses DDR writes interface data Bit wide is 256b, so bit wide matching to be needed to the process of one data splicing of increase, can not only be spliced 128b data Into 256b, while invalid field can also be removed.Data splicing carries out successively according to compact arranged principle, after the completion of splicing It is written to Write post FIFO；

C) Write post FIFO3：Write list state indication signal it is effective when, if pfull is effective, to DDR6 initiate write behaviour Make, or write that list state is invalid and Write post FIFO3 non-NULLs, also need to initiate write operation to write data in Write post FIFO3 Into DDR6；

D) AXI logic interfacings 4：After the write request of initiation obtains DDR6 responses, you can initiate the data of a burst length Data in Write post FIFO3 are deposited into DDR6 by transmission in the form of the strb of the data of 256b and 8b.

The method that write address produces is as follows：First address of reading is by " base address "+" address offset that pre-decode unit is sent " Produce, address thereafter is updated according to the size length write every time；

The producing method for writing burst length is as follows：To avoid the problem that across DDR address boundary, write address is done The regulation of 512 byte-aligneds, so writing burst length need to only determine according to the number of data.If pfull is initiated Write DDR request, then burst length is 4'b1111；If being sent to the end of display list, burst length is by buffering Remaining data amount check determines in FIFO.

The method for writing data splicing is as follows：The process of order splicing is illustrated in fig. 2 shown below, as received nlist_wr_wden When effective, it is successively placed in the null field of wr_data_tmp, and it is 1 to set corresponding wr_data_wden at the same time；When 8 The enabled of a word is all 1, or when the current command is the last item order in list, word is enabled and is together write with data FIFO_WR。

Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although The present invention is explained with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that：It still may be used To modify to the technical solution described in foregoing embodiments, or equivalent substitution is carried out to which part technical characteristic； And these modification or replace, do not make appropriate technical solution essence depart from various embodiments of the present invention technical solution spirit and Scope.

Claims

1. a kind of OpenGL creates display listing circuitry, it is characterised in that including：Pre-decode writes interface (1), writes data splicing (2), Write post FIFO (3), AXI logic interfacings (4)；

Pre-decode writes interface (1), and the newly-built list enable signal sent for pre-decode unit (5) is detected, when detecting When newly-built list enable signal is effective, setting OpenGL to create, to create list state in display listing circuitry effective；From pre-decode Unit (5) obtains newly-built table data and word of the list in DDR (6) and enables information, and table data and word are enabled letter Breath, which is sent to, writes data splicing (2)；

Data splicing (2) is write, the table data received and word are enabled into information is assembled into the FIFO of 264b and write data, when 264b data assemblings finish or pre-decode unit (5) is decoded to the order for terminating list, then are written to the data of assembling Buffer FIFO (3)；

Write post FIFO (3), when newly-built list state is effective, if pfull indication signals are effective or pre-decode unit (5) is translated Buffered data in Write post FIFO (3) is then sent to AXI logic interfacings (4) by code to the order for terminating list；

AXI logic interfacings (4), DDR (6) is written to by the buffered data from Write post FIFO (3) according to AXI standard interfaces In.

2. a kind of OpenGL as claimed in claim 1 creates display listing circuitry, it is characterised in that

The FIFO depth of Write post FIFO (3) is 32b, and data width 264b's, pfull is dimensioned to 16；The height of data 8b is enabled as the word of low 256b.

3. a kind of OpenGL as claimed in claim 1 creates display listing circuitry, it is characterised in that

AXI logic interfacings (4) include the process in the data write-in DDR (6) of assembling：

AXI logic interfacings are to DDR (6) sends the write address useful signal of 1b, the write address of write access ID, 30b of 4b is believed first Breath, 4b write burst length, after waiting the 1b write access ready signal response for receiving DDR (6) replies, you can initiate one The data transfer of burst length, by 1b write useful signal, 8b write data word enable, the table data of 256b and 1b Write end signal and be sent to DDR (6), DDR (6) replys the ready signal of writing of 1b after receiving, completion is once transmitted.

4. a kind of OpenGL as claimed in claim 3 creates display listing circuitry, it is characterised in that

The method that write address information produces is as follows：First address of reading is by " base address "+" address offset that pre-decode unit is sent " Produce, address thereafter is updated according to the burst length of last write-in DDR (6).

5. a kind of OpenGL as claimed in claim 3 creates display listing circuitry, it is characterised in that

The producing method for writing burst length is as follows：If the DDR that writes that pfull is initiated is asked, then burst length is 4' b1111；If being sent to the end of display list, burst length is remaining data amount check in Write post FIFO (3).

6. a kind of OpenGL as claimed in claim 1 creates display listing circuitry, it is characterised in that

The 128b data received and corresponding 4b words are enabled be assembled into 264b FIFO write data method it is as follows：Work as receipts When the nlist_wr_wden arrived is effective, it is successively placed in the null field of wr_data_tmp, and corresponding wr_ is set at the same time Data_wden is 1；When 8 the enabled of word are all 1, or the current command is the last item order in list, word is enabled Write post FIFO (3) is together write with data.