CN113485875A - Chip verification system and verification method - Google Patents
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Abstract
The application provides a chip verification system and a chip verification method, which comprise at least one TM chip and at least one SW chip, wherein at least one serial communication link is arranged between each TM chip and each SW chip, each TM chip and each SW chip are obtained by respectively adopting SystemC modeling, and each TM chip and each SW chip are respectively provided with a communication service process corresponding to the serial communication link. Each TM chip sends first data to the SW chip through the corresponding serial communication link by using the communication service process in the TM chip, so that the SW chip reads the first data from the corresponding serial communication link by using the communication service process in the SW chip; each SW chip sends the second data to the TM chip through the corresponding serial communication link by using the communication service process therein, so that the TM chip reads the second data from the corresponding serial communication link by using the communication service process therein.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a chip verification system and a chip verification method.
Background
The frame Switch generally includes a plurality of Traffic Management (TM) chips and a plurality of Switch (SW) chips, where the TM chip is responsible for forwarding messages, queue Management, Traffic Management, and other services, and the SW chip is responsible for forwarding cells, and the TM chip and the SW chip belong to the same solution, and cooperate to complete processing of large-scale data messages. The TM chip and the SW chip belong to large-scale integrated circuit design, and in order to complete the design of a very large-scale integrated circuit, a simulation verification model of the chip needs to be established at a pre-research stage of the chip, that is, the TM chip and the SW chip need to be verified, that is, the architecture, algorithm and function of the chip are verified at a higher abstraction level, and meanwhile, complicated gate-level and RTL-level hardware descriptions are not involved, so that the normal use of the subsequent TM chip and the SW chip is ensured.
At present, when a chip is verified, the verification is generally performed through an established SystemC verification model, and SystemC is a system modeling language which is supported and maintained by Open SystemC Initiative (OSIC) and is a set of libraries developed on the basis of C + +. By establishing a verification model through SystemC, the functions of message forwarding, queue management, QoS, routing strategy and the like of the switching chip solution and related algorithms can be verified and evaluated as references for subsequent hardware development. However, the conventional modeling scheme based on SystemC generally describes a single chip architecture. The method comprises the steps of describing sequential logic or combinational logic of subsystems in a chip by using modules (modules) provided by SystemC and corresponding methods (methods) and threads (threads), describing input and output signals of the subsystems by ports (ports), connecting ports among the subsystems by signals (signals), and defining clock signals as trigger signals of each module, thereby establishing a model of the whole chip. However, the method only meets the verification requirement of a single chip, and cannot meet the requirement of simultaneous verification of the TM chip and the SW chip under the solution of the frame switch. And it is not applicable to a scene in which various structures are changed when a plurality of TM chips and a plurality of SW chips are included in the block switch.
Therefore, how to simultaneously verify the TM chip and the SW chip is one of the considerable technical problems.
Disclosure of Invention
In view of this, the present application provides a chip verification system and a verification method for simultaneously verifying a TM chip and a SW chip.
Specifically, the method is realized through the following technical scheme:
according to a first aspect of the present application, a chip verification system is provided, including at least one traffic management TM chip and at least one switching SW chip, at least one serial communication link is provided between each TM chip and each SW chip, each TM chip and each SW chip are obtained by respectively adopting a system modeling language SystemC modeling, each TM chip is provided with a communication service process corresponding to the serial communication link, each SW chip is provided with a communication service process corresponding to the serial communication link, wherein:
each TM chip sends first data to the SW chip through the corresponding serial communication link by using the communication service process in the TM chip, so that the SW chip reads the first data from the corresponding serial communication link by using the communication service process in the SW chip;
each SW chip utilizes the communication service process in the SW chip to send the second data to the TM chip through the corresponding serial communication link, so that the TM chip utilizes the communication service process in the TM chip to read the second data from the corresponding serial communication link.
According to a second aspect of the present application, a chip verification method is provided, which is applied to a traffic management TM chip in a chip verification system, the chip verification system further includes an exchange SW chip, at least one serial communication link is provided between the TM chip and the SW chip, the TM chip and the SW chip are obtained by respectively adopting a system modeling language SystemC modeling, the TM chip is provided with a communication service process corresponding to the serial communication link, and the SW chip is provided with a communication service process corresponding to the serial communication link; the method comprises the following steps:
the TM chip sends first data to the SW chip through a corresponding serial communication link by using a communication service process in the TM chip, so that the SW chip reads the first data from the corresponding serial communication link by using the communication service process in the SW chip and executes corresponding verification operation;
and the TM chip reads the second data sent by the SW chip from the corresponding serial communication link by utilizing a communication service process in the TM chip and executes corresponding verification operation.
According to a third aspect of the present application, a chip verification method is provided, which is applied to an exchange SW chip in a chip verification system, where the chip verification system further includes a traffic management TM chip, at least one serial communication link is provided between the SW chip and the TM chip, the SW chip and the TM chip are obtained by respectively modeling using a system modeling language SystemC, the SW chip is provided with a communication service process corresponding to the serial communication link, and the TM chip is provided with a communication service process corresponding to the serial communication link; the method comprises the following steps:
the SW chip reads first data sent by the TM chip from a corresponding serial communication link by using a communication service process in the SW chip and executes corresponding verification operation by using the first data;
and the SW chip utilizes the communication service process in the SW chip to send the second data to the TM chip through the corresponding serial communication link, so that the TM chip utilizes the communication service process in the TM chip to read the second data from the corresponding serial communication link and execute corresponding verification operation.
The beneficial effects of the embodiment of the application are as follows:
through the chip verification system provided by the embodiment, the TM chip and the SW chip can perform data transmission through a serial communication link between the two chips, that is, the TM chip and the SW chip can perform data interaction through respective communication service processes, so that verification of data transmission functions of the TM chip and the SW chip can be completed, and verification of functions (functions except for verification related to a data interaction function) of the TM chip and the SW chip is combined at the same time, so that simultaneous verification of each TM chip and each SW chip can be realized, and the problems of poor verification efficiency and poor networking flexibility caused by the fact that only single-chip verification can be realized in the prior art are solved.
Drawings
Fig. 1 is a schematic structural diagram of a chip verification system according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of another chip verification system provided in an embodiment of the present application;
fig. 3 is a schematic diagram of a link between a TM chip 1 and a TM chip 2 provided in an embodiment of the present application;
fig. 4 is a schematic flowchart of a chip verification method according to an embodiment of the present application;
fig. 5 is a schematic flowchart of another chip verification method according to an embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with aspects such as the present application.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the corresponding listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
The chip verification system provided by the present application is described in detail below.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a chip verification system provided by the present application, where the chip verification system includes at least one TM chip and at least one SW chip, at least one serial communication link is provided between each TM chip and each SW chip, each TM chip and each SW chip are obtained by respectively modeling using a system modeling language SystemC, each TM chip is provided with a communication service process corresponding to the serial communication link, and each SW chip is provided with a communication service process corresponding to the serial communication link, where:
each TM chip sends first data to the SW chip through the corresponding serial communication link by using the communication service process in the TM chip, so that the SW chip reads the first data from the corresponding serial communication link by using the communication service process in the SW chip;
each SW chip utilizes the communication service process in the SW chip to send the second data to the TM chip through the corresponding serial communication link, so that the TM chip utilizes the communication service process in the TM chip to read the second data from the corresponding serial communication link.
Specifically, each TM chip and each SW chip are independent SystemC models, and can run on hosts with different IP addresses, so as to realize verification of each TM chip and each SW chip. It should be noted that the switches with different structures are different in the configuration of the switch, but the verification of the TM chip and the SW chip in the switches with different structures may adopt the chip verification system provided by the present application. When the chip verification system provided by the embodiment is used for verification, the functions of the TM chip and the SW chip can be verified through interaction between the modules of the TM chip and the SW chip. For example, when the TM chip is verified, the functions to be verified may be, but are not limited to, verification of a scheduling algorithm, verification of a traffic shaping function, verification of a distributed flow proportion function, verification of a queue scheduling function, and the like; when the SW chip performs verification, functions required to be verified may include, but are not limited to, verification of a message forwarding function, and the message forwarding function may involve table lookup, forwarding, and the like. And the verification of the interaction function between the TM chip and the SW chip can be realized by performing data interaction through a serial communication link between the two chips through a communication service process in the two chips so as to complete the verification of the related function.
The first data may be test data, such as a test message, etc., and the second data may be, but is not limited to, response data of the first data, such as a response message, etc. It should be noted that, in the verification process of the TM chip and the SW chip, data related to interaction between the two chips can be interacted through a serial communication link between the TM chip and the SW chip, but a specific verification process of the chip refers to a currently provided verification method, and details are not described here. For ease of understanding, a simple example is given here to describe the testing process of the relevant functions of the TM chip and the SW chip. For example, when the TM chip needs to test the traffic scheduling capability, the TM chip may transmit first data to be scheduled in the TM chip to a serial communication link corresponding to the communication service process through a communication service process therein, then the communication service process corresponding to the serial communication link in the SM chip may read the first data from the serial communication link, and then the SW chip may find a destination address of the first data by checking a routing table, a forwarding table, and the like, and forward the first data to a network device corresponding to the destination address.
It should be noted that the number of TM chips and SW chips included in the chip verification system provided in this embodiment may be determined according to an actual networking environment, and may be changed according to the number of chips in the actual networking environment, so as to adapt to flexible changes of networking.
Through the chip verification system provided by the embodiment, the TM chip and the SW chip can perform data transmission through a serial communication link between the two chips, that is, the TM chip and the SW chip can perform data interaction through respective communication service processes, so that verification of data transmission functions of the TM chip and the SW chip can be completed, and verification of functions (functions except for verification related to a data interaction function) of the TM chip and the SW chip is combined at the same time, so that simultaneous verification of each TM chip and each SW chip can be realized, and the problems of poor verification efficiency and poor networking flexibility caused by the fact that only single-chip verification can be realized in the prior art are solved.
Optionally, the communication service process corresponding to each serial communication link includes a client process and a server process; each TM chip utilizes the client process therein to send first data to the SW chip through the corresponding serial communication link, so that the SW chip utilizes the server process therein to read the first data from the corresponding serial communication link; and each SW chip utilizes the client process in the SW chip to send the second data to the TM chip through the corresponding serial communication link, so that the TM chip utilizes the server process in the TM chip to read the second data from the corresponding serial communication link.
Specifically, the serial communication link provided by the application is a bidirectional serial communication link, on this basis, each TM chip is provided with a communication service process corresponding to the serial communication link, including a client process and a server process, and similarly, each SW chip is provided with a communication service process corresponding to the serial communication link, including a client process and a server process. On this basis, one bidirectional serial communication link in the embodiment includes a unidirectional communication link in which the TM chip points to the SW chip direction and a unidirectional communication link in which the SW chip points to the TM chip direction. In order to implement a serial communication link between a TM chip and a SW chip, a client process and a server process need to be set on the TM chip side, and similarly, a client process and a server process need to be set on the SW chip side, that is, one serial communication link corresponds to one client process and one server process on the TM chip side, and one client process and one server process on the SW chip side. Then, a client process at the TM chip side and a server process at the SW chip side simulate to form a one-way communication link of the TM chip pointing to the SW chip direction, a client process at the SW chip side and a server process at the TM chip side simulate to form a one-way communication link of the SW chip pointing to the TM chip direction, so that a serial communication link between the TM chip and the SW chip can be formed, and one client process and one server process form a pair of client process and server process, which can be called a pair of communication service processes, so that one serial communication link needs 2 pairs of client process and server process, namely 2 pairs of communication service processes; when a plurality of serial communication links are included between the TM chip and the SW chip, a plurality of pairs of communication service processes are arranged in both the TM chip and the SW chip.
Further, the client process in each pair of communication service processes is used for performing data sending operation, and the server process is used for performing data reading operation. That is, when the TM chip sends the first data, it may call a client process in the TM chip to send the first data to the client for a corresponding serial communication link, so that a server process in the SW chip corresponding to the serial communication link may read the first data from the serial communication link and perform a related verification operation. Similarly, when the SW chip sends the second data to the TM chip, the SW chip may call a client process therein to send the second data to the corresponding serial communication link, and then a server process in the TM chip may call a server process thereon to read the second data from the serial communication link, and then perform the related verification operation.
Alternatively, the serial communication link provided by this embodiment may be a SerDes link (bidirectional SerDes link), each SerDes link is simulated by a communication service process respectively located in the TM chip and the SW chip, for example, a client process located in the TM chip and a server process located in the SW chip simulate a unidirectional SerDes link in which the TM chip points to the SW chip, and similarly, a client process located in the SW chip and a server process located in the TM chip simulate a unidirectional SerDes link in which the SW chip points to the TM chip, and these two unidirectional SerDes links constitute the above-mentioned bidirectional SerDes link. Correspondingly, the communication service process in any of the embodiments of the present application may be, but is not limited to, a Socket process, and on this basis, a Socket process corresponding to one SerDes link includes 2 Socket client processes and 2 Socket server processes, that is, 2 pairs of Socket processes, where 1 Socket client process and 1 Socket server process are arranged in a TM chip, and 1 Socket client process and 1 Socket server process are arranged in an SW chip.
To better understand the chip verification system provided in the present embodiment, a chip verification system including 2 TM chips and 2 SW chips shown in fig. 2 is taken as an example for description. Each chip (TM chip, SW chip) in fig. 2 is an independent SystemC model, and then a bidirectional SerDes link between the TM chip and the SW chip is simulated using 2 pairs of Socket processes to support a full-duplex operating mode. The SystemC model of each chip (TM chip, SW chip) maintains a plurality of Socket processes, and for each TM chip and SW chip, each Socket process within the chip only processes one operation of sending data or reading data, for example, TM chip (TM chip 1 and TM chip 2) in fig. 2 includes a plurality of Socket processes, SW chip (SW chip 1 and SW chip 2) includes a plurality of Socket processes, and Socket Ai in TM chip (TM chip 1 and TM chip 2) is a Socket client process, Socket Bi is a server process, Socket Ci in SW chip (SW chip 1 and SW chip 2) is a Socket client process, Socket Di is a server process, i.e. Socket a1 in TM chip 1 and Socket D1 in SW chip 1 in fig. 2 constitute a unidirectional serial des link pointing to SW chip, and Socket 1 in SW chip 1 and Socket B35 in TM chip in SW chip constitute a unidirectional serial des link pointing to SW chip, and so on. On the basis, the TM chip only uses Socket Ai to carry out sending operation, and only uses Socket Bi to carry out reading operation; accordingly, in the SW chip, only Socket Ci is used for sending operation, and only Socket Di is used for reading operation.
On this basis, when the TM chip 1 interacts with the SW chip 1, the TM chip 1 may send the first data to a SerDes link corresponding to the Socket a1 by using the Socket a1 therein, and the SerDes link is connected by the Socket D1 on the SW chip 1 side, so that the SW chip 1 may read the first data sent by the TM chip 1 from the SerDes link by using the Socket D1. Similarly, when the SW chip 1 needs to send the second data to the TM chip 1, the SW chip 1 may send the second data to the SerDes link corresponding to the Socket C1 by using the Socket C1 therein, and the SerDes link corresponding to the Socket C1 is connected by the Socket B1 on one side of the TM chip 1, so that the TM chip 1 may read the second data from the SerDes link by using the Socket B1, thereby implementing the verification of the related exchange function between the TM chip 1 and the SW chip 1.
Based on any of the above embodiments, each TM chip and each SW chip respectively include an interface module for maintaining the communication service process.
Specifically, as also illustrated in fig. 2, the interface module of the SystemC model of each chip (TM chip or SW chip) is responsible for maintaining a Socket process and processing Socket events, including sending data, receiving data, and Socket listening. For example, a Socket process responsible for sending data is implemented by a Socket client process, and a Socket process responsible for reading data is implemented by a Socket server process. For convenience of understanding, please refer to fig. 3, in an interface module of a SystemC model of a chip (TM chip or SW chip), a SerDes link is simulated by respectively maintaining a Socket server process and a Socket client process, in fig. 3, 2 full-duplex SerDes links are simulated by the Socket server process and the Socket client between TM chip 1 and SW chip 1, which are SerDes link 1 and SerDes link 2, specifically: the SerDes link 1 is formed by a unidirectional SerDes link which is formed by a TM chip 1 and a Socket Client process 1 (noted as Client1) in the TM chip 1 and a Socket Server process 1 (noted as Server1) in the SW chip 1, wherein the TM chip 1 points to the SW chip 1, and a unidirectional SerDes link which is formed by a Socket Client process 2 (noted as Client2) in the SW chip 1 and a Socket Server process 2 (noted as Server2) in the TM chip 1 points to the TM chip 1; and the SerDes link 2 is composed of a unidirectional SerDes link in which a TM chip 1 composed of a Socket Client process 3 (denoted as Client3) in the TM chip 1 and a Socket Server process 3 (denoted as Server3) in the SW chip 1 points to the SW chip 1, and a unidirectional SerDes link in which a Socket Client process 4 (denoted as Client4) in the SW chip 1 and a Socket Server process 4 (denoted as Server4) in the TM chip 1 points to the TM chip 1. Data interaction between the TM chip 1 and the SW chip 1 can be performed based on the SerDes link shown in fig. 3, and thus chip verification of the TM chip 1 and the SW chip 1 is simultaneously achieved.
In an actual environment, for modeling of multiple chips, it is generally assumed that SerDes links between chips do not lose packets, for a SystemC model of one chip, on a Socket client process side, a packet to be sent is sent to a corresponding server process in each clock cycle by the Socket client process, and on a Socket server side, the Socket server process receives data external to the SystemC model (chip), so that, in each clock cycle, the number of Socket events to be processed is not constant (including receiving data and reopening a monitoring port after Socket connection is closed), but time consumption for processing different Socket events should be different in time consumption simulation (for example, time consumption for receiving data should be less than time consumption for reopening the monitoring port after Socket connection is closed), and therefore, an operation of reading data should be decoupled from the monitoring event. Specifically, the present application proposes to perform the above decoupling operation by the global Quantum time Quantum Keeper of SystemC TLM.
On this basis, the interface module adjusts the counter based on the set global quantum time to control the operation times of the communication service process for reading data and the operation times of the communication service process for establishing communication connection in the period.
Specifically, for each chip (TM chip and SW chip), the global quantum time may be configured according to a simulation cycle, so as to advance the chip to a next simulation clock cycle, that is, the global quantum time is a time for advancing the simulation to the next simulation clock cycle. The global quantum time may specifically be configured with a set _ global _ quantum in the initialization phase. It should be noted that the simulation clock period should be the same as the clock period of the chip. And then setting a counter for the communication service process in the interface module, and controlling the operation times of reading data by the communication service process and establishing communication connection with the communication service process in each simulation clock cycle by adjusting the value of the counter, thereby controlling the time of the communication service process entering the next simulation clock cycle.
Optionally, if the communication service process maintained by the interface module in each chip (TM chip and SW chip) is a server process, the interface module may determine whether the server process is disconnected; if the switch-off is carried out, the counter is adjusted to a first value; if not, adjusting the server process to a second value; then the interface module judges whether the numerical value of the counter is not less than the global quantum time; if not, monitoring the server process; and continuing to execute the step of judging whether the server process is disconnected.
Specifically, the interface module may determine whether a communication connection established by the server process is disconnected, and if the connection is disconnected, it indicates that a disconnection event occurs, adjust the counter to a first value; if not, the server process is used for continuously reading data, monitoring the server process continuously, and meanwhile the counter is adjusted to a second value; then the interface module judges whether the value of the counter is not less than the set global quantum time, if so, the simulation period is not finished, the monitoring of the server process is required to be continued, namely, the server process continues to execute the operation of reading data; if the value of the counter is smaller than the global quantum time, the simulation clock period is ended, and the next simulation clock period needs to be promoted.
It should be noted that the value of the counter in this embodiment is used to characterize the simulation progress of the interface module in this simulation clock cycle.
It should be noted that, when it is determined that the communication connection established by the server process is disconnected, the server process continues to monitor the server, because the server process may reestablish the communication connection at any time, and then continues to perform the step of determining whether the communication connection established by the server process is disconnected.
It should be noted that, after the interface module performs the value adjustment of the counter, the interface module may advance the value of the counter by calling an inc method of the Keeper, then compare the value of the counter with the global quantum time, assign different values to the counter according to different Socket events, advance the simulation time to different degrees until the global quantum time is reached, call the Sync of the Keeper to synchronize, then jump out of the process of the interface module, and enter the next simulation clock cycle.
It should be noted that, before the step of determining whether the server process is disconnected is performed, the interface module may initialize in global quantum time, then create the server process, and after the server process is created, bind the server process and the port, so that the server process establishes a communication connection through the bound port, and the communication connection created by the server process and the communication connection created by the client process in the peer-to-peer chip form the unidirectional serial communication connection. Then the interface module can monitor the bound port and then execute the step of judging whether the server process is disconnected.
For better understanding of the above process, the Server process is taken as a Socket Server process (denoted as Socket Server process), and the following example is taken for explanation, where the first value may be, but is not limited to, 10, and the second value may be, but is not limited to, 4, to describe monitoring of the Server process by the interface module:
step 1: initializing a global quantum time, configured in this example as 20;
step 2: creating a Socket Server process;
step 3: binding a Port by a Socket Server process;
step 4: the Socket Server process monitors the bound Port;
step 5: calling a Select function of the Socket to trigger a Socket monitoring event;
step 6: judging whether a Socket connection established by a Socket Server process is closed or not, if the Socket connection is closed, jumping to Step 7, and if not, jumping to Step 10;
step 7: the counter value is advanced by 10, namely the counter value is increased by 10;
step 8: comparing the value of the counter with the set global quantum time, jumping to Step 9 if the value is not less than the global quantum time, and jumping to Step 5 if the value is less than the global quantum time;
step 9: executing Keeper synchronization, entering the next cycle by simulation, and jumping to Step 5;
step 10: reading data by using a Socket Server process;
step 11: the counter value advances forward 4;
step 12: comparing the value of the counter with the set global quantum time, jumping to Step 13 if the value is not less than the global quantum time, and jumping to Step 5 if the value is less than the global quantum time;
step 13: executing Keeper synchronization, entering the next cycle by simulation, and jumping to Step 5;
by implementing the chip verification system provided by the application, a multi-chip distributed simulation model which is difficult to construct by using a single SystemC model originally is constructed, and due to the use of SerDes links among Socket process simulation chips (TM chips and SW chips), a chip network has good expandability, and the development efficiency is improved. Socket processing and a model clock are decoupled through the Keeper, the processing of different Socket events can be advanced to simulation time in different degrees, and the sequential logic of hardware is simulated more accurately.
Based on the same inventive concept, the application also provides a chip verification method, which is applied to a Traffic Management (TM) chip in a chip verification system, wherein the chip verification system further comprises an exchange SW chip, at least one serial communication link is arranged between the TM chip and the SW chip, the TM chip and the SW chip are obtained by respectively adopting a system modeling language (SystemC) for modeling, the TM chip is provided with a communication service process corresponding to the serial communication link, and the SW chip is provided with a communication service process corresponding to the serial communication link; when the TM chip implements the chip verification method, the TM chip may implement the following procedure as shown in fig. 4:
s401, the TM chip sends first data to the SW chip through a corresponding serial communication link by using a communication service process in the TM chip, so that the SW chip reads the first data from the corresponding serial communication link by using the communication service process in the TM chip and executes corresponding verification operation.
S402, the TM chip reads second data sent by the SW chip from a corresponding serial communication link by utilizing a communication service process in the TM chip and executes corresponding verification operation.
It should be noted that, reference may be made to the related description about the TM chip in the chip verification system for implementation of steps S401 to S402, and details thereof are not listed here.
By adopting the chip verification method, the TM chip and the SW chip can carry out data transmission through a serial communication link between the two chips, namely, the TM chip and the SW chip can carry out data interaction through respective communication service processes, so that the verification of the data transmission function of the TM chip and the data transmission function of the SW chip can be finished, and the verification of the functions (except the verification related to the data interaction function) of the TM chip and the SW chip is combined, so that the simultaneous verification of each TM chip and each SW chip can be realized, and the problems of poor verification efficiency and poor networking flexibility caused by the fact that only single-chip verification can be realized in the prior art are solved.
Optionally, the communication service process corresponding to each serial communication link includes a client process and a server process; on this basis, step S401 may be performed according to the following procedure: and sending the first data to the SW chip through a corresponding serial communication link by utilizing a client process in the SW chip. On this basis, step S402 may be performed as follows: and reading the second data sent by the SW chip from the corresponding serial communication link by utilizing a server process in the serial communication link.
Specifically, the implementation of the above process can refer to the above TM chip for the related description of the client process and the server process, which is not listed in detail here.
Optionally, the TM chip includes an interface module for maintaining the communication service process; the chip verification method provided by the embodiment further includes:
the TM chip utilizes the interface module to adjust the counter through the set global quantum time so as to control the operation times of the communication service process for reading data and the operation times of the communication service process for establishing communication connection in the period.
In particular, the implementation of the above process can refer to the relevant description about the interface module in the chip verification system, which is not listed in detail here.
Based on the same inventive concept, the application also provides a chip verification method, which is applied to an exchange SW chip in a chip verification system, the chip verification system also comprises a traffic management TM chip, at least one serial communication link is arranged between the SW chip and the TM chip, the SW chip and the TM chip are obtained by respectively adopting a system modeling language SystemC, the SW chip is provided with a communication service process corresponding to the serial communication link, and the TM chip is provided with a communication service process corresponding to the serial communication link; when the SW implements the chip verification method, the process shown in fig. 5 may be implemented:
s501, the SW chip reads first data sent by the TM chip from a corresponding serial communication link by using a communication service process in the SW chip, and corresponding verification operation is executed by using the first data.
S502, the SW chip sends the second data to the TM chip through the corresponding serial communication link by using the communication service process in the SW chip, so that the TM chip reads the second data from the corresponding serial communication link by using the communication service process in the TM chip and executes the corresponding verification operation.
It should be noted that, reference may be made to the relevant description of the SW chip in the chip verification system, and details of the implementation of steps S501 to S502 are not listed here.
By adopting the chip verification method, the TM chip and the SW chip can carry out data transmission through a serial communication link between the two chips, namely, the TM chip and the SW chip can carry out data interaction through respective communication service processes, so that the verification of the data transmission function of the TM chip and the data transmission function of the SW chip can be finished, and the verification of the functions (except the verification related to the data interaction function) of the TM chip and the SW chip is combined, so that the simultaneous verification of each TM chip and each SW chip can be realized, and the problems of poor verification efficiency and poor networking flexibility caused by the fact that only single-chip verification can be realized in the prior art are solved.
Optionally, the communication service process corresponding to each serial communication link includes a client process and a server process; step S501 may be performed according to the following procedure: reading first data sent by the TM chip from a corresponding serial communication link by using a server process in the TM chip; step S502 may be performed according to the following procedure: and sending the second data to the TM chip through the corresponding serial communication link by using the client process in the TM chip.
Specifically, the implementation of the above process can refer to the above related description of the SW chip on the client process and the server process, which is not listed in detail here.
Optionally, the SW chip includes an interface module for maintaining the communication service process; on this basis, the chip verification method provided in this embodiment further includes: the SW chip utilizes the interface module to adjust the counter through the set global quantum time so as to control the operation times of the communication service process for reading data and the operation times of the communication service process for establishing communication connection in the period.
In particular, the implementation of the above process can refer to the relevant description about the interface module in the chip verification system, which is not listed in detail here.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The implementation process of the functions and actions of each unit/module in the above device is specifically described in the implementation process of the corresponding step in the above method, and is not described herein again.
For the device embodiments, since they substantially correspond to the method embodiments, reference may be made to the partial description of the method embodiments for relevant points. The above-described embodiments of the apparatus are merely illustrative, wherein the units/modules described as separate parts may or may not be physically separate, and the parts displayed as units/modules may or may not be physical units/modules, may be located in one place, or may be distributed on a plurality of network units/modules. Some or all of the units/modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (11)
1. A chip verification system is characterized by comprising at least one Traffic Management (TM) chip and at least one exchange SW chip, wherein at least one serial communication link is arranged between each TM chip and each SW chip, each TM chip and each SW chip are obtained by respectively adopting a system modeling language SystemC, each TM chip is provided with a communication service process corresponding to the serial communication link, each SW chip is provided with a communication service process corresponding to the serial communication link, and the traffic management system comprises:
each TM chip sends first data to the SW chip through the corresponding serial communication link by using the communication service process in the TM chip, so that the SW chip reads the first data from the corresponding serial communication link by using the communication service process in the SW chip;
each SW chip utilizes the communication service process in the SW chip to send the second data to the TM chip through the corresponding serial communication link, so that the TM chip utilizes the communication service process in the TM chip to read the second data from the corresponding serial communication link.
2. The system of claim 1, wherein the communication service process corresponding to each serial communication link comprises a client process and a server process; then
Each TM chip utilizes a client process in the TM chip to send first data to the SW chip through a corresponding serial communication link, so that the SW chip utilizes a server process in the SW chip to read the first data from the corresponding serial communication link;
and each SW chip utilizes the client process in the SW chip to send the second data to the TM chip through the corresponding serial communication link, so that the TM chip utilizes the server process in the TM chip to read the second data from the corresponding serial communication link.
3. The system of claim 1, wherein each TM chip and each SW chip respectively includes an interface module for maintaining the communication service process;
and the interface module adjusts a counter based on the set global quantum time so as to control the operation times of reading data by the communication service process and the operation times of establishing communication connection by the communication service process in the period.
4. The system of claim 3, wherein the communication service process maintained by the interface module is a server process; then
The interface module judges whether the progress of the server is disconnected; if the switch-off is carried out, the counter is adjusted to a first value; if not, adjusting the server process to a second value;
the interface module judges whether the numerical value of the counter is not less than the global quantum time; if the number of the processes is smaller than the preset number, monitoring the server process; and continuing to execute the step of judging whether the server process is disconnected.
5. The system of claim 4,
and the interface mode monitors the progress of the server by triggering a monitoring event.
6. A chip verification method is characterized in that the chip verification method is applied to a Traffic Management (TM) chip in a chip verification system, the chip verification system further comprises an exchange SW chip, at least one serial communication link is arranged between the TM chip and the SW chip, the TM chip and the SW chip are obtained by respectively adopting a system modeling language (SystemC) for modeling, the TM chip is provided with a communication service process corresponding to the serial communication link, and the SW chip is provided with a communication service process corresponding to the serial communication link; the method comprises the following steps:
the TM chip sends first data to the SW chip through a corresponding serial communication link by using a communication service process in the TM chip, so that the SW chip reads the first data from the corresponding serial communication link by using the communication service process in the SW chip and executes corresponding verification operation;
and the TM chip reads the second data sent by the SW chip from the corresponding serial communication link by utilizing a communication service process in the TM chip and executes corresponding verification operation.
7. The method of claim 6, wherein the communication service process corresponding to each serial communication link comprises a client process and a server process;
sending first data to the SW chip through a corresponding serial communication link by using a communication service process in the SW chip, comprising:
the client process in the system is utilized to send the first data to the SW chip through a corresponding serial communication link;
reading second data sent by the SW chip from a corresponding serial communication link by utilizing a communication service process in the communication service process, and the method comprises the following steps:
and reading the second data sent by the SW chip from the corresponding serial communication link by utilizing a server process in the serial communication link.
8. The method of claim 6, wherein the TM chip comprises an interface module for maintaining the communication service process; the method further comprises the following steps:
the TM chip utilizes the interface module to adjust the counter through the set global quantum time so as to control the operation times of the communication service process for reading data and the operation times of the communication service process for establishing communication connection in the period.
9. A chip verification method is characterized in that the chip verification method is applied to an exchange SW chip in a chip verification system, the chip verification system also comprises a traffic management TM chip, at least one serial communication link is arranged between the SW chip and the TM chip, the SW chip and the TM chip are obtained by respectively adopting a system modeling language SystemC, the SW chip is provided with a communication service process corresponding to the serial communication link, and the TM chip is provided with a communication service process corresponding to the serial communication link; the method comprises the following steps:
the SW chip reads first data sent by the TM chip from a corresponding serial communication link by using a communication service process in the SW chip and executes corresponding verification operation by using the first data;
and the SW chip utilizes the communication service process in the SW chip to send the second data to the TM chip through the corresponding serial communication link, so that the TM chip utilizes the communication service process in the TM chip to read the second data from the corresponding serial communication link and execute corresponding verification operation.
10. The method of claim 9, wherein the communication service process corresponding to each serial communication link comprises a client process and a server process; then
Reading first data sent by the TM chip from a corresponding serial communication link by using a communication service process in the TM chip, wherein the reading comprises the following steps:
reading first data sent by the TM chip from a corresponding serial communication link by using a server process in the TM chip;
and sending the second data to the TM chip through a corresponding serial communication link by using a communication service process in the TM chip, wherein the method comprises the following steps:
and sending the second data to the TM chip through the corresponding serial communication link by using the client process in the TM chip.
11. The method of claim 9, wherein the SW chip includes an interface module for maintaining the communication service process; the method further comprises the following steps:
the SW chip utilizes the interface module to adjust the counter through the set global quantum time so as to control the operation times of the communication service process for reading data and the operation times of the communication service process for establishing communication connection in the period.
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