CN108122761A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN108122761A CN108122761A CN201611085957.6A CN201611085957A CN108122761A CN 108122761 A CN108122761 A CN 108122761A CN 201611085957 A CN201611085957 A CN 201611085957A CN 108122761 A CN108122761 A CN 108122761A
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- side wall
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 89
- 238000000034 method Methods 0.000 title claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 123
- 238000012545 processing Methods 0.000 claims abstract description 25
- 230000009467 reduction Effects 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims description 137
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 238000003851 corona treatment Methods 0.000 claims description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 210000002381 plasma Anatomy 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 16
- 239000007789 gas Substances 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 15
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 125000006850 spacer group Chemical group 0.000 claims description 12
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 10
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- 229910052582 BN Inorganic materials 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- 229910003978 SiClx Inorganic materials 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 13
- 238000006731 degradation reaction Methods 0.000 abstract description 13
- 238000005516 engineering process Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 106
- 229910052751 metal Inorganic materials 0.000 description 14
- 239000002184 metal Substances 0.000 description 14
- 239000003989 dielectric material Substances 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 5
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- 241000406668 Loxodonta cyclotis Species 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- -1 by percent by volume Chemical compound 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of semiconductor structure and forming method thereof, forming method includes：Substrate is provided, the substrate includes substrate and the fin on the substrate；Form gate structure；Form source and drain doping area；Forerunner's side wall is formed on side wall of the gate structure towards the source and drain doping area；Form the pseudo- side wall positioned at forerunner's side wall side wall；Form dielectric layer；Reduction processing is carried out to forerunner's side wall, exposes the partial sidewall of the gate structure, remaining forerunner's side wall is used to form turning side wall；The pseudo- side wall is removed, vacuum side wall is formed between the gate structure and the dielectric layer.The technology of the present invention side is conducive to improve transistor conduct resistance and conducting electric current performance degradation problem, is conducive to improve the performance for forming semiconductor structure.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
With the rapid development of semiconductor fabrication, semiconductor devices is towards higher component density and higher collection
The direction of Cheng Du is developed.Transistor is just being widely used at present as most basic semiconductor devices, therefore with semiconductor device
The raising of the component density and integrated level of part, the size of transistor are also less and less.Short-channel effect and grid under small size
The problem of leakage current, makes the performance depreciation of transistor, therefore improves performance face by reducing the physical size of conventional transistor
Face a series of difficulty.
III-V race's semi-conducting material (for example, InGaAs) becomes current research due to its outstanding electron transport performance
Hot spot.In order to solve the difficulty that conventional semiconductor devices physical size is difficult to further reduce, the prior art proposes using III-
V race's semi-conducting material forms the technical solution of transistor channel, to improve the performance of transistor.
But in the prior art, III-V race's semi-conducting material still needs as the semiconductor structure performance of channel material
It improves.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of semiconductor structure and forming method thereof, to improve the property of semiconductor structure
Energy.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：
Substrate is provided, the substrate includes substrate and the fin on the substrate；It is formed and is located on the fin
Gate structure, the gate structure is across the fin and the surface of the covering fin atop part and partial sidewall；Institute
It states and source and drain doping area is formed in the fin of gate structure both sides；The shape on side wall of the gate structure towards the source and drain doping area
Into forerunner's side wall；Form the pseudo- side wall positioned at forerunner's side wall side wall；In the gate structure, forerunner's side wall and institute
It states and dielectric layer is formed in the substrate that pseudo- side wall exposes, the dielectric layer exposes the gate structure, forerunner's side wall and institute
State pseudo- side wall；Reduction processing is carried out to forerunner's side wall, exposes the partial sidewall of the gate structure, the remaining forerunner
Side wall is used to form turning side wall；The pseudo- side wall is removed, inlet side is formed between the gate structure and the dielectric layer
Wall.
Optionally, in the step of forming forerunner's side wall, the material of forerunner's side wall is silica, silicon nitride, carbon
One or more in SiClx, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride or boron carbonitrides.
Optionally, the step of forming forerunner's side wall includes：Side wall is formed on the gate structure and the substrate
Material layer；The spacer material layer on the gate structure and in the substrate is removed, is formed and is located at the gate structure sidewall
Forerunner's side wall.
Optionally, remove on the gate structure and the substrate on the upside of the walling bed of material the step of include：To the grid
The walling bed of material carries out the first corona treatment in the structure of pole and on the upside of the substrate；Removed by way of wet method through wait from
The portion of material of daughter processing, forms forerunner's side wall.
Optionally, formed after forerunner's side wall, formed before the pseudo- side wall, the forming method further includes：To separate
Part forerunner's side wall of the substrate carries out the second corona treatment；The step of reduction processing is carried out to forerunner's side wall bag
It includes：Plasma-treated portion of material is removed by way of wet method.
Optionally, in the step of forming forerunner's side wall, the material of forerunner's side wall is silicon nitride；Described first etc.
One or two step in the step of the step of gas ions processing and second corona treatment includes：Using H2 or He
Plasma carries out gas ions processing.
Optionally, using H2Or He plasmas were carried out in the step of gas ions processing, technological parameter includes：Process gas
Pressure is in the range of 2mTorr to 100mTorr, H2Or He flows, in the range of 50sccm to 500sccm, technological temperature is at 0 DEG C
To in the range of 100 DEG C.
Optionally, in the step of forming forerunner's side wall, the material of forerunner's side wall is silicon nitride；Pass through wet method
Mode, which removes the step of plasma-treated portion of material, to be included：Plasma-treated part is removed using hydrofluoric acid
Material.
Optionally, in the step of forming the vacuum side wall, along the direction of the vertical substrate surface, the inlet side
The ratio between wall size and the turning side wall size are 5:4 to 5:In the range of 1.
Optionally, in the step of forming source and drain doping area, along the fin extending direction, between the source and drain doping area
Distance is more than the size of the gate structure；The step of forming forerunner's side wall includes：In the source and drain doping area and the grid
Forerunner's side wall is formed on fin between structure.
Optionally, in the step of forming the pseudo- side wall, the material of the puppet side wall is polysilicon.
Optionally, the step of removing the pseudo- side wall includes：The pseudo- side wall is removed by way of chemical diffusion etching.
Optionally, the step of removing the pseudo- side wall by way of chemical diffusion etching includes：Using NH3Described in removal
Pseudo- side wall.
Optionally, in the step of providing the substrate, the material of the fin is III-V race's semi-conducting material.
Optionally, in the step of providing the substrate, the material of the fin is InGaAs.
Correspondingly, the present invention also provides a kind of semiconductor structure, including：
Substrate, the substrate include substrate and the fin on the substrate；Dielectric layer in the substrate；Position
In the gate structure in the dielectric layer on fin, the gate structure is across the fin and the covering fin atop part
With the surface of partial sidewall；Source and drain doping area in the fin of the gate structure both sides；Positioned at the gate structure direction
Turning side wall on source and drain doping area side wall；Vacuum side wall between the gate structure and the dielectric layer.
Optionally, the material of the turning side wall for silica, silicon nitride, carborundum, carbonitride of silicium, carbon silicon oxynitride,
One or more in silicon oxynitride, boron nitride or boron carbonitrides.
Optionally, along the direction of the vertical substrate surface, the inlet side wall size and the turning side wall size
The ratio between 5:4 to 5:In the range of 1.
Optionally, the material of the fin is III-V race's semi-conducting material.
Optionally, the distance between described source and drain doping area is more than the size of the gate structure；The turning side wall position
In on the fin between the source and drain doping area and the gate structure.
Compared with prior art, technical scheme has the following advantages：
Technical solution of the present invention is and described by forming turning side wall on side wall of the gate structure towards source and drain doping area
The dielectric constant of turning spacer material is more than the dielectric constant of vacuum, so the setting of the turning side wall can effectively increase
The average dielectric constant of the turning side wall and the vacuum side wall maintains smaller edge capacitance so as to not only improve, also has
Beneficial to transistor conduct resistance and conducting electric current performance degradation problem is improved, be conducive to improve the property for forming semiconductor structure
Energy.
Description of the drawings
Fig. 1 to Figure 13 is the structural representation corresponding to each step of one embodiment of method for forming semiconductor structure of the present invention
Figure.
Specific embodiment
From background technology, III-V race's semi-conducting material is deposited as the semiconductor structure of channel material in the prior art
The poor-performing the problem of.The reason in conjunction with its poor-performing problem of the specificity analysis of III-V race's semi-conducting material：
The raceway groove that III-V race's semi-conducting material is formed is present with more significant quantum limitation effect and subband division is existing
As.Therefore with the reduction of channel length, III-V race's semi-conducting material is susceptible to grid as the semiconductor structure of channel material
The problem of dielectric layer is electrically isolated performance degradation, and gate tunneling electric current increases.
In order to suppressor grid leak electricity, III-V race's semi-conducting material as in the semiconductor structure of channel material, it is necessary to set
The larger gate dielectric layer of thickness.In order to improve influence of the gate dielectric layer thickness increase to device performance, draw in the semiconductor structure
The structure of vacuum side wall (vacuum spacer) is entered, i.e., has been realized and be electrically insulated with air between gate structure and dielectric layer.
But due to the smaller (K of the dielectric constant of airvacuum=1), so the setting of vacuum side wall can reduce the side of device
Edge capacitance (Fringing Capacitance), but the degeneration of transistor conduct resistance and conducting electric current performance is caused simultaneously,
Influence forms the performance of semiconductor structure.
To solve the technical problem, the present invention provides a kind of forming method of semiconductor structure, including：
Substrate is provided, the substrate includes substrate and the fin on the substrate；It is formed and is located on the fin
Gate structure, the gate structure is across the fin and the surface of the covering fin atop part and partial sidewall；Institute
It states and source and drain doping area is formed in the fin of gate structure both sides；The shape on side wall of the gate structure towards the source and drain doping area
Into forerunner's side wall；Form the pseudo- side wall positioned at forerunner's side wall side wall；In the gate structure, forerunner's side wall and institute
It states and dielectric layer is formed in the substrate that pseudo- side wall exposes, the dielectric layer exposes the gate structure, forerunner's side wall and institute
State pseudo- side wall；Reduction processing is carried out to forerunner's side wall, exposes the partial sidewall of the gate structure, the remaining forerunner
Side wall is used to form turning side wall；The pseudo- side wall is removed, inlet side is formed between the gate structure and the dielectric layer
Wall.
Technical solution of the present invention is and described by forming turning side wall on side wall of the gate structure towards source and drain doping area
The dielectric constant of turning spacer material is more than the dielectric constant of vacuum, so the setting of the turning side wall can effectively increase
The average dielectric constant of the turning side wall and the vacuum side wall maintains smaller edge capacitance so as to not only improve, also has
Beneficial to transistor conduct resistance and conducting electric current performance degradation problem is improved, be conducive to improve the property for forming semiconductor structure
Energy.
It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Referring to figs. 1 to Figure 13, show corresponding to each step of one embodiment of method for forming semiconductor structure of the present invention
Structure diagram.
As shown in Figure 1 to Figure 3, substrate is provided, the substrate includes substrate 100 and the fin on the substrate 100
130。
Wherein Fig. 1 is the three dimensional structure diagram of the substrate, and Fig. 2 is along the cross-sectional view of AA lines in Fig. 1；Figure
3 be along the cross-sectional view of BB lines in Fig. 1.
The substrate 100 is used to provide technological operation platform.
In the present embodiment, the material of the substrate 100 is monocrystalline silicon.In other embodiments of the invention, the substrate may be used also
Be multicrystalline silicon substrate, amorphous silicon substrate or germanium silicon substrate, carbon silicon substrate, silicon-on-insulator substrate, germanium substrate on insulator,
Glass substrate or III-V compound substrate, such as gallium nitride substrate or gallium arsenide substrate etc..The material of the substrate can
To choose the material for being suitable for process requirements or being easily integrated.
The fin 130 is used to provide the raceway groove of the fin formula field effect transistor.
In the present embodiment, the material of the fin 130 is III-V race's semi-conducting material.Specifically, the fin 130
Material is InGaAs.In other embodiments of the invention, the material of the fin or other III-V race's semi-conducting materials.
III-V race's semi-conducting material becomes the preferable channel material of transistor with its higher low field electron mobility, is conducive to reduce
The channel length of transistor improves the integrated level of semiconductor structure.
The step of forming the substrate 100 and the fin 130 includes：Substrate 100 is provided；The shape on the substrate 100
Into fin material layer；Patterned fin mask layer is formed in the fin material layer；Using the fin mask layer as mask
It etches the fin material layer and forms fin 130.
The fin material layer is used to etch to form fin 130.
In the present embodiment, the material of the fin 130 is InGaAs.So the material of the fin material layer is also
InGaAs can be formed by way of chemical vapor deposition, physical vapour deposition (PVD) or atomic layer deposition.
It should be noted that in the present embodiment, the substrate further include positioned at the substrate 100 and the fin 130 it
Between oxide layer 110.The oxide layer 110 is used to provide good interface basis for the fin material layer, the shape to improve
Into the quality of fin material layer.So after providing substrate 100, formed before fin material layer, the forming method further includes：
Oxide layer is formed on the substrate 100.
The fin mask layer is used to define size and the position of the fin 130.
The step of forming the fin mask layer includes：Mask layer is formed in the fin material layer；Described
Graph layer is formed on mask layer；Using the graph layer as mask, the mask layer is etched, exposes the fin material
Layer, to form the fin mask layer.
The graph layer is for being patterned the mask layer, to define the size of the fin and position.
In the present embodiment, the graph layer is patterned photoresist layer, can pass through coating process and photoetching process shape
Into.In other embodiments of the invention, mask that the graph layer can also be formed by multiple graphical masking process, to reduce
The distance between the characteristic size of fin and adjacent fin improve the integrated level for forming semiconductor structure.Wherein multigraph
Shape masking process includes：Self-alignment duplex pattern (Self-aligned Double Patterned, SaDP) technique, from
It is directed at triple graphical (Self-aligned Triple Patterned) techniques or the graphical (Self- of autoregistration quadruple
Aligned Double Double Patterned, SaDDP) technique.
With continued reference to Fig. 1 to Fig. 3, the gate structure being located on the fin 130 is formed, the gate structure is across described
Fin 130 and the surface of covering 130 atop part of fin and partial sidewall.
In the present embodiment, the gate structure is the puppet for the position that takes up space by follow-up formation metal gate structure
Grid structure 121.In other embodiments of the invention, the gate structure can also be the gate structure of formed semiconductor structure.
In the present embodiment, dummy gate structure 121 can be laminated construction, including the pseudo- oxide layer being located in the substrate
And the dummy grid in the pseudo- oxide layer.The material of the dummy grid is polysilicon, and the material of the puppet oxide layer can
Think silica and silicon oxynitride.
In other embodiments of the invention, the material of the dummy grid can also be silica, silicon nitride, silicon oxynitride, carbon
The other materials such as SiClx, carbonitride of silicium, carbon silicon oxynitride or amorphous carbon.In other embodiments of the invention, dummy gate structure
Can also be single layer structure, material can be selected from polysilicon, silica, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium, carbon
One or more of other materials such as silicon oxynitride or amorphous carbon.
The step of forming dummy gate structure 121 includes：Pseudo- gate material layer is formed on the substrate；In the pseudo- grid material
Pseudo- grid mask layer is formed on the bed of material, using the pseudo- grid mask layer as mask, the pseudo- gate material layer is etched, forms the pseudo- grid knot
Structure 121.
With continued reference to Fig. 1 to Fig. 3, source and drain doping area 131 is formed in fin 130 in the gate structure both sides.
Specifically, in the present embodiment, the gate structure is pseudo- grid structure 121.So form the step in source and drain doping area 131
Suddenly include：Source and drain doping area 131 is formed in 121 both sides fin 130 of dummy gate structure.
In the present embodiment, the semiconductor structure is NMOS transistor, so the Doped ions in the source and drain doping area 131
For N-type ion, such as P, As or Sb.In other embodiments of the invention, the semiconductor structure or PMOS transistor, institute
Using the Doped ions in the source and drain doping area as p-type ion, such as B, Ga or In.
In the present embodiment, it is more than along the distance between 130 extending direction of fin, described source and drain doping area 131 described
The size of pseudo- grid structure 121, that is to say, that there is the semiconductor structure bottom to expose source/drain regions (gate-to-
Source/drain underlap) structure.This structure advantageously reduces the edge electricity of drain terminal in formed semiconductor structure
Hold, so as to improve the performance of formed semiconductor structure.So it is used to be formed the part of raceway groove between the source and drain doping area 131
Fin 130 is not covered by dummy gate structure 121, that is to say, that 121 exposed portion source and drain doping area 131 of dummy gate structure
Between for forming the fin 130 of raceway groove.
The step of source and drain doping area 131 are formed in the present embodiment includes：By to 121 both sides of dummy gate structure
The mode that fin 130 carries out ion implanting forms the source and drain doping area 131.But in other embodiments of the invention, the source
Leakage doped region can also be formed in the fin by way of epitaxial growth.
With reference to figure 4 to Fig. 7, forerunner's side wall is formed on side wall of the gate structure towards the source and drain doping area 131
144。
Wherein Fig. 4 and Fig. 6 is the cross-sectional view corresponding to Fig. 2；Fig. 5 and Fig. 7 is the cross-section structure corresponding to Fig. 3
Schematic diagram.
In the present embodiment, the gate structure is pseudo- grid structure 121.So the step of forming forerunner side wall 144 includes：
Dummy gate structure 121 is towards forming forerunner's side wall 144 on the side wall in the source and drain doping area 131.
Forerunner's side wall 144 is used to take up space for the formation of follow-up vacuum side wall, is additionally operable to etching and forms turning side
Wall.In addition, in the present embodiment, the gate structure is pseudo- grid structure 121, so after forerunner's side wall 144 is additionally operable to definition
Continuous size and the position for forming gate structure.
In the present embodiment, the distance between described source and drain doping area 131 is more than the size of the gate structure.So it is formed
The step of forerunner's side wall 144, includes：Shape on fin 130 between the source and drain doping area 131 and the gate structure
Into forerunner's side wall 144.
The material of forerunner's side wall 144 is silicon nitride.In other embodiments of the invention, the material of forerunner's side wall is also
Can be silica, carborundum, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride or one kind or more in boron carbonitrides
Kind
The step of forming forerunner's side wall 144 includes：Spacer material is formed on the gate structure and the substrate
Layer 143；The spacer material layer on the gate structure and in the substrate is removed, is formed positioned at the gate structure sidewall
Forerunner's side wall 144.
In the present embodiment, the step of forming forerunner's side wall 144, includes：As shown in figure 4, in dummy gate structure 121
With formation spacer material layer 143 in the substrate；As shown in figure 5, in removal dummy gate structure 121 and in the substrate
Spacer material layer forms forerunner's side wall 144 positioned at 121 side wall of dummy gate structure.
Remove on the gate structure and the substrate on the upside of the walling bed of material 143 the step of include：To the grid knot
The walling bed of material 143 carries out the first corona treatment 210 on structure and on the upside of the substrate；It is removed by way of wet method through institute
The portion of material of the first corona treatment 210 is stated, forms forerunner's side wall 144.
Specifically, include in removal dummy gate structure 121 and on the upside of the substrate the step of walling bed of material 143：It is right
The walling bed of material 143 carries out the first corona treatment 210 in dummy gate structure 121 and on the upside of the substrate；Pass through wet method
Mode remove the portion of material through the first corona treatment, form forerunner's side wall 144.
Wherein, in the present embodiment, the material of forerunner's side wall is silicon nitride.So first corona treatment
In 210 the step of, using H2Or He plasmas carry out gas ions processing, technological parameter includes：Process gas pressure exists
In the range of 2mTorr to 100mTorr, H2Or He gas flows, in the range of 50sccm to 500sccm, Ar gas flows exist
In the range of 0sccm to 200sccm, technological temperature is in the range of 0 DEG C to 100 DEG C；The mode of the wet etching remove through wait from
The step of portion of material of daughter processing, includes：Plasma-treated portion of material, wherein hydrogen fluorine are removed using hydrofluoric acid
Acid is diluted hydrofluoric acid, i.e., by percent by volume, the concentration of hydrofluoric acid is in the range of 1/2000 to 1/100.
The method that using plasma processing is combined with the mode of wet etching to the spacer material layer 143 with compared with
High etching selection ratio, so as to it is effective reduce formed the processing step of forerunner's side wall 144 in substrate other half
The influence of conductor structure is conducive to improve yield, is conducive to improve the performance for forming semiconductor structure.
With reference to reference to figure 8 and Fig. 9, the pseudo- side wall 145 positioned at 144 side wall of forerunner's side wall is formed.
Wherein, Fig. 8 is the cross-sectional view corresponding to Fig. 6, and Fig. 9 is the cross-sectional view corresponding to Fig. 7.
The puppet side wall 145 is used to take up space for the formation of follow-up vacuum side wall.
Specifically, in the present embodiment, the material of the puppet side wall 145 is polysilicon.The step of forming pseudo- side wall 145
Including：Pseudo- side wall is formed on the surface of the substrate, dummy gate structure 121 (as shown in Figure 6) and forerunner's side wall 144
Material layer；The pseudo- spacer material layer on the substrate, dummy gate structure 121 and forerunner's side wall 144 is removed, positioned at institute
The remaining pseudo- spacer material layer of 144 side wall of forerunner's side wall is stated for forming the pseudo- side wall 145.
It should be noted that as shown in fig. 7, after formation forerunner side wall 144, formed before the pseudo- side wall 145, it is described
Forming method further includes：Second corona treatment 220 is carried out to part forerunner's side wall 144 away from the substrate 100.
Second corona treatment 220 is used to provide Process ba- sis to be subsequently formed turning side wall, so as to reduce
State influence of the formation of turning side wall to other semiconductor structures in substrate.
Specifically, in the step of the second corona treatment 220, using H2Or He plasmas are carried out at gas ions
Reason, technological parameter include：Process gas pressure is in the range of 2mTorr to 100mTorr, H2Or He gas flows are arrived in 50sccm
In the range of 500sccm, Ar gas flows are in the range of 0sccm to 200sccm, and technological temperature is in the range of 0 DEG C to 100 DEG C.
It should be noted that in the present embodiment, the step of the first corona treatment 210 and second plasma
The step of body processing 220 adopts to be handled in a like fashion.This way is only an example, other embodiments of the invention
In, it is also carried out in different ways with the step of second corona treatment the step of first corona treatment
Processing.
With continued reference to Fig. 8 and Fig. 9, expose in the gate structure, forerunner's side wall 144 and the pseudo- side wall 145
Substrate on form dielectric layer 150, the dielectric layer 150 exposes the gate structure, forerunner's side wall 144 and the puppet
Side wall 145.
The dielectric layer 150 is used to implement the electric isolution between adjacent semiconductor constructs, is additionally operable to define and is subsequently formed
The size of vacuum side wall and position.
In the present embodiment, the dielectric layer 150 is interlayer dielectric layer, and material is silica.In other embodiments of the invention,
The material of the dielectric layer is also selected from other dielectric materials such as silicon nitride, silicon oxynitride or carbon silicon oxynitride.
The step of forming dielectric layer 150 includes：By chemical vapor deposition (such as：Fluid chemistry is vapor-deposited) etc.
Medium is formed in the substrate that method is exposed in dummy gate structure 121, forerunner's side wall 144 and the pseudo- side wall 145
Material layer, the layer of dielectric material cover dummy gate structure 121；Removal is higher than the layer of dielectric material of dummy gate structure 121,
Expose dummy gate structure 121, forerunner's side wall 144 and the pseudo- side wall 145.
It should be noted that in the present embodiment, the gate structure is pseudo- grid structure 121, so with continued reference to Fig. 8 and figure
9, it is formed after the dielectric layer 150, removal dummy gate structure 121 is (as shown in Figure 6) to form opening and in the opening
Form metal gate structure 120.
In the present embodiment, the semiconductor structure has " high-K metal gate " structure；So removal dummy gate structure 121
The step of for forming metal gate structure.
Dummy gate structure 121 covers the part surface of 130 top of fin and side wall across the fin 130,
Therefore the open bottom that removal dummy gate structure 121 is formed exposes the part surface of 130 top of fin and side wall.Institute
With the metal gate structure 120 that is formed in the opening also across the fin 130, and cover the fin 130 and push up
Portion and the part surface of side wall.
The metal gate structure 120 includes being located at the gate dielectric layer (not shown) of the substrate uplink and be located at
Gate electrode (not indicated in figure) on the gate dielectric layer.
The gate dielectric layer is used to implement the electric isolution between formed gate structure and substrate interior raceway groove.The gate medium
The material of layer is high K dielectric material.Wherein, high K dielectric material refers to that relative dielectric constant is more than silica relative dielectric constant
Dielectric material.Specifically, the material of the gate dielectric layer is HfO2.In other embodiments of the invention, the gate dielectric layer
Material is also selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3Deng.
The gate electrode layer is used as electrode, and realization is electrically connected with external circuit.In the present embodiment, the gate electrode layer
Material be W.In other embodiments of the invention, the material of the gate electrode layer can also be Al, Cu, Ag, Au, Pt, Ni or Ti
Deng.
It should be noted that since the material of the fin 130 is InGaAs, so being other semiconductors with fin material
The technical solution of material is compared, and in the present embodiment, the thickness of the gate dielectric layer is larger so that the gate dielectric layer have compared with
Big equivalent oxide (Equivalent Oxide Thickness) thickness is larger, with suppressor grid leakage current.Specifically, this
In embodiment, the thickness of the gate dielectric layer existsIt arrivesIn the range of.
With reference to figure 10 and Figure 11, reduction processing is carried out to forerunner's side wall 144 (as shown in Figure 8 and Figure 9), described in exposing
The partial sidewall of gate structure, remaining forerunner's side wall 144 are used to form turning side wall 141.
In the present embodiment, the gate structure is metal gate structure 120, so the step of carrying out reduction processing includes：
Reduction processing is carried out to forerunner's side wall 144, exposes the partial sidewall of the metal gate structure 120, forms turning side wall
141。
Wherein, Figure 10 is the cross-sectional view corresponding to Fig. 8；Figure 11 is the cross-sectional view corresponding to Fig. 9.
The turning side wall 141 is used to realize gate structure and other semiconductors together with the vacuum side wall subsequently formed
Electric isolution between structure.
The dielectric constant of 141 material of turning side wall is more than the dielectric constant of vacuum, so the turning side wall 141
The problem of being provided with beneficial to transistor conduct resistance and conducting electric current performance degradation is improved, it is existing to advantageously reduce delay (delay)
The appearance of elephant is conducive to improve the performance for forming semiconductor structure.
The material of forerunner's side wall 144 (as shown in Figure 8 and Figure 9) is silicon nitride, that is to say, that the turning side wall 141
Material be silicon nitride.The dielectric constant of silicon nitride is 7.5, so the formation of the turning side wall 141 of silicon nitride material, is conducive to
The problem of improving transistor conduct resistance and conducting electric current performance degradation.
In the present embodiment, portion of material of the forerunner's side wall 144 away from the substrate 100 is by the second plasma
Managed for 220 (as shown in Figure 6 and Figure 7), so the step of carrying out reduction processing to forerunner's side wall 144 includes：Pass through wet method
Mode removes plasma-treated portion of material.
The step of removing plasma-treated portion of material includes：It is removed using hydrofluoric acid through second plasma
The portion of material of processing 220.Specifically, in the step of removing portion of material using hydrofluoric acid, by percent by volume, hydrofluoric acid
Concentration is in the range of 1/2000 to 1/100.It should be noted that percent by volume therein refers to the volume basis of HF and water
Than.
It should be noted that in the present embodiment, remove through the step of the first corona treatment portion of material and removal
It adopts through the step of the second corona treatment portion of material and is removed in a like fashion.In other embodiments of the invention,
Removal is through the step of the first corona treatment portion of material and the step of removal is through the second corona treatment portion of material
It can also be removed in different ways.
After the plasma treatment, the mode of wet etching is higher to the etch rate of forerunner's side wall 144, therefore
Using plasma processing the material that modes remove part forerunner's side wall 144 such as is combined with wet etching, can be effective
Influence of the reduction reduction process to other semiconductor structures in substrate, be conducive to improve yield, be conducive to improve and formed partly
The performance of conductor structure.
It should be noted that as shown in figure 11, in the present embodiment, forerunner's side wall 144 is (as shown in Figure 10) to be located at institute
It states between source and drain doping area 131 and the gate structure 120, so the turning side wall 141 also is located at the source and drain doping area
Between 131 and the gate structure 120.This way is conducive to the conducting resistance and capacitance that optimization forms semiconductor structure
Performance, so as to improve delay issue.
With reference to figure 12 and Figure 13, the pseudo- side wall 145, the shape between the gate structure and the dielectric layer 150 are removed
Into vacuum side wall 142.
The vacuum side wall 142 forms the problem of conducting electric current reduces in semiconductor structure for improving, and improves larger
Influence of the gate dielectric layer of thickness to formed semiconductor structure.The dielectric constant of vacuum side wall 142 is relatively low, is conducive to reduce institute
Form the edge capacitance (Fringing Capacitance) of semiconductor structure.
The step of removing pseudo- side wall 145 includes：The pseudo- side wall 145 is removed by way of chemical diffusion etching.
After removing the pseudo- side wall 145, the metal gate structure 120, the turning side wall 141 and the dielectric layer 150 it
Between form gap, the gap is for forming the vacuum side wall 142.
In the present embodiment, the step of removing pseudo- side wall 145 by way of chemical diffusion etching, includes：Using NH3
Remove the pseudo- side wall 145.Specifically, using Frontier boards, using NH3Institute is removed by way of chemical diffusion etching
State pseudo- side wall 145.Since the material of the pseudo- side wall 145 is polysilicon, the quarter of the lithographic method polycrystalline silicon material of this sample loading mode
Erosion rate is larger, therefore the way for removing the pseudo- side wall 145 in this way effectively can reduce to form the vacuum
Influence of 142 technique of side wall to other semiconductor structures, is conducive to the raising of yield, the improvement of device performance.
It should be noted that on the direction of the vertical substrate surface, size and the turning of the vacuum side wall 142
The ratio between size of side wall 141 should not it is too big also should not be too small.
On the direction of the vertical substrate surface, the size of the vacuum side wall 142 and the size of the turning side wall 141
If the ratio between it is too big, i.e., vacuum side wall 142 is oversized, turning side wall 141 it is undersized, then vacuum side wall 142 with turn
The average dielectric constant of angle side wall 141 is smaller, can influence to improve the function of conducting resistance and conducting electric current performance degradation problem；Institute
If size and the ratio between the size of the turning side wall 141 of stating vacuum side wall 142 are too small, i.e. the size mistake of vacuum side wall 142
It is small, turning side wall 141 it is oversized, then the average dielectric constant of vacuum side wall 142 and turning side wall 141 is larger, also can shadow
Ringing improves the function of conducting resistance and conducting electric current performance degradation problem.Specifically, in the present embodiment, the vacuum side wall is formed
In 142 the step of, along the direction of the vertical substrate surface, 142 size of vacuum side wall and 141 ruler of turning side wall
It is the ratio between very little 5:4 to 5:In the range of 1.
Correspondingly, the present invention also provides a kind of semiconductor structure, as shown in figure 13, including：
Substrate, the substrate include substrate 100 and the fin 130 on the substrate 100；In the substrate
Dielectric layer 150；Gate structure on fin 130 in the dielectric layer 150, the gate structure is across the fin 130
And the surface of the covering fin atop part and partial sidewall；Source and drain in gate structure both sides fin 130 is mixed
Miscellaneous area 131；Positioned at the gate structure towards the turning side wall 141 on 131 side wall of source and drain doping area；Positioned at the grid
Vacuum side wall 142 between structure and the dielectric layer 150.
The substrate 100 is used to provide technological operation platform.
In the present embodiment, the material of the substrate 100 is monocrystalline silicon.In other embodiments of the invention, the substrate may be used also
Be multicrystalline silicon substrate, amorphous silicon substrate or germanium silicon substrate, carbon silicon substrate, silicon-on-insulator substrate, germanium substrate on insulator,
Glass substrate or III-V compound substrate, such as gallium nitride substrate or gallium arsenide substrate etc..The material of the substrate can
To choose the material for being suitable for process requirements or being easily integrated.
The fin 130 is used to provide the raceway groove of the fin formula field effect transistor.
In the present embodiment, the material of the fin 130 is III-V race's semi-conducting material.Specifically, the fin 130
Material is InGaAs.In other embodiments of the invention, the material of the fin or other III-V race's semi-conducting materials.
III-V race's semi-conducting material becomes the preferable channel material of transistor with its higher low field electron mobility, is conducive to reduce
The channel length of transistor improves the integrated level of semiconductor structure.
It should be noted that in the present embodiment, the substrate further include positioned at the substrate 100 and the fin 130 it
Between oxide layer 110.The oxide layer 110 is used to provide interface basis for the formation of the fin material, to improve the fin
The quality in portion 130.
The dielectric layer 150 is used to implement the electric isolution between adjacent semiconductor constructs, is additionally operable to define and is subsequently formed
The size of vacuum side wall and position.
In the present embodiment, the dielectric layer 150 is interlayer dielectric layer, and material is silica.In other embodiments of the invention,
The material of the dielectric layer is also selected from other dielectric materials such as silicon nitride, silicon oxynitride or carbon silicon oxynitride.
The gate structure is used to control the conducting of raceway groove in semiconductor structure and block.
In the present embodiment, the semiconductor structure has " high-K metal gate " structure, so the gate structure is metal gate
Pole structure 120.The metal gate structure 120 includes the gate dielectric layer (not shown) and position positioned at the substrate uplink
In the gate electrode (not indicated in figure) on the gate dielectric layer.
The gate dielectric layer is used to implement the electric isolution between formed gate structure and substrate interior raceway groove.The gate medium
The material of layer is high K dielectric material.Wherein, high K dielectric material refers to that relative dielectric constant is more than silica relative dielectric constant
Dielectric material.Specifically, the material of the gate dielectric layer is HfO2.In other embodiments of the invention, the gate dielectric layer
Material is also selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3Deng.
The gate electrode layer is used as electrode, and realization is electrically connected with external circuit.In the present embodiment, the gate electrode layer
Material be W.In other embodiments of the invention, the material of the gate electrode layer can also be Al, Cu, Ag, Au, Pt, Ni or Ti
Deng.
It should be noted that since the material of the fin 130 is InGaAs, so being other semiconductors with fin material
The technical solution of material is compared, and in the present embodiment, the thickness of the gate dielectric layer is larger so that the gate dielectric layer have compared with
Big equivalent oxide (Equivalent Oxide Thickness) thickness is larger, with suppressor grid leakage current.Specifically, this
In embodiment, the thickness of the gate dielectric layer existsIt arrivesIn the range of.
The source and drain doping area 131 is used to be formed source region or the drain region of the semiconductor structure.
In the present embodiment, the semiconductor structure is NMOS transistor, thus doping in the source and drain doping area 131 from
Son is N-type ion, such as P, As or Sb.In other embodiments of the invention, the semiconductor structure or PMOS transistor,
So the Doped ions in the source and drain doping area are p-type ion, such as B, Ga or In.
In the present embodiment, it is more than along the distance between 130 extending direction of fin, described source and drain doping area 131 described
The size of pseudo- grid structure 121, that is to say, that there is the semiconductor structure bottom to expose source/drain regions (gate-to-
Source/drain underlap) structure.This structure advantageously reduces the edge electricity of drain terminal in formed semiconductor structure
Hold, so as to improve the performance of formed semiconductor structure.So it is used to be formed the part of raceway groove between the source and drain doping area 131
Fin 130 is not covered by the metal gate structure 120, that is to say, that the 120 exposed portion source and drain of metal gate structure is mixed
It is used to be formed the fin 130 of raceway groove between miscellaneous area 131.
The turning side wall 141 is used to realize gate structure and other semiconductor structures together with the vacuum side wall 142
Between electric isolution.
The dielectric constant of 141 material of turning side wall is more than the dielectric constant of vacuum, so the turning side wall 141
The problem of being provided with beneficial to transistor conduct resistance and conducting electric current performance degradation is improved, it is existing to advantageously reduce delay (delay)
The appearance of elephant is conducive to improve the performance for forming semiconductor structure.
In the present embodiment, the material of the turning side wall 141 is silicon nitride.The dielectric constant of silicon nitride is 7.5, so nitrogen
The problem of turning side wall 141 of silicon nitride material is conducive to improve transistor conduct resistance and conducting electric current performance degradation.
In other embodiments of the invention, the material of the turning side wall can also be silica, carborundum, carbonitride of silicium,
One or more in carbon silicon oxynitride, silicon oxynitride, boron nitride or boron carbonitrides
In the present embodiment, the distance between described source and drain doping area 131 is more than the size of the gate structure, so described
Turning side wall 141 is on the fin 130 between the source and drain doping area 131 and the gate structure.
The vacuum side wall 142 forms the problem of conducting electric current reduces in semiconductor structure for improving, and improves larger
Influence of the gate dielectric layer of thickness to formed semiconductor structure.The dielectric constant of vacuum side wall 142 is relatively low, is conducive to reduce institute
Form the edge capacitance (Fringing Capacitance) of semiconductor structure.
It should be noted that on the direction of the vertical substrate surface, size and the turning of the vacuum side wall 142
The ratio between size of side wall 141 should not it is too big also should not be too small.
On the direction of the vertical substrate surface, the size of the vacuum side wall 142 and the size of the turning side wall 141
If the ratio between it is too big, i.e., vacuum side wall 142 is oversized, turning side wall 141 it is undersized, then vacuum side wall 142 with turn
The average dielectric constant of angle side wall 141 is smaller, can influence to improve the function of conducting resistance and conducting electric current performance degradation problem；Institute
If size and the ratio between the size of the turning side wall 141 of stating vacuum side wall 142 are too small, i.e. the size mistake of vacuum side wall 142
It is small, turning side wall 141 it is oversized, then the average dielectric constant of vacuum side wall 142 and turning side wall 141 is larger, also can shadow
Ringing improves the function of conducting resistance and conducting electric current performance degradation problem.Specifically, in the present embodiment, the vacuum side wall is formed
In 142 the step of, along the direction of the vertical substrate surface, 142 size of vacuum side wall and 141 ruler of turning side wall
It is the ratio between very little 5:4 to 5:In the range of 1.
To sum up, technical solution of the present invention by side wall of the gate structure towards source and drain doping area formed turning side wall,
And the dielectric constant of the turning spacer material is more than the dielectric constant of vacuum, so the setting of the turning side wall can be effective
The average dielectric constant for increasing the turning side wall and the vacuum side wall, maintain smaller edge electricity so as to not only improve
Hold, be also beneficial to improve transistor conduct resistance and conducting electric current performance degradation problem, be conducive to raising and form semiconductor junction
The performance of structure.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the scope of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure, which is characterized in that including：
Substrate is provided, the substrate includes substrate and the fin on the substrate；
The gate structure being located on the fin is formed, the gate structure is across the fin and the covering fin part top
Portion and the surface of partial sidewall；
Source and drain doping area is formed in the fin of the gate structure both sides；
Forerunner's side wall is formed on side wall of the gate structure towards the source and drain doping area；
Form the pseudo- side wall positioned at forerunner's side wall side wall；
Dielectric layer, the medium are formed in the substrate exposed in the gate structure, forerunner's side wall and the pseudo- side wall
Layer exposes the gate structure, forerunner's side wall and the pseudo- side wall；
Reduction processing is carried out to forerunner's side wall, exposes the partial sidewall of the gate structure, remaining forerunner's side wall
For forming turning side wall；
The pseudo- side wall is removed, vacuum side wall is formed between the gate structure and the dielectric layer.
2. forming method as described in claim 1, which is characterized in that in the step of forming forerunner's side wall, the forerunner
The material of side wall is silica, silicon nitride, carborundum, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride or carbon nitrogenize
One or more in boron.
3. forming method as described in claim 1, which is characterized in that the step of forming forerunner's side wall includes：
Spacer material layer is formed on the gate structure and the substrate；
The spacer material layer on the gate structure and in the substrate is removed, is formed before being located at the gate structure sidewall
Drive side wall.
4. forming method as claimed in claim 3, which is characterized in that remove on the gate structure and the substrate on the upside of
The step of walling bed of material, includes：
To the walling bed of material carries out the first corona treatment on the gate structure and on the upside of the substrate；
Plasma-treated portion of material is removed by way of wet method, forms forerunner's side wall.
5. forming method as described in claim 1, which is characterized in that formed after forerunner's side wall, formed the pseudo- side wall it
Before, the forming method further includes：Second corona treatment is carried out to part forerunner's side wall away from the substrate；
The step of carrying out reduction processing to forerunner's side wall includes：Plasma-treated portion is removed by way of wet method
Divide material.
6. forming method as described in claim 4 or 5, which is characterized in that in the step of forming forerunner's side wall, before described
The material for driving side wall is silicon nitride；
One or two step in the step of the step of first corona treatment and second corona treatment
Including：Using H2Or He plasmas carry out gas ions processing.
7. forming method as claimed in claim 6, which is characterized in that using H2Or He plasmas carry out gas ions processing
In step, technological parameter includes：Process gas pressure is in the range of 2mTorr to 100mTorr, H2Or He flows are arrived in 50sccm
In the range of 500sccm, technological temperature is in the range of 0 DEG C to 100 DEG C.
8. forming method as described in claim 4 or 5, which is characterized in that in the step of forming forerunner's side wall, before described
The material for driving side wall is silicon nitride；
The step of plasma-treated portion of material is removed by way of wet method includes：Using hydrofluoric acid removal through wait from
The portion of material of daughter processing.
9. forming method as described in claim 1, which is characterized in that in the step of forming the vacuum side wall, along vertical institute
It states on the direction of substrate surface, the ratio between the inlet side wall size and the turning side wall size are 5:4 to 5:In the range of 1.
10. forming method as described in claim 1, which is characterized in that in the step of forming source and drain doping area, along the fin
The distance between extending direction, the source and drain doping area is more than the size of the gate structure；
The step of forming forerunner's side wall includes：Described in being formed on fin between the source and drain doping area and the gate structure
Forerunner's side wall.
11. forming method as described in claim 1, which is characterized in that in the step of forming the pseudo- side wall, the puppet side wall
Material be polysilicon.
12. the forming method as described in claim 1 or 11, which is characterized in that the step of removing the pseudo- side wall includes：Pass through
The mode of chemical diffusion etching removes the pseudo- side wall.
13. forming method as claimed in claim 12, which is characterized in that remove the puppet by way of chemical diffusion etching
The step of side wall, includes：Using NH3Remove the pseudo- side wall.
14. forming method as described in claim 1, which is characterized in that in the step of substrate is provided, the material of the fin
Expect for III-V race's semi-conducting material.
15. the forming method as described in claim 1 or 14, which is characterized in that in the step of substrate is provided, the fin
Material be InGaAs.
16. a kind of semiconductor structure, which is characterized in that including：
Substrate, the substrate include substrate and the fin on the substrate；
Dielectric layer in the substrate；
Gate structure on fin in the dielectric layer, the gate structure is across the fin and the covering fin portion
At the top of point and surface of partial sidewall；
Source and drain doping area in the fin of the gate structure both sides；
Positioned at the gate structure towards the turning side wall on source and drain doping area side wall；
Vacuum side wall between the gate structure and the dielectric layer.
17. semiconductor structure as claimed in claim 16, which is characterized in that the material of the turning side wall is silica, nitrogen
One or more in SiClx, carborundum, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride or boron carbonitrides.
18. semiconductor structure as claimed in claim 16, which is characterized in that along the direction of the vertical substrate surface, institute
The ratio between inlet side wall size and the turning side wall size are stated 5:4 to 5:In the range of 1.
19. semiconductor structure as claimed in claim 16, which is characterized in that the material of the fin is III-V race's semiconductor
Material.
20. semiconductor structure as claimed in claim 16, which is characterized in that the distance between described source and drain doping area is more than institute
State the size of gate structure；
The turning side wall is located on the fin between the source and drain doping area and the gate structure.
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| CN109216192A (en) * | 2017-07-03 | 2019-01-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN112838048A (en) * | 2019-11-22 | 2021-05-25 | 联华电子股份有限公司 | Interconnection structure and manufacturing method thereof |
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| US20120104512A1 (en) * | 2010-10-28 | 2012-05-03 | International Business Machines Corporation | Sealed air gap for semiconductor chip |
| KR20130106622A (en) * | 2012-03-20 | 2013-09-30 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the device |
| US20150263122A1 (en) * | 2014-03-12 | 2015-09-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Air-gap offset spacer in finfet structure |
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| US20120104512A1 (en) * | 2010-10-28 | 2012-05-03 | International Business Machines Corporation | Sealed air gap for semiconductor chip |
| KR20130106622A (en) * | 2012-03-20 | 2013-09-30 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the device |
| US20150263122A1 (en) * | 2014-03-12 | 2015-09-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Air-gap offset spacer in finfet structure |
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| CN109216192A (en) * | 2017-07-03 | 2019-01-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN109216192B (en) * | 2017-07-03 | 2021-10-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN112838048A (en) * | 2019-11-22 | 2021-05-25 | 联华电子股份有限公司 | Interconnection structure and manufacturing method thereof |
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