CN110364483B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN110364483B
CN110364483B CN201810252695.0A CN201810252695A CN110364483B CN 110364483 B CN110364483 B CN 110364483B CN 201810252695 A CN201810252695 A CN 201810252695A CN 110364483 B CN110364483 B CN 110364483B
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source
drain doping
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CN110364483A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate and a fin part protruding out of the surface of the substrate, wherein an isolation layer is arranged on the substrate and covers partial side wall of the fin part, a grid electrode crossing the fin part is arranged on the isolation layer, the grid electrode covers the top and the side wall of the fin part, a source drain doping layer is arranged in the fin part on two sides of the grid electrode, and the source drain doping layer comprises a first source drain doping layer and a second source drain doping layer positioned on the top of the first source drain doping layer; forming a sacrificial layer on the isolation layer, wherein the sacrificial layer covers the side wall of the first source-drain doping layer and exposes the top and the side wall of the second source-drain doping layer; forming a first metal silicide layer on the top and the side wall of the second source drain doping layer; etching the sacrificial layer to expose the side wall of the first source drain doping layer; and forming a second metal silicide layer on the surface of the first metal silicide layer and the side wall of the first source drain doping layer. The invention can reduce leakage current, reduce contact resistance between the source-drain doped layer and a subsequently formed conductive plug, and improve electrical performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, as the feature size of integrated circuits continues to decrease, the channel length of MOSFETs has correspondingly continued to decrease. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, and short-channel effects (SCE) are more likely to occur.
The fin field effect transistor (FinFET) has outstanding performance in the aspect of inhibiting short channel effect, and the grid electrode of the FinFET can control the fin part at least from two sides, so that compared with a planar MOSFET, the grid electrode of the FinFET has stronger channel control capability, and the short channel effect can be well inhibited.
However, the electrical performance of the prior art semiconductor structures is still to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are beneficial to reducing leakage current, and are also beneficial to reducing the contact resistance between a source-drain doped layer and a subsequently formed conductive plug and improving the electrical property of the semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate and a fin part protruding out of the surface of the substrate, wherein the surface of the substrate is provided with an isolation layer, the isolation layer covers part of the side wall of the fin part, the surface of the isolation layer is provided with a grid electrode crossing the fin part, the grid electrode covers the top and the side wall of the fin part, the fin part on two sides of the grid electrode is internally provided with a groove and a source drain doping layer filled with the groove, and the source drain doping layer comprises a first source drain doping layer covering the bottom of the groove and a second source drain doping layer positioned at the top of the first source drain doping layer; forming a sacrificial layer on the surface of the isolation layer, wherein the sacrificial layer covers the side wall of the first source-drain doping layer, which is vertical to the extending direction of the grid electrode, and exposes the top of the second source-drain doping layer and the side wall, which is vertical to the extending direction of the grid electrode; forming a first metal silicide layer on the top and the side wall surface of the second source drain doping layer exposed out of the sacrificial layer; after the first silicide metal layer is formed, etching the sacrificial layer to expose the surface of the side wall of the first source drain doping layer; and forming a second metal silicide layer on the surface of the first metal silicide layer and the surface of the exposed side wall of the first source-drain doped layer.
Optionally, a ratio of the thickness of the first metal silicide layer to the thickness of the second metal silicide layer is 1.2-2.
Optionally, the thickness of the first metal silicide layer is
Figure BDA0001608204000000021
Optionally, the thickness of the second metal silicide layer is
Figure BDA0001608204000000022
Optionally, before the sacrificial layer is formed, the thickness of the second source-drain doped layer is as follows
Figure BDA0001608204000000023
Optionally, in the process of etching the sacrificial layer, the thickness of the exposed first source-drain doped layer is as follows
Figure BDA0001608204000000024
Optionally, in the process of etching the sacrificial layer, the surface of the sidewall of the first source-drain doped layer higher than the top of the isolation layer is completely exposed.
Optionally, before the sacrificial layer is formed, the top of the isolation layer is higher than the bottom of the first source-drain doping layer or is flush with the bottom of the first source-drain doping layer; and in the process of etching the sacrificial layer, removing the sacrificial layer with the whole thickness.
Optionally, the sacrificial layer is made of amorphous silicon, amorphous carbon, an anti-reflection coating material, an organic coating material, silicon oxide, silicon nitride, silicon oxycarbonitride or silicon oxynitride.
Optionally, before the sacrificial layer is formed, the top of the isolation layer is lower than the bottom of the first source drain doping layer; and in the process of etching the sacrificial layer, removing part of the sacrificial layer, wherein the top of the rest sacrificial layer is flush with the bottom of the first source-drain doping layer.
Optionally, the sacrificial layer is made of silicon oxide, silicon nitride, silicon oxycarbonitride or silicon oxynitride.
Optionally, the sacrificial layer is etched by using a dry etching process.
Optionally, the process method for forming the sacrificial layer includes: forming a sacrificial film covering the side wall of the first source-drain doping layer, the top of the second source-drain doping layer and the side wall on the isolation layer, wherein the top of the sacrificial film is higher than the top of the second source-drain doping layer; and removing part of the sacrificial film, and keeping the top of the remaining sacrificial film flush with the top of the first source-drain doping layer to form the sacrificial layer.
Optionally, a dielectric layer is formed on the surface of the isolation layer, the dielectric layer covers the surface of the sidewall of the sacrificial film, the sacrificial film and the dielectric layer are formed in the same process, and the material of the dielectric layer is the same as that of the sacrificial film; in the process of removing the sacrificial film with partial thickness, the bottom of the residual sacrificial film is lower than the top of the dielectric layer; a first opening is formed by the top of the sacrificial layer and the side wall of the dielectric layer in a surrounding mode; and after the first silicide metal layer is formed, etching the sacrificial layer, and forming a second opening at the bottom of the first opening, wherein the second opening exposes the side wall of the first source-drain doped layer.
Optionally, after forming the second metal silicide layer, the method further includes: and forming a conductive plug on the surface of the second metal silicide layer, wherein the first opening and the second opening are filled with the conductive plug.
Accordingly, the present invention also provides a semiconductor structure comprising: the semiconductor device comprises a substrate and a fin part protruding out of the substrate, wherein an isolation layer is arranged on the surface of the substrate and covers partial side walls of the fin part, a grid electrode crossing the fin part is arranged on the surface of the isolation layer, the grid electrode covers the top and the side walls of the fin part, a groove and a source drain doping layer filled with the groove are arranged in the fin part on two sides of the grid electrode, and the source drain doping layer comprises a first source drain doping layer covering the bottom of the groove and a second source drain doping layer located on the top of the first source drain doping layer; the first silicide layer is positioned on the top of the first source-drain doped layer and on the surface of the side wall vertical to the extension direction of the grid electrode; and the second metal silicide layer is positioned on the surface of the first metal silicide layer and the surface of the side wall of the second source drain doping layer, which is vertical to the extending direction of the grid electrode. .
Optionally, the thickness of the first metal silicide layer is
Figure BDA0001608204000000031
Optionally, the thickness of the second metal silicide layer is
Figure BDA0001608204000000032
Optionally, the thickness of the second source-drain doped layer is
Figure BDA0001608204000000033
Optionally, the thickness of the first source-drain doped layer covered by the second silicide layer is as follows
Figure BDA0001608204000000034
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the technical scheme of the forming method of the semiconductor structure, the sacrificial layer is formed on the surface of the isolation layer, covers the side wall of the first source-drain doping layer, which is vertical to the extending direction of the grid electrode, and exposes the top of the second source-drain doping layer and the side wall, which is vertical to the extending direction of the grid electrode; forming a first metal silicide layer on the top and the side wall surface of the second source drain doping layer exposed out of the sacrificial layer; after the first silicide metal layer is formed, etching the sacrificial layer to expose the surface of the side wall of the first source drain doping layer; and forming a second metal silicide layer on the surface of the first metal silicide layer and the surface of the exposed side wall of the first source-drain doped layer. The first metal silicide layer and the second metal silicide layer form a metal silicide layer. And subsequently forming a conductive plug covering the surface of the second metal silicide layer, wherein the thickness of the metal silicide layer influences the contact resistance between the conductive plug and the surface of the source drain doping layer. The first silicide layer covers the top and the side wall surface of the second source-drain doped layer, and the second silicide layer covers the surface of the first silicide layer, so that the thickness of the silicide layer on the top and the side wall of the second source-drain doped layer is large, and the reduction of the contact resistance between the surface of the source-drain doped layer and the conductive plug is facilitated. On the other hand, the side wall of the first source-drain doped layer is only provided with the second silicide layer, so that the thickness of the silicide layer on the side wall of the first source-drain doped layer is small; and because the first source-drain doping layer covers the bottom of the groove, the thickness of the silicide layer on the side wall of the first source-drain doping layer is small, which is beneficial to inhibiting metal ions in the silicide layer material on the side wall of the first source-drain doping layer from diffusing to the substrate through the surface of the fin part exposed at the bottom of the groove, thereby reducing leakage current and improving the electrical property of the semiconductor structure.
In an alternative, the first metal silicide layer has a thickness of
Figure BDA0001608204000000041
The thickness of the first silicide layer is proper, so that on one hand, the contact resistance between the top and the side wall of the second source-drain doped layer and a subsequently formed conductive plug is reduced, and further the contact resistance between the surface of the source-drain doped layer and the conductive plug can be reduced; on the other hand, the thickness of the second metal silicide layer is made appropriate; the first source-drain doping layer covers the bottom of the groove, and the surface of the side wall of the first source-drain doping layer is only covered with the second silicide layer, so that the thickness of the second silicide layer is proper, and the metal ions in the material of the second silicide layer on the side wall of the first source-drain doping layer are prevented from being diffused to the substrate through the surface of the fin part exposed from the bottom of the groove; in addition, the distance between the second metal silicide layers on the opposite side walls of the adjacent second source-drain doped layers is proper, so that the process window for forming the conductive plug subsequently is favorably enlarged, and the filling quality of the conductive plug is favorably improved.
In an alternative, the second metal silicide layer has a thickness of
Figure BDA0001608204000000042
The second silicide layer is proper in thickness, and on one hand, the contact resistance between the side wall of the first source-drain doped layer and a subsequently formed conductive plug is favorably reduced; on the other hand, the first source-drain doping layer covers the bottom of the groove, and the side wall of the first source-drain doping layer is only provided with the second silicide layer, so that the thickness of the second silicide layer is proper, and metal ions in the second silicide layer material on the side wall of the first source-drain doping layer are prevented from diffusing to the substrate through the surface of the fin part exposed from the bottom of the groove.
In an alternative, before the sacrificial layer is formed, the thickness of the second source-drain doped layer is equal to
Figure BDA0001608204000000043
After the sacrificial layer is formed, forming a first metal silicide layer on the top and the side wall surface of the second source drain doping layer; after the sacrificial layer is etched, forming a second metal silicide layer on the surface of the first metal silicide layer and the surface of the exposed side wall of the first source drain doping layer; therefore, the first silicide metal layer and the second silicide metal layer cover the top and the side wall of the second source-drain doped layer together. The thickness of the second source-drain doping layer is proper, so that the thickness of the source-drain doping layer covered by the first silicide metal layer and the second silicide metal layer together is proper, and the contact resistance between the source-drain doping layer and a subsequently formed conductive plug is favorably reduced; on the other hand, the thickness of the first source-drain doping layer is appropriate, so that the distance between the second silicide layer on the side wall of the second source-drain doping layer and the bottom of the groove and the distance between the first silicide layer and the bottom of the groove are ensured, and the diffusion of metal ions in the material of the second silicide layer on the side wall of the second source-drain doping layer and the first silicide layer to the substrate through the surface of the fin part exposed from the bottom of the groove are favorably avoided.
In an alternative scheme, in the process of etching the sacrificial layer, the thickness of the exposed first source-drain doped layer is as follows
Figure BDA0001608204000000051
After the sacrificial layer is etched, forming a second metal silicide layer on the surface of the first metal silicide layer and the surface of the exposed side wall of the first source drain doping layer; therefore, the exposed side wall of the first source-drain doped layer is only covered with the second metal silicide layer. The thickness of the exposed first source-drain doping layer is proper, so that the thickness of the source-drain doping layer covered by the second silicide metal layer is proper, and on one hand, the contact resistance between the source-drain doping layer and a subsequently formed conductive plug is favorably reduced; on the other hand, the distance between the second source-drain doping layer and the bottom of the groove is ensured, and the situation that metal ions in the first silicide layer on the side wall of the second source-drain doping layer and the material of the second silicide layer pass through the bottom of the groove is favorably avoidedThe exposed surface of the fin portion is diffused to the substrate.
Drawings
Fig. 1 to 4 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 5 to 16 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As is known in the art, the performance of the conventional semiconductor structure is still to be improved.
Now, an analysis is performed in combination with a method for forming a semiconductor structure, and fig. 1 to 4 are schematic structural diagrams corresponding to respective steps in the method for forming a semiconductor structure, where the steps of the process for forming a semiconductor structure mainly include:
referring to fig. 1, a substrate 10 and a fin portion 12 protruding from the surface of the substrate 10 are provided, an isolation layer 13 is provided on the surface of the substrate 10, the isolation layer 13 covers part of a sidewall of the fin portion 12, a gate (not shown in the figure) crossing the fin portion 12 is provided on the surface of the isolation layer 13, the gate covers the top and the sidewall of the fin portion 12, a source drain doping layer 30 is provided in the fin portion 12 on both sides of the gate, and a sidewall 21 is provided on a sidewall of the source drain doping layer 30 perpendicular to the extending direction of the gate.
Referring to fig. 2, an etching stop layer 31 is formed on the top of the isolation layer 13, the sidewall of the sidewall 21, and the top surface of the source-drain doping layer 30.
Referring to fig. 3, a dielectric layer 40 covering the surface of the etch stop layer 31 is formed, and the top of the dielectric layer 40 is higher than the top of the etch stop layer 31 located at the top of the source drain doping layer 30.
Referring to fig. 4, forming a groove (not shown in the figure) in the dielectric layer 40, where the groove exposes a portion of the top of the isolation layer 13, the top of the source-drain doping layer 30, and a sidewall perpendicular to the gate extending direction; and forming a metal silicide layer 60 on the top and the side wall surface of the source drain doping layer 30 exposed by the groove.
The semiconductor structure formed by the method has poor electrical properties, and the reason for analyzing the poor electrical properties is as follows:
and forming a conductive plug filled in the groove, wherein the contact resistance between the conductive plug and the surface of the source-drain doping layer 30 is related to the thickness of the silicide layer 60, and the larger the thickness of the silicide layer 60 is, the smaller the contact resistance between the conductive plug and the source-drain doping layer 30 is, so that the thickness of the silicide layer 60 is large for reducing the contact resistance between the conductive plug and the source-drain doping layer 30. However, the silicide layer 60 material has metal ions, and when the thickness of the silicide layer 60 is large, the metal ions in the silicide layer 60 material near the bottom of the source-drain doping layer 30 are easily diffused to the substrate 10 through the fin portion 12 contacting with the bottom of the source-drain doping layer 30, which results in leakage current in the substrate 10, and thus the electrical performance of the formed semiconductor structure is poor.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: forming a sacrificial layer on the surface of the isolation layer, wherein the sacrificial layer covers the side wall of the first source-drain doping layer, which is vertical to the extending direction of the grid electrode, and exposes the top of the second source-drain doping layer and the side wall, which is vertical to the extending direction of the grid electrode; forming a first metal silicide layer on the top and the side wall surface of the second source drain doping layer exposed out of the sacrificial layer; after the first silicide metal layer is formed, etching the sacrificial layer to expose the surface of the side wall of the first source drain doping layer; and forming a second metal silicide layer on the surface of the first metal silicide layer and the surface of the exposed side wall of the first source-drain doped layer.
In the technical scheme of the semiconductor structure forming method provided by the invention, the first metal silicide layer and the second metal silicide layer form a metal silicide layer. On one hand, the second silicide metal layer covers the surface of the first silicide metal layer, and the first silicide metal layer covers the top and the side wall surface of the second source-drain doping layer, so that the thickness of the silicide metal layer on the top and the side wall of the second source-drain doping layer is large, and the reduction of the contact resistance between the source-drain doping layer and a subsequently formed conductive plug is facilitated. On the other hand, the side wall of the first source-drain doping layer is only covered with a second silicide layer, so that the thickness of the silicide layer on the side wall of the first source-drain doping layer is small; and because the first source-drain doping layer covers the bottom of the groove, the thickness of the silicide layer on the side wall of the first source-drain doping layer is small, so that metal ions in the silicide layer material on the side wall of the first source-drain doping layer are favorably inhibited from being diffused to the substrate through the fin part exposed at the bottom of the groove, the leakage current can be reduced, and the electrical property of the semiconductor structure can be improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 16 are schematic structural diagrams illustrating a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 5, a substrate 100 and a fin 120 protruding from a surface of the substrate 100 are provided, the surface of the substrate 100 has an isolation layer 130, the isolation layer 130 covers a portion of a sidewall of the fin 120, the surface of the isolation layer 130 has a gate 140 crossing the fin 120, and the gate 140 covers a top and a sidewall of the fin 120.
Fig. 5 shows a schematic cross-sectional view of the gate 140 in a plane perpendicular to the extension direction of the gate 140.
The substrate 100 is made of silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide, and the substrate 100 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; in this embodiment, the substrate 100 is a silicon substrate.
In this embodiment, the fin 120 is made of the same material as the substrate 100, and is also made of silicon. In other embodiments, the material of the fin portion may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
The process method for forming the substrate 100 and the fin 120 includes: providing an initial substrate (not shown); forming a patterned fin mask layer (not shown) on the surface of the initial substrate; and etching the initial substrate by taking the fin part mask layer as a mask, wherein the etched initial substrate is taken as the substrate 100, and the protrusion on the surface of the substrate 100 is taken as the fin part 120.
The isolation layer 130 is made of silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the isolation layer 130 is made of silicon oxynitride.
The gate 140 is made of polysilicon or poly-germanium; in addition, the gate electrode 140 may be made of a metal material, such as Cu, W, Ag, or Al. In this embodiment, the gate 140 is made of polysilicon.
A gate dielectric layer (not shown) is disposed between the gate 140 and the fin 120. The material of the gate dielectric layer is silicon oxide or germanium oxide; in addition, the gate dielectric layer material can also be a high-k dielectric material, such as HfO2HfSiO, HfSiON, HfTaO or ZrO2。
In this embodiment, in order to protect the top of the gate 140 and prevent the top of the gate 140 from being damaged by the subsequent process steps, the top of the gate 140 is covered with the hard mask layer 150.
In addition, the surface of the side wall of the gate 140 has an offset sidewall 160, and the offset sidewall 160 also covers the surface of the side wall of the hard mask layer 150.
And forming source and drain doped layers in the fin portion 120 on two sides of the gate 140. The following describes the formation process of the source-drain doping layer in detail with reference to fig. 6 to 9.
Referring to fig. 6, a sidewall film 200 covering the top and sidewall surfaces of the fins 120 on both sides of the gate 140 (see fig. 5) is formed on the top of the isolation layer 130, and the sidewall surfaces of the fins 120 covered by the sidewall film 200 are perpendicular to the extending direction of the gate 140.
Fig. 6 shows a cross-sectional view of the fin 120 on both sides of the gate 140 (see fig. 5) in a plane perpendicular to the extending direction of the fin 120.
The material of the sidewall film 200 is silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride. In this embodiment, the sidewall film 200 is made of silicon nitride.
Referring to fig. 7, the sidewall film 200 (see fig. 6) on the top of the isolation layer 130 and the top of the fin 120 on both sides of the gate 140 is removed to form a sidewall 210.
The sidewalls 210 cover sidewall surfaces of the fins 120 on two sides of the gate 140 (see fig. 5) perpendicular to the extending direction of the gate 140.
And subsequently, the fin parts 120 on two sides of the grid 140 are etched to form a groove, and a source-drain doping layer filled in the groove is formed. The sidewall 210 serves to standardize the growth of the source-drain doped layer and improve the formation quality of the source-drain doped layer.
Referring to fig. 8, the fin portions 120 on two sides of the gate 140 are etched, and the tops of the etched fin portions 120 are lower than the tops of the sidewalls 210, and form a trench 220 with the sidewalls of the sidewalls 210.
The trench 220 provides a spatial location for the subsequent formation of source and drain doped layers. The bottom of the trench 220 exposes the top surface of the etched fin 120. In this embodiment, the bottom of the trench 220 is lower than the top of the isolation layer 130. In other embodiments, the trench bottom is higher than or flush with the isolation layer top.
Referring to fig. 9, a source-drain doped layer 300 is formed to fill the trench 220 (refer to fig. 8).
The source-drain doping layer 300 includes a first source-drain doping layer 301 covering the bottom of the trench 220 and a second source-drain doping layer 302 located on the top of the first source-drain doping layer 301.
In this embodiment, the top of the second source-drain doping layer 302 is flush with the top of the sidewall 210. In other embodiments, the top of the second source-drain doping layer may also be higher or lower than the top of the sidewall.
And forming a first metal silicide layer on the top and the side wall surface of the second source-drain doping layer 302, wherein the second metal silicide layer formed subsequently covers the surface of the first metal silicide layer, so that the second metal silicide layer and the first metal silicide layer jointly cover the top and the side wall surface of the second source-drain doping layer 302, and the contact resistance between the source-drain doping layer 300 and a conductive plug formed subsequently is reduced. If the thickness of the second source-drain doping layer 302 is too small, the thickness of the source-drain doping layer 300 covered by the second silicide layer and the first silicide layer is too small, and the contact resistance between the source-drain doping layer 300 and the conductive plug is too large. If the thickness of the second source-drain doping layer 302 is too large, the thickness of the first source-drain doping layer 301 is too small, so that the second metal silicide layer on the sidewall of the second source-drain doping layer 302And the distance between the first metal silicide layer and the bottom of the trench 220 (refer to fig. 8) is too small, so that the metal ions in the second metal silicide layer on the sidewall of the second source-drain doping layer 302 and the material of the first metal silicide layer are easily diffused to the substrate 100 through the surface of the fin 120 exposed at the bottom of the trench 220. In this embodiment, the thickness of the second source-drain doped layer 302 is
Figure BDA0001608204000000091
If the thickness of the first source-drain doping layer 301 is too small, the distance between the second silicide layer and the bottom of the trench 220 (refer to fig. 8) on the sidewall of the second source-drain doping layer 302 and the first silicide layer is too small, so that the metal ions in the material of the second silicide layer and the first silicide layer on the sidewall of the second source-drain doping layer 302 are easily diffused to the substrate 100 through the surface of the fin 120 exposed at the bottom of the trench 220. If the thickness of the first source-drain doping layer 301 is too large, the thickness of the second source-drain doping layer 302 is too small, so that the thickness of the source-drain doping layer 300 covered by the second silicide layer and the first silicide layer together is too small, and the contact resistance between the source-drain doping layer 300 and the conductive plug is too large. In this embodiment, the thickness of the first source-drain doped layer 301 is
Figure BDA0001608204000000101
In this embodiment, the bottom of the trench 220 (refer to fig. 8) is lower than the top of the isolation layer 130, so that the bottom of the first source-drain doping layer 301 is lower than the top of the isolation layer 130, and the isolation layer 130 exposes a part of the sidewall of the first source-drain doping layer 301.
The sidewall surface of the first source drain doped layer 301 exposed by the isolation layer 130 is subsequently covered with only the second metal silicide layer. If the thickness of the first source-drain doping layer 301 exposed by the isolation layer 130 is too large, the thickness of the source-drain doping layer 300 covered by the second silicide layer is too large, so that the contact resistance between the source-drain doping layer 300 and a subsequently formed conductive plug is too large. If the thickness of the first source/drain doped layer 301 exposed by the isolation layer 130 is too small, the second silicon on the sidewall of the second source/drain doped layer 302 is formedThe distance between the metal silicide layer and the first metal silicide layer and the bottom of the trench 220 (refer to fig. 8) is too small, so that metal ions in the material of the second metal silicide layer and the first metal silicide layer on the sidewalls of the second source-drain doped layer 302 are easily diffused to the substrate 100 through the surface of the fin 120 exposed at the bottom of the trench 220. In this embodiment, the thickness of the first source-drain doped layer 301 exposed by the isolation layer 130 is as follows
Figure BDA0001608204000000102
The material of the first source-drain doped layer 301 is the same as that of the second source-drain doped layer 302. In this embodiment, the material of the first source-drain doping layer 301 and the material of the second source-drain doping layer 302 are both silicon; in other embodiments, the first source-drain doping layer material and the second source-drain doping layer material may also be silicon germanium.
The material of the first source-drain doping layer 301 is doped with N-type ions or P-type ions; the second source-drain doping layer 302 is doped with N-type ions or P-type ions, and the type of the doped ions in the second source-drain doping layer 302 is the same as the type of the doped ions in the first source-drain doping layer 301. In this embodiment, the materials of the first source-drain doping layer 301 and the second source-drain doping layer 302 are both doped with P-type ions, specifically, the P-type ions are boron ions.
The first source-drain doping layer 301 and the second source-drain doping layer 302 are formed in the same process step. In this embodiment, the first source-drain doping layer 301 and the second source-drain doping layer 302 are formed by a selective epitaxial growth process.
In another embodiment, the bottom of the trench is flush with the top of the isolation layer, so that the bottom of the first source/drain doped layer is flush with the top of the isolation layer.
In another embodiment, the bottom of the trench is higher than the top of the isolation layer, so that the bottom of the first source drain doped layer is higher than the top of the isolation layer.
Referring to fig. 10, an etch stop layer 310 is formed on the isolation layer 130 to cover the top of the second source-drain doping layer 302, the sidewall of the sidewall 210, and the top.
And forming a sacrificial film covering the surface of the etching stop layer 310, and etching a part of the sacrificial film to expose the top and the side wall of the second source-drain doping layer 302. The etching stop layer 310 is used to provide an etching stop position to prevent the etching process from damaging the top and sidewall surfaces of the second source-drain doping layer 302.
The material of the etching stop layer 310 is silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride. In this embodiment, the material of the etch stop layer 310 is silicon nitride.
And forming a sacrificial layer on the surface of the isolation layer 130, wherein the sacrificial layer covers the sidewall of the first source-drain doping layer perpendicular to the extending direction of the gate, and exposes the top of the second source-drain doping layer and the sidewall perpendicular to the extending direction of the gate. The process of forming the sacrificial layer will be described in detail with reference to fig. 11 and 12.
Referring to fig. 11, a sacrificial film 410 covering the sidewalls of the first source-drain doping layer 301, the top of the second source-drain doping layer 302, and the sidewalls is formed on the isolation layer 130, and the top of the sacrificial film 410 is higher than the top of the second source-drain doping layer 302.
In this embodiment, the sacrificial film 410 covers the surface of the etching stop layer 310, and the top of the sacrificial film 410 is higher than the top of the etching stop layer 310 located at the top of the second source-drain doping layer 302.
A portion of the thickness of the sacrificial film 410 is subsequently removed to form a sacrificial layer, and the sacrificial layer is etched prior to the subsequent formation of the second metal silicide layer. The choice of the material of the sacrificial film 410 is related to whether the sacrificial layer is removed to the full thickness in the subsequent etching process of the sacrificial layer.
If the sacrificial layer is removed to the full thickness subsequently, the material of the sacrificial film 410 is amorphous silicon, amorphous carbon, anti-reflective coating material, organic coating material, silicon oxide, silicon nitride, silicon oxycarbonitride, or silicon oxynitride. In this embodiment, the sacrificial layer is removed to the full thickness, and the sacrificial film 410 is made of silicon oxide.
In other embodiments, a portion of the thickness of the sacrificial layer is subsequently removed. The sacrificial film is made of silicon oxide, silicon nitride, carbon nitrogen silicon oxide or silicon oxynitride.
In this embodiment, the method further includes: a dielectric layer 400 is formed on the surface of the isolation layer 130, and the dielectric layer 400 covers the surface of the sidewall of the sacrificial film 410. In other embodiments, after the etching stop layer is formed, only the sacrificial film may be formed on the surface of the isolation layer.
The dielectric layer 400 is made of silicon oxide, silicon nitride, silicon oxycarbonitride or silicon oxynitride. In this embodiment, the dielectric layer 400 is made of silicon oxide.
In this embodiment, the material of the dielectric layer 400 is the same as that of the sacrificial film 410, and the sacrificial film 410 and the dielectric layer 400 are formed in the same process.
In other embodiments, the material of the dielectric layer and the material of the sacrificial film may also be different.
Referring to fig. 12, a portion of the thickness of the sacrificial film 410 (refer to fig. 11) is removed, and the top of the sacrificial film 410 is left to be flush with the top of the first source-drain doping layer 301, so as to form the sacrificial layer 420.
In this embodiment, before removing a part of the thickness of the sacrificial film 410, the method further includes: forming a capping layer (not shown) on top of the dielectric layer 400; the sacrificial film 410 is etched using the capping layer as a mask. After the sacrificial layer 420 is formed, the capping layer is removed.
The top of the sacrificial layer 420 is lower than the top of the dielectric layer 400. The top of the sacrificial layer 420 and the sidewall of the dielectric layer 400 enclose a first opening 500.
In this embodiment, the process of removing a portion of the thickness of the sacrificial film 410 further includes: removing the etching stop layer 310 on the top and the side wall of the second source-drain doping layer 302; removing the side wall 210 on the surface of the side wall of the second source-drain doping layer 302; the top of the etch stop layer 310 and the top of the sidewall spacers 210 are left flush with the top of the sacrificial layer 420.
And forming silicon with a first thickness on the top and the side wall surface of the source-drain doping layer 300 exposed from the sacrificial layer 420And the metal layer is gasified, and a second metal silicide layer covering the surface of the first metal silicide layer is formed subsequently. If the thickness of the source-drain doping layer 300 exposed by the sacrificial layer 420 is too small, the thickness of the source-drain doping layer 300 covered by the second silicide layer and the first silicide layer formed subsequently is too small, so that the contact resistance between the source-drain doping layer 300 and the conductive plug formed subsequently is large. If the thickness of the source-drain doping layer 300 exposed by the sacrificial layer 420 is too large, which results in a too small distance between the first silicide layer and the bottom of the trench 220, the probability that metal ions in the first silicide layer and the second silicide layer covering the first silicide layer will diffuse to the substrate 100 through the surface of the fin 120 exposed at the bottom of the trench 220 (refer to fig. 8) is high. In this embodiment, the thickness of the source-drain doping layer 300 exposed from the sacrificial layer 420 is equal to the thickness of the second source-drain doping layer 302, which is
Figure BDA0001608204000000131
Referring to fig. 13, a first metal silicide layer 600 is formed on the top and sidewall surfaces of the source-drain doped layer 300 exposed by the sacrificial layer 420.
The process method for forming the first metal silicide layer 600 includes: forming a first metal film (not shown) covering the top and sidewall surfaces of the exposed second source-drain doping layer 302; the first metal film is annealed to convert the first metal film into a first metal silicide layer 600.
The first metal film material is Ti, Ni or Co. In this embodiment, the first metal film material is Ti.
In this embodiment, the first metal film is annealed by a laser annealing process. The annealing temperature is 850-1000 ℃. And subsequently, etching the sacrificial layer 420 to form a second silicide layer covering the first silicide layer 600 and the exposed sidewall of the first source-drain doping layer 301, wherein the second silicide layer and the first silicide layer 600 form a silicide layer. If the thickness of the first silicide layer 600 is too large, the distance between the second silicide layers on the opposite sidewalls of the adjacent second source/drain doping layers 302 is too small, resulting in the subsequent processesThe process window for forming the conductive plug is small, so that the filling quality of the conductive plug is poor. If the thickness of the first silicide layer 600 is too small, the thickness of the second silicide layer is too large, which results in too large thickness of the silicide layer on the sidewall of the first source-drain doping layer 301, and since the first source-drain doping layer 301 covers the bottom of the trench 220 (refer to fig. 8), the probability that metal ions in the silicide layer material on the sidewall of the first source-drain doping layer 301 diffuse to the substrate 100 through the surface of the fin 120 exposed from the bottom of the trench 220 is high. In this embodiment, the thickness of the first silicide layer 600 is
Figure BDA0001608204000000132
Referring to fig. 14, the sacrificial layer 420 (refer to fig. 13) is etched to expose the sidewall surface of the first source-drain doping layer 301.
In the process of etching the sacrificial layer 420, the sidewall surface of the first source drain doping layer 301 higher than the top of the isolation layer 130 is completely exposed.
In this embodiment, the top of the isolation layer 130 is higher than the bottom of the first source-drain doping layer 301; in the process of etching the sacrificial layer 420, the sacrificial layer 420 is removed to the full thickness.
In this embodiment, the sacrificial layer 420 is etched by a dry etching process. The technological parameters of the dry etching process comprise: the process gas comprises CH4And CHF3Said CH4The gas flow rate of (1) is 8sccm to 1000sccm, and the CHF is3The gas flow of the gas is 30 sccm-2000 sccm, the radio frequency power is 100W-1300W, the direct current self-bias voltage is 80V-1000V, the process time is 4 s-500 s, and the chamber pressure is 10 mTorr-20000 mTorr.
The sacrificial layer 420 is etched, and a second opening (not shown in the figure) is formed at the bottom of the first opening 500 (refer to fig. 12), where the second opening exposes the sidewall of the first source-drain doping layer 301.
In another embodiment, the bottom of the first source drain doped layer is flush with the top of the isolation layer; and in the process of etching the sacrificial layer, removing the sacrificial layer with the whole thickness.
In another other embodiment, the bottom of the first source drain doping layer is higher than the top of the isolation layer; and in the process of etching the sacrificial layer, removing part of the sacrificial layer, wherein the top of the rest sacrificial layer is flush with the bottom of the first source-drain doping layer.
The top of the residual sacrificial layer is flush with the bottom of the first source-drain doping layer, so that the residual sacrificial layer covers the fin side wall between the isolation layer and the first source-drain doping layer, a subsequently formed second metal silicide layer is prevented from covering the fin side wall between the isolation layer and the first source-drain doping layer, and metal ions in the material of the second metal silicide layer are prevented from diffusing to the substrate through the surface of the fin side wall between the isolation layer and the first source-drain doping layer.
Referring to fig. 15, a second metal silicide layer 610 is formed on the surface of the first metal silicide layer 600 and the exposed sidewall surface of the first source-drain doping layer 301.
The process method for forming the second metal silicide layer 610 includes: forming a second metal film (not shown in the figure) covering the surface of the first silicide layer 600 and the exposed sidewall surface of the first source drain doping layer 301; the second metal film is annealed to convert the second metal film into a second metal silicide layer 610.
The second metal film material is Ti, Ni or Co. In this embodiment, the second metal film material is Ti.
In this embodiment, the first metal film is annealed by a laser annealing process. The annealing temperature is 850-1000 ℃.
The first silicide layer 600 and the second silicide layer 610 constitute a silicide layer.
The thickness of the silicide layer affects the contact resistance between the source-drain doping layer 300 and the subsequently formed conductive plug. Because the second silicide layer 610 and the first silicide layer 600 cover the top and the sidewall surface of the second source-drain doping layer 302 together, the thickness of the silicide layer on the top and the sidewall of the second source-drain doping layer 302 is large, which is helpful for reducing the contact resistance between the conductive plug and the top and sidewall surface of the second source-drain doping layer 302, and is further beneficial for reducing the contact resistance between the conductive plug and the source-drain doping layer 300.
The first source-drain doping layer 301 covers the bottom of the trench 220 (refer to fig. 8), and the probability that metal ions in the silicide layer material on the sidewall of the first source-drain doping layer 301 diffuse to the substrate 100 is related to the thickness of the silicide layer on the sidewall of the first source-drain doping layer 301. The sidewall of the first source-drain doping layer 301 is only covered with the second silicide layer 610, so that the thickness of the silicide layer on the sidewall of the first source-drain doping layer 301 is small, which is helpful for reducing the probability that metal ions in the silicide layer material on the sidewall of the first source-drain doping layer 301 diffuse to the substrate 100 through the surface of the fin portion 120 exposed at the bottom of the trench 220.
If the ratio of the thickness of the first silicide layer 600 to the thickness of the second silicide layer 610 is too large, and correspondingly, the thickness of the second silicide layer 610 is too small, since the sidewall of the first source-drain doping layer 301 is only covered with the second silicide layer 610, if the thickness of the second silicide layer 610 is too small, the contact resistance between the sidewall of the first source-drain doping layer 301 and a subsequently formed conductive plug is large. If the ratio of the thickness of the first silicide layer 600 to the thickness of the second silicide layer 610 is too small, correspondingly, the thickness of the second silicide layer 610 is too large, so that metal ions in the material of the second silicide layer 610 on the sidewall of the first source-drain doping layer 301 are easily diffused to the substrate 100 through the surface of the fin 120 exposed at the bottom of the trench 220 (refer to fig. 8), and a leakage current exists in the substrate 100 covered by the fin 120. In this embodiment, the ratio of the thickness of the first silicide layer 600 to the thickness of the second silicide layer 610 is 1.2-2.
If the thickness of the second silicide layer 610 is too large, the probability that metal ions in the material of the second silicide layer 610 on the sidewall of the first source-drain doping layer 301 diffuse to the substrate 100 through the surface of the fin 120 exposed at the bottom of the trench 220 (refer to fig. 8) is high. If the thickness of the second silicide layer is too small, the contact resistance between the sidewall of the first source-drain doping layer 301 and the subsequently formed conductive plug is large. In this embodiment, the second silicidation is performedThe metal layer 610 has a thickness of
Figure BDA0001608204000000161
Referring to fig. 16, a conductive plug 700 is formed on the surface of the second silicide layer 610, and the conductive plug 700 fills the first opening 500 (refer to fig. 12) and the second opening.
The conductive plug 700 is made of W, Ag, Al, or Cu. In this embodiment, the material of the conductive plug 700 is W.
In this embodiment, the top of the conductive plug 700 is flush with the top of the dielectric layer 400.
The process of forming the conductive plug 700 includes: forming an initial conductive plug (not shown) on the surface of the second silicide layer 610 to fill the first opening 500 and the second opening, wherein the top of the initial conductive plug is higher than the top of the dielectric layer 400; and carrying out planarization treatment on the initial conductive plug to enable the top of the rest initial conductive plug to be flush with the top of the dielectric layer 400, so as to form the conductive plug 700.
In sum, after the sacrificial layer 420 is etched, a second silicide layer 610 is formed on the surface of the first silicide layer 600 and the exposed surface of the sidewall of the first source drain doping layer 301. The first silicide layer 600 and the second silicide layer 610 form a silicide layer. On the one hand, since the second silicide layer 610 covers the surface of the first silicide layer 600 and the first silicide layer 600 covers the top and the sidewall surface of the second source-drain doping layer 302, the thickness of the silicide layer formed on the top and the sidewall surface of the second source-drain doping layer 302 is large, which is beneficial to reducing the contact resistance between the surface of the second source-drain doping layer 302 and a subsequently formed conductive plug, and is further beneficial to reducing the contact resistance between the source-drain doping layer 300 and the conductive plug.
On the other hand, the first source-drain doping layer 301 covers the bottom of the trench 220, so that the sidewall of the first source-drain doping layer 301 is only covered with the second silicide layer 610, and further, the thickness of the silicide layer on the sidewall of the first source-drain doping layer 301 is small, which is beneficial to reducing the probability that metal ions in the silicide layer material on the sidewall of the first source-drain doping layer 301 diffuse to the substrate 100 through the surface of the fin portion 120 exposed at the bottom of the trench 220, thereby reducing leakage current and improving the electrical performance of the semiconductor structure.
Referring to fig. 16, the present invention also provides a semiconductor structure obtained by the above forming method, the semiconductor structure including: the semiconductor structure comprises a substrate 100 and a fin portion 120 protruding out of the substrate 100, wherein an isolation layer 130 is arranged on the surface of the substrate 100, the isolation layer 130 covers part of the side wall of the fin portion 120, a grid (not shown in the figure) stretching over the fin portion 120 is arranged on the surface of the isolation layer 130, the grid covers the top and the side wall of the fin portion 120, a groove (not shown in the figure) and a source-drain doping layer 300 filling the groove are arranged in the fin portion 120 on two sides of the grid, and the source-drain doping layer 300 comprises a first source-drain doping layer 301 covering the bottom of the groove and a second source-drain doping layer 302 located on the top of the first source-drain doping layer 301; the first silicide layer 600 is positioned on the top of the first source-drain doped layer 301 and on the surface of the side wall vertical to the extension direction of the grid; and the second metal silicide layer 610 is positioned on the surface of the first metal silicide layer 600 and the surface of the sidewall of the second source drain doping layer 302, which is vertical to the extending direction of the gate.
In this embodiment, the method further includes: the conductive plug 700 covers the surface of the second silicide layer 610, and the top of the conductive plug 700 is higher than the top of the second silicide layer 610 on the top of the second source-drain doped layer 302; a dielectric layer 400 on the sidewalls of the conductive plug 700.
In this embodiment, the top of the isolation layer 130 is higher than the bottom of the first source-drain doping layer 301. In other embodiments, the top of the isolation layer is flush with the bottom of the first source drain doping layer.
The first silicide layer 600 and the second silicide layer 610 form a silicide layer.
On the one hand, the thickness of the silicide layer on the surface of the source-drain doped layer 300 affects the contact resistance between the conductive plug 700 and the source-drain doped layer 300. The second silicide layer 610 and the first silicide layer 600 cover the top and the sidewall surface of the second source-drain doping layer 302 together, so that the thickness of the silicide layer on the top and the sidewall of the second source-drain doping layer 302 is large, which is helpful for reducing the contact resistance between the conductive plug 700 and the surface of the source-drain doping layer 300.
On the other hand, the surface of the sidewall of the first source-drain doping layer 301 is only covered with the second silicide layer 610, so that the thickness of the silicide layer on the sidewall of the first source-drain doping layer 301 is small; since the first source-drain doping layer 301 covers the bottom of the trench, the thickness of the silicide layer on the sidewall of the first source-drain doping layer 301 is small, which is helpful for reducing the probability that metal ions in the silicide layer material on the sidewall of the first source-drain doping layer 301 diffuse to the substrate 100 through the surface of the fin portion 120 exposed at the bottom of the trench, thereby reducing the leakage current and improving the electrical performance of the semiconductor structure.
If the thickness of the first silicide layer 600 is too small, correspondingly, the thickness of the second silicide layer 610 is too large, so that the probability that metal ions in the material of the second silicide layer 610 on the sidewall of the first source-drain doping layer 301 diffuse to the substrate 100 through the surface of the fin 120 exposed at the bottom of the trench is high. In this embodiment, the thickness of the first silicide layer 600 is
Figure BDA0001608204000000181
If the thickness of the second silicide layer 610 is too large, metal ions in the material of the second silicide layer 610 on the sidewall of the first source-drain doping layer 301 are likely to diffuse to the substrate 100 through the surface of the fin 120 exposed at the bottom of the trench. If the thickness of the second silicide layer 610 is too small, the contact resistance between the sidewall of the first source-drain doped layer 301 and the conductive plug 700 is large. In this embodiment, the thickness of the second silicide layer 610 is
Figure BDA0001608204000000182
If the thickness of the second source-drain doping layer 302 is too large, correspondingly, the thickness of the first source-drain doping layer 301 is too small, so that the distance between the second silicide layer 610 and the first silicide layer 600 on the sidewall of the second source-drain doping layer 302 and the bottom of the trench is too small, and a first silicide layer is formed on the sidewall of the second source-drain doping layer 302, and the distance between the first silicide layer 600 and the bottom of the trench is too small, so that a first silicide layer is formedThe metal ions in the second metal silicide layer and the first metal silicide layer on the sidewalls of the two source-drain doped layers 302 are easily diffused to the substrate 100 through the surface of the fin 120 exposed at the bottom of the trench. If the thickness of the second source-drain doping layer 302 is too small, the thickness of the source-drain doping layer 300 covered by the second silicide layer 610 and the first silicide layer 600 is too small, and the contact resistance between the source-drain doping layer 300 and the conductive plug 700 is too large. In this embodiment, the thickness of the second source-drain doped layer 302 is
Figure BDA0001608204000000183
If the thickness of the first source-drain doping layer 301 is too small, the distance between the second silicide layer 610 and the first silicide layer 600 on the sidewall of the second source-drain doping layer 302 and the bottom of the trench is too small, so that metal ions in the materials of the second silicide layer 610 and the first silicide layer 600 on the sidewall of the second source-drain doping layer 302 are easily diffused to the substrate 100 through the surface of the fin 120 exposed at the bottom of the trench. If the thickness of the first source-drain doping layer 301 is too large, the thickness of the second source-drain doping layer 302 is too small, so that the thickness of the source-drain doping layer 300 covered by the second silicide layer and the first silicide layer together is too small, and the contact resistance between the source-drain doping layer 300 and the conductive plug 700 is too large. In this embodiment, the thickness of the first source-drain doped layer 301 is
Figure BDA0001608204000000184
If the thickness of the first source-drain doping layer 301 covered by the second silicide layer 610 is too large, the thickness of the source-drain doping layer 300 only covered by the second silicide layer 610 is too large, and the contact resistance between the conductive plug 700 and the surface of the source-drain doping layer 300 is large. If the thickness of the first source-drain doping layer 301 covered by the second silicide layer 610 is too small, the distance between the second silicide layer 610 and the first silicide layer 600 on the sidewall of the second source-drain doping layer 302 and the bottom of the trench is too small, so that metal ions in the material of the second silicide layer and the first silicide layer on the sidewall of the second source-drain doping layer 302 are easily exposed from the bottom of the trenchThe surface of the fin 120 is diffused into the substrate 100. In this embodiment, the thickness of the first source-drain doped layer 301 covered by the second silicide layer 610 is as follows
Figure BDA0001608204000000191
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method for forming a semiconductor structure, comprising:
providing a substrate and a fin part protruding out of the surface of the substrate, wherein the surface of the substrate is provided with an isolation layer, the isolation layer covers part of the side wall of the fin part, the surface of the isolation layer is provided with a grid electrode crossing the fin part, the grid electrode covers the top and the side wall of the fin part, the fin part on two sides of the grid electrode is internally provided with a groove and a source drain doping layer filled with the groove, and the source drain doping layer comprises a first source drain doping layer covering the bottom of the groove and a second source drain doping layer positioned at the top of the first source drain doping layer;
forming a sacrificial layer on the surface of the isolation layer, wherein the sacrificial layer covers the side wall of the first source-drain doping layer, which is vertical to the extending direction of the grid electrode, and exposes the top of the second source-drain doping layer and the side wall, which is vertical to the extending direction of the grid electrode;
forming a first metal silicide layer on the top and the side wall surface of the second source drain doping layer exposed out of the sacrificial layer;
after the first silicide metal layer is formed, etching the sacrificial layer to expose the surface of the side wall of the first source drain doping layer;
and forming a second metal silicide layer on the surface of the first metal silicide layer and the surface of the exposed side wall of the first source-drain doped layer.
2. The method according to claim 1, wherein a ratio of the thickness of the first silicide layer to the thickness of the second silicide layer is 1.2-2.
3. The method of claim 2, wherein the first metal silicide layer is formed to a thickness of
Figure FDA0001608203990000011
4. The method of claim 2, wherein the second metal silicide layer is formed to a thickness of
Figure FDA0001608203990000012
5. The method for forming a semiconductor structure according to claim 1, wherein before the sacrificial layer is formed, the thickness of the second source-drain doped layer is equal to
Figure FDA0001608203990000013
6. The method for forming a semiconductor structure according to claim 1, wherein in the process of etching the sacrificial layer, the thickness of the exposed first source-drain doped layer is equal to
Figure FDA0001608203990000014
7. The method for forming a semiconductor structure according to claim 1, wherein in the process of etching the sacrificial layer, the surface of the sidewall of the first source-drain doped layer higher than the top of the isolation layer is completely exposed.
8. The method for forming a semiconductor structure according to claim 1 or 7, wherein before the sacrificial layer is formed, the top of the isolation layer is higher than the bottom of the first source-drain doping layer or is flush with the bottom of the first source-drain doping layer; and in the process of etching the sacrificial layer, removing the sacrificial layer with the whole thickness.
9. The method for forming a semiconductor structure according to claim 8, wherein a material of the sacrifice layer is amorphous silicon, amorphous carbon, an antireflection coating material, an organic coating material, silicon oxide, silicon nitride, silicon oxycarbonitride, or silicon oxynitride.
10. The method for forming a semiconductor structure according to claim 1 or 7, wherein before the sacrificial layer is formed, the top of the isolation layer is lower than the bottom of the first source-drain doped layer; and in the process of etching the sacrificial layer, removing part of the sacrificial layer, wherein the top of the rest sacrificial layer is flush with the bottom of the first source-drain doping layer.
11. The method for forming a semiconductor structure according to claim 10, wherein a material of the sacrifice layer is silicon oxide, silicon nitride, silicon oxycarbonitride, or silicon oxynitride.
12. The method of forming a semiconductor structure of claim 1, wherein the sacrificial layer is etched using a dry etch process.
13. The method of forming a semiconductor structure of claim 1, wherein the process of forming the sacrificial layer comprises: forming a sacrificial film covering the side wall of the first source-drain doping layer, the top of the second source-drain doping layer and the side wall on the isolation layer, wherein the top of the sacrificial film is higher than the top of the second source-drain doping layer; and removing part of the sacrificial film, and keeping the top of the remaining sacrificial film flush with the top of the first source-drain doping layer to form the sacrificial layer.
14. The method for forming a semiconductor structure according to claim 13, further comprising forming a dielectric layer on a surface of the isolation layer, wherein the dielectric layer covers a sidewall surface of the sacrificial film, and the sacrificial film and the dielectric layer are formed in the same process, and a material of the dielectric layer is the same as a material of the sacrificial film; in the process of removing the sacrificial film with partial thickness, the bottom of the residual sacrificial film is lower than the top of the dielectric layer; the top of the sacrificial layer and the side wall of the dielectric layer form a first opening in a surrounding mode; and after the first silicide metal layer is formed, etching the sacrificial layer, and forming a second opening at the bottom of the first opening, wherein the second opening exposes the side wall of the first source-drain doped layer.
15. The method of forming a semiconductor structure of claim 14, further comprising, after forming the second metal silicide layer: and forming a conductive plug on the surface of the second metal silicide layer, wherein the first opening and the second opening are filled with the conductive plug.
16. A semiconductor structure, comprising:
the semiconductor device comprises a substrate and a fin part protruding out of the substrate, wherein an isolation layer is arranged on the surface of the substrate and covers partial side walls of the fin part, a grid electrode crossing the fin part is arranged on the surface of the isolation layer, the grid electrode covers the top and the side walls of the fin part, a groove and a source drain doping layer filled with the groove are arranged in the fin part on two sides of the grid electrode, and the source drain doping layer comprises a first source drain doping layer covering the bottom of the groove and a second source drain doping layer located on the top of the first source drain doping layer;
the first silicide layer is positioned on the top of the first source-drain doped layer and on the surface of the side wall vertical to the extension direction of the grid electrode;
and the second metal silicide layer is positioned on the surface of the first metal silicide layer and the surface of the side wall of the second source drain doping layer, which is vertical to the extending direction of the grid electrode.
17. The semiconductor structure of claim 16, wherein said first metal silicide layer is of a thickness of
Figure FDA0001608203990000031
18. The semiconductor structure of claim 16, wherein said second metal silicide layer is of a thickness of
Figure FDA0001608203990000032
19. The semiconductor structure of claim 16, wherein the second source drain dopant layer is thick enough to form a channel region
Figure FDA0001608203990000033
20. The semiconductor structure of claim 16, wherein the thickness of the first source drain doped layer covered by the second silicide layer is equal to
Figure FDA0001608203990000034
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