CN108109986A - 一种功率半导体集成式封装用陶瓷模块及其制备方法 - Google Patents

一种功率半导体集成式封装用陶瓷模块及其制备方法 Download PDF

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CN108109986A
CN108109986A CN201711176148.0A CN201711176148A CN108109986A CN 108109986 A CN108109986 A CN 108109986A CN 201711176148 A CN201711176148 A CN 201711176148A CN 108109986 A CN108109986 A CN 108109986A
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layer
ceramic substrate
ceramic
metal box
box dam
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CN108109986B (zh
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吴朝晖
康为
郭晓泉
章军
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Jinhua Xinci Technology Co ltd
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Dongguan National China New Mstar Technology Ltd
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Priority to GB1811180.7A priority patent/GB2565227B/en
Priority to US16/029,649 priority patent/US10461016B2/en
Priority to PCT/CN2018/094940 priority patent/WO2019011198A1/zh
Priority to DE102018116847.0A priority patent/DE102018116847B4/de
Priority to FR1870829A priority patent/FR3069101B1/fr
Priority to KR1020180081120A priority patent/KR102107901B1/ko
Priority to JP2018132801A priority patent/JP6549763B2/ja
Priority to US16/208,572 priority patent/US11011450B2/en
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Abstract

本发明公开一种功率半导体集成式封装用陶瓷模块及其制备方法，陶瓷模块包括陶瓷基板和一体式金属围坝层；该陶瓷基板的下表面设有导电线路层、绝缘层和散热层；该陶瓷基板的上表面设有正极焊盘、负极焊盘和固晶区；且陶瓷基板上设置有垂直导通孔。通过在陶瓷基板上表面设置一体式金属围坝，与固晶区围构成凹形腔室，可实现半导体芯片的气密性封装；通过在陶瓷基板的下表面设置散热层，可把半导体芯片产生的热量快速向外部传导；通过设置导电线路层及垂直导通孔，可在陶瓷基板的下表面实现多芯片的串并联连接。本发明可实现功率半导体的多芯片集成式封装，具有热电分离良好、气密性高、热阻低、结构紧凑等优点，且生产工艺简单，产品一致性高。

Description

一种功率半导体集成式封装用陶瓷模块及其制备方法
技术领域
本发明涉及功率半导体封装领域技术，尤其是指一种功率半导体集成式封装用陶瓷模块及其制备方法。
背景技术
在集成电路、电力电子应用中，用于光电转换、功率变换的半导体功率器件已经广泛应用于诸如大功率发光二极管、激光器、电机控制、风力发电和UPS等各种领域。近年来，为应对电力电子***对空间和重量的要求，功率半导体模块小型化已成为发展趋势。
在功率半导体模块封装过程中，为解决单一芯片功率小、集成度低和功能不够完善的问题，需要把多个高集成度、高性能、高可靠性的芯片通过串并联方式封装在一个模块内，从而实现多芯片的集成式封装。
多芯片集成式封装会导致流经模块的电流密度增加，芯片功耗也会增加，故而需要提高模块的导热性能。此外，随着工作电压的提高，也需要提高模块的绝缘性能，因此，需要选择低电阻率的布线导体材料，低介电常数、高导热率的绝缘材料作为封装载体，陶瓷模块刚好契合了这个发展要求。
在功率半导体封装中，陶瓷模块（或称陶瓷基座）是半导体芯片及其它微电子器件重要的承载基板，主要起形成密封腔室、机械支撑保护、电互连（绝缘）、导热散热、辅助出光等作用。现阶段应用于功率半导体封装的陶瓷模块有HTCC/LTCC及DBC陶瓷基板等。
HTCC又称为高温共烧多层陶瓷, LTCC 又称为低温共烧多层陶瓷，此技术均采用厚膜印刷技术完成线路制作，因此线路表面较为粗糙（Ra约为1～3um），对位不精准；而且多层陶瓷叠压、高温烧结等工艺使得陶瓷模块尺寸不精确，曲翘高；此外，该工艺采用的陶瓷材料配方复杂、导热率低，且需要专用成型模具，制造周期长，成本高。DBC陶瓷基板又称直接健合陶瓷基板，此技术采用高温键合的方式将铜箔烧结在陶瓷上下表面，再依据线路设计，以蚀刻方式制备线路。该工艺使得DBC陶瓷基板无法在其表面获得凹形密封腔室，故而无法实现真空气密封装，且无法制备垂直导通孔以实现上下线路的互连，因此多芯片的串并联布线比较困难。上述问题，已严重制约了这类陶瓷基板在功率半导体封装中的应用。
发明内容
有鉴于此，本发明针对现有技术存在之缺失，其主要目的是提供一种功率半导体集成式封装用陶瓷模块及其制备方法，其能有效解决现有之陶瓷基板尺寸不精准、曲翘高、散热差、无凹形密封腔室及不方便进行多芯片集成的问题。
为实现上述目的，本发明采用如下之技术方案：
一种功率半导体集成式封装用陶瓷模块，包括有陶瓷基板以及一体式金属围坝层；该陶瓷基板的下表面设置有导电线路层、绝缘层和散热层，该绝缘层完全覆盖住导电线路层，该散热层位于非导电线路层的区域上并与导电线路层间隔分开，散热层的厚度不低于导电线路层及绝缘层的总厚度；该陶瓷基板的上表面设置有正极焊盘、负极焊盘和多个固晶区，每一固晶区上均具有连接层和固晶层，该连接层和固晶层彼此间隔分开；且陶瓷基板上设置有垂直导通孔，垂直导通孔电连接于固晶区与导电线路层之间以及导电线路层与正极焊盘、负极焊盘之间；该一体式金属围坝层设置于陶瓷基板的上表面上，一体式金属围坝层环绕于单个或者多个固晶区的周围并与固晶区间隔分开，一体式金属围坝层的厚度大于固晶区的厚度。
作为一种优选方案，所述陶瓷基板为氧化铝陶瓷、氮化铝陶瓷、氮化硅陶瓷或碳化硅陶瓷。
作为一种优选方案，所述导电线路层和散热层均为电镀铜材质，散热层的厚度大于导电线路层的厚度。
作为一种优选方案，所述一体式金属围坝层为电镀铜材质。
作为一种优选方案，所述正极焊盘、负极焊盘位于陶瓷基板上表面周边，且与一体式金属围坝层间隔分开。
作为一种优选方案，所述垂直导通孔采用外部金属填充或者电镀铜填充。
一种功率半导体集成式封装用陶瓷模块的制备方法，包括有以下步骤：
（1）取陶瓷基板，在陶瓷基板对应的位置上开贯穿孔；
（2）对陶瓷基板的上下表面进行金属化；
（3）对上下表面金属化的陶瓷基板进行贴干膜、曝光、显影和电镀，从而形成正极焊盘、负极焊盘、连接层、固晶层、一体式金属围坝底层，导电线路层、散热底层、垂直导通孔；
（4）在陶瓷基板的上下表面再次进行贴干膜、曝光、显影和电镀，使一体式金属围坝底层及散热底层各自被电镀加厚，获得一体式金属围坝层及散热层；
（5）对陶瓷模块进行退膜、蚀刻；
（6）在陶瓷基板的下表面涂上绝缘材质，形成绝缘层。
作为一种优选方案，进一步包括有步骤（7）：在陶瓷模块之各金属层的表面上镀金/银。
一种功率半导体集成式封装用陶瓷模块的制备方法，包括有以下步骤：
（1）取陶瓷基板，在陶瓷基板对应的位置上开贯穿孔；
（2）对陶瓷基板的上下表面进行金属化；
（3）对上下表面金属化的陶瓷基板进行贴干膜、曝光、显影和电镀，从而形成正极焊盘、负极焊盘、连接层、固晶层、一体式金属围坝底层，导电线路层、散热底层、垂直导通孔；
（4）在陶瓷基板的上下表面再次进行贴干膜、曝光、显影和电镀，使一体式金属围坝底层及散热底层各自被电镀加厚，获得一体式金属围坝层及散热层；
（5）在陶瓷基板的上表面再次进行贴干膜、曝光、显影和电镀，使一体式金属围坝层部分区域被电镀加厚，获得限位用台阶面及台阶层；
（6）对陶瓷模块进行退膜、蚀刻；
（7）在陶瓷基板的下表面涂上绝缘材质，形成绝缘层。
作为一种优选方案，进一步包括有步骤（8）：在陶瓷模块之各金属层的表面上镀金/银。
本发明与现有技术相比具有明显的优点和有益效果，具体而言，由上述技术方案可知：
通过在陶瓷基板上表面设置一体式金属围坝，与固晶区围构成凹形腔室，可实现半导体芯片的气密性封装；通过在陶瓷基板的下表面设置散热层，可把半导体芯片产生的热量快速向外部传导，提高散热性能；通过设置导电线路层及垂直导通孔，可在陶瓷基板的下表面实现多芯片的串并联连接。本发明可以实现功率半导体的多芯片集成式封装，具有热电分离良好、气密性高、热阻低、结构紧凑等优点，且生产工艺简单，产品一致性高。
为更清楚地阐述本发明的结构特征和功效，下面结合附图与具体实施例来对本发明进行详细说明。
附图说明
图1是本发明之较佳实施例的立体示意图；
图2是本发明之较佳实施例的仰视图；
图3是本发明之较佳实施例的局部截面图。
附图标识说明：
10、陶瓷基板 20、一体式金属围坝层
21、凹形腔室 201、一体式金属围坝底层
202、台阶面 203、台阶层
31、导电线路层 32、绝缘层
33、散热层 34、正极焊盘
35、负极焊盘 36、垂直导通孔
301、散热底层 40、固晶区
41、连接层 42、固晶层。
具体实施方式
请参照图1至图3所示，其显示出了本发明之较佳实施例的具体结构，包括有陶瓷基板10以及一体式金属围坝层20。
该陶瓷基板10的下表面设置有导电线路层31、绝缘层32和散热层33，该绝缘层32完全覆盖住导电线路层31，该散热层32位于非导电线路层的区域上并与导电线路层31间隔分开，散热层33的厚度不低于导电线路层31及绝缘层32的总厚度；在本实施例中，所述导电线路层31和散热层33均为电镀铜材质，散热层33的厚度大于导电线路层31的厚度，所述绝缘层32为白色或者绿色油墨材质，绝缘层32的厚度小于散热层33的厚度。
该陶瓷基板10的上表面设置有正极焊盘34、负极焊盘35和多个固晶区40，每一固晶区40上均具有连接层41和固晶层42，该连接层41和固晶层42彼此间隔分开；在本实施例中，所述正极焊盘34、负极焊盘35位于陶瓷基板10上表面周边，且与一体式金属围坝层20间隔分开，所述多个固晶区40呈阵列式排布。
且陶瓷基板10设置有垂直导通孔36，垂直导通孔36电连接于固晶区40与导电线路层31之间以及导电线路层31与正极焊盘34、负极焊盘35之间，即该连接层41和固晶层42通过对应的垂直导通孔36而分别与导电线路层31导通连接，前述有正极焊盘34和负极焊盘35通过对应的垂直导通孔36而分别与导电线路层31导通连接，从而形成串并联线路结构。在本实施例中，所述垂直导通孔36采用外部金属填充或者电镀铜填充，并且，所述陶瓷基板10为氧化铝（Al2O3）陶瓷、氮化铝(AlN)陶瓷、氮化硅(Si3N4)陶瓷或者碳化硅(SiC)陶瓷，氧化铝陶瓷价格便宜，氮化铝陶瓷散热效果好，氮化硅陶瓷强度高，碳化硅陶瓷价格适中，散热效果良好，不以为限。
该一体式金属围坝层20设置于陶瓷基板10的上表面上，一体式金属围坝层20环绕于单个或者多个固晶区40的周围并与固晶区40间隔分开，一体式金属围坝层20的厚度大于固晶区40的厚度。在本实施例中，所述一体式金属围坝层20为电镀铜材质。以及，一体式金属围坝层20上具有多个凹形腔室21，该多个凹形腔室21亦呈阵列式排布，前述多个固晶区40位于对应的凹形腔室21中，并且，所述凹形腔室21的周缘下沉形成台阶面202。
本发明还公开了一种功率半导体集成式封装用陶瓷模块的制备方法，包括有以下步骤：
（1）取陶瓷基板10，在陶瓷基板10对应的位置上开贯穿孔。
（2）对陶瓷基板10的上下表面进行金属化。
（3）对上下表面金属化的陶瓷基板10进行贴干膜、曝光、显影和电镀，从而形成正极焊盘34、负极焊盘35、连接层41、固晶层42、一体式金属围坝底层201，导电线路层31、散热底层301、垂直导通孔36。
（4）在陶瓷基板10的上下表面再次进行贴干膜、曝光、显影和电镀，使一体式金属围坝底层201及散热底层301各自被电镀加厚，获得一体式金属围坝层20及散热层33。
（5）对陶瓷模块进行退膜、蚀刻。
（6）在陶瓷基板10的下表面涂上绝缘材质，形成绝缘层32。
进一步包括有步骤（7）：在陶瓷模块之各金属层的表面上镀金/银（图中未示），即对正极焊盘34、负极焊盘35、连接层41、固晶层42、一体式金属围坝层20及散热层33的表面进行镀金/银。
本发明还公开了另一种功率半导体集成式封装用陶瓷模块的制备方法，包括有以下步骤：
（1）取陶瓷基板10，在陶瓷基板10对应的位置上开贯穿孔。
（2）对陶瓷基板10的上下表面进行金属化。
（3）对上下表面金属化的陶瓷基板10进行贴干膜、曝光、显影和电镀，从而形成正极焊盘34、负极焊盘35、连接层41、固晶层42、一体式金属围坝底层201，导电线路层31、散热底层301、垂直导通孔36。
（4）在陶瓷基板10的上下表面再次进行贴干膜、曝光、显影和电镀，使一体式金属围坝底层201及散热底层301各自被电镀加厚，获得一体式金属围坝层20及散热层33。
（5）在陶瓷基板10的上表面再次进行贴干膜、曝光、显影和电镀，使一体式金属围坝层20部分区域被电镀加厚，获得限位用台阶面202及台阶层203。
（6）对陶瓷模块进行退膜、蚀刻。
（7）在陶瓷基板10的下表面涂上绝缘材质，形成绝缘层32。
进一步包括有步骤（8）：在陶瓷模块之各金属层的表面上镀金/银（图中未示），即对正极焊盘34、负极焊盘35、连接层41、固晶层42、一体式金属围坝层20及散热层33的表面进行镀金/银。
本发明的设计重点在于：通过在陶瓷基板上表面设置一体式金属围坝，与固晶区围构成凹形腔室，可实现半导体芯片的气密性封装；通过在陶瓷基板的下表面设置散热层，可把半导体芯片产生的热量快速向外部传导，提高散热性能；通过设置导电线路层及垂直导通孔，可在陶瓷基板的下表面实现多芯片的串并联连接。本发明可以实现功率半导体的多芯片集成式封装，具有热电分离良好、气密性高、热阻低、结构紧凑等优点，且生产工艺简单，产品一致性高。
以上所述，仅是本发明的较佳实施例而已，并非对本发明的技术范围作任何限制，故凡是依据本发明的技术实质对以上实施例所作的任何细微修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (10)

1.一种功率半导体集成式封装用陶瓷模块，其特征在于：包括有陶瓷基板以及一体式金属围坝层；该陶瓷基板的下表面设置有导电线路层、绝缘层和散热层，该绝缘层完全覆盖住导电线路层，该散热层位于非导电线路层的区域上并与导电线路层间隔分开，散热层的厚度不低于导电线路层及绝缘层的总厚度；该陶瓷基板的上表面设置有正极焊盘、负极焊盘和多个固晶区，每一固晶区上均具有连接层和固晶层，该连接层和固晶层彼此间隔分开；且陶瓷基板上设置有垂直导通孔，垂直导通孔电连接于固晶区与导电线路层之间以及导电线路层与正极焊盘、负极焊盘之间；该一体式金属围坝层设置于陶瓷基板的上表面上，一体式金属围坝层环绕于单个或者多个固晶区的周围并与固晶区间隔分开，一体式金属围坝层的厚度大于固晶区的厚度。
2.根据权利要求1所述的一种功率半导体集成式封装用陶瓷模块，其特征在于：所述陶瓷基板为氧化铝陶瓷、氮化铝陶瓷、氮化硅陶瓷或碳化硅陶瓷。
3.根据权利要求1所述的一种功率半导体集成式封装用陶瓷模块，其特征在于：所述导电线路层和散热层均为电镀铜材质，散热层的厚度大于导电线路层的厚度。
4.根据权利要求1所述的一种功率半导体集成式封装用陶瓷模块，其特征在于：所述一体式金属围坝层为电镀铜材质。
5.根据权利要求1所述的一种功率半导体集成式封装用陶瓷模块，其特征在于：所述正极焊盘、负极焊盘位于陶瓷基板上表面周边，且与一体式金属围坝层间隔分开。
6.根据权利要求1所述的一种功率半导体集成式封装用陶瓷模块，其特征在于：所述垂直导通孔采用外部金属填充或者电镀铜填充。
7.一种如权利要求1至6任一项所述的一种功率半导体集成式封装用陶瓷模块的制备方法，其特征在于：包括有以下步骤：
（1）取陶瓷基板，在陶瓷基板对应的位置上开贯穿孔；
（2）对陶瓷基板的上下表面进行金属化；
（3）对上下表面金属化的陶瓷基板进行贴干膜、曝光、显影和电镀，从而形成正极焊盘、负极焊盘、连接层、固晶层、一体式金属围坝底层，导电线路层、散热底层、垂直导通孔；
（4）在陶瓷基板的上下表面再次进行贴干膜、曝光、显影和电镀，使一体式金属围坝底层及散热底层各自被电镀加厚，获得一体式金属围坝层及散热层；
（5）对陶瓷模块进行退膜、蚀刻；
（6）在陶瓷基板的下表面涂上绝缘材质，形成绝缘层。
8.根据权利要求7所述的一种功率半导体集成式封装用陶瓷模块，其特征在于：进一步包括有步骤（7）：在陶瓷模块之各金属层的表面上镀金/银。
9.一种如权利要求1至6任一项所述的一种功率半导体集成式封装用陶瓷模块的制备方法，其特征在于：包括有以下步骤：
（1）取陶瓷基板，在陶瓷基板对应的位置上开贯穿孔；
（2）对陶瓷基板的上下表面进行金属化；
（3）对上下表面金属化的陶瓷基板进行贴干膜、曝光、显影和电镀，从而形成正极焊盘、负极焊盘、连接层、固晶层、一体式金属围坝底层，导电线路层、散热底层、垂直导通孔；
（4）在陶瓷基板的上下表面再次进行贴干膜、曝光、显影和电镀，使一体式金属围坝底层及散热底层各自被电镀加厚，获得一体式金属围坝层及散热层；
（5）在陶瓷基板的上表面再次进行贴干膜、曝光、显影和电镀，使一体式金属围坝层部分区域被电镀加厚，获得限位用台阶面及台阶层；
（6）对陶瓷模块进行退膜、蚀刻；
（7）在陶瓷基板的下表面涂上绝缘材质，形成绝缘层。
10.根据权利要求9所述的一种功率半导体集成式封装用陶瓷模块，其特征在于：进一步包括有步骤（8）：在陶瓷模块之各金属层的表面上镀金/银。
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