CN107993985A - 电子部件搭载用基板、电子装置以及电子模块 - Google Patents

电子部件搭载用基板、电子装置以及电子模块 Download PDF

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Publication number
CN107993985A
CN107993985A CN201710699457.XA CN201710699457A CN107993985A CN 107993985 A CN107993985 A CN 107993985A CN 201710699457 A CN201710699457 A CN 201710699457A CN 107993985 A CN107993985 A CN 107993985A
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China
Prior art keywords
electrode
substrate
part carrying
electro part
electronic unit
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CN107993985B (zh
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村上健策
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
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Abstract

电子部件搭载用基板(1)具有：基板(11)；搭载电极(12)，其将电子部件(2)搭载于基板(11)的主面，以隔着第一缝隙(12a)的方式设置；平面电极(13)，其在俯视下包围搭载电极(12)，以具有第二缝隙(13a)的方式设置；连接电极(14)，其将搭载电极(12)与平面电极(13)连接；以及外部电极(15)，其设置于与主面相对的另一主面，在俯视透视下，连接电极(14)与外部电极(15)重叠，外部电极(15)的外缘以包围连接电极(14)的方式设置。

Description

电子部件搭载用基板、电子装置以及电子模块
技术领域
本发明涉及电子部件搭载用基板、电子装置以及电子模块。
背景技术
以往，电子部件搭载用基板具有：搭载电极，其设置于基板的主面，用于搭载电子部件；外部电极，其设置于基板的另一主面；以及过孔导体，其将搭载电极与外部电极连接。在通过焊料等接合材料将包括电子部件以及电子部件搭载用基板的电子装置接合于例如模块用基板的情况下，外部电极经由焊料等接合材料而接合于模块用基板。
在先技术文献
专利文献
专利文献1：日本特开2014-086630号公报
发明要解决的课题
近年来，正在追求电子装置的高功能化以及小型化。若过孔导体以在俯视透视下与电子部件的搭载部重叠的方式连接于搭载电极，则在电子装置工作时，电子部件所产生的的热量和因电流流过过孔导体而过孔导体产生的热量集中于基板的中央部，担心电子部件搭载用基板的变形所引起的电子部件的剥离、电子部件的破损。
发明内容
用于解决课题的方案
根据本发明的一技术方案，电子部件搭载用基板具有：基板；搭载电极，其将电子部件搭载于该基板的主面，以隔着第一缝隙的方式设置；平面电极，其在俯视下包围所述搭载电极，以具有第二缝隙的方式设置；连接电极，其将所述搭载电极与所述平面电极连接；以及外部电极，其设置于与所述主面相对的另一主面，在俯视透视下，所述连接电极与所述外部电极重叠，所述外部电极的外缘以包围所述连接电极的方式设置。
根据本发明的另一技术方案，电子装置具有上述结构的电子部件搭载用基板和搭载于该电子部件搭载用基板的电子部件。
根据本发明的又一技术方案，电子模块具有上述结构的电子装置和与该电子装置连接的模块用基板。
发明效果
本发明的一技术方案的电子部件搭载用基板具有：基板；搭载电极，其将电子部件搭载于基板的主面，以隔着第一缝隙的方式设置；平面电极，其在俯视下包围搭载电极，以具有第二缝隙的方式设置；连接电极，其将搭载电极与平面电极连接；以及外部电极，其设置于与主面相对的另一主面，在俯视透视下，连接电极与外部电极重叠，外部电极的外缘以包围连接电极的方式设置。根据该结构，在例如平面电极与外部电极经由过孔导体而连接的情况下，抑制过孔导体的热量经由连接电极而向电子部件侧大量传递，与连接电极侧相比容易向外部电极侧传递热量，由此能够抑制电子部件搭载用基板的变形，能够减少电子部件的剥离、电子部件的破损。
本发明的另一技术方案的电子装置通过具有上述结构的电子部件搭载用基板和搭载于电子部件搭载用基板的电子部件，能够提高电可靠性。
本发明的又一技术方案的电子模块通过具有上述结构的电子装置和与电子装置连接的模块用基板，能够形成长期可靠性优异的电子模块。
附图说明
图1的(a)是表示本发明的第一实施方式的电子装置的俯视图，(b)是(a)的仰视图。
图2的(a)是表示图1的电子装置的电子部件搭载用基板的俯视图，(b)是(a)的A部的主要部分放大俯视图。
图3的(a)是图1的(a)所示的电子装置的A-A线处的纵剖视图，(b)是图1的(a)的B-B线处的纵剖视图。
图4是表示在使用了图1中的电子装置的模块用基板上安装的电子模块的纵剖视图。
图5的(a)是表示本发明的第二实施方式的电子装置的俯视图，(b)是(a)的仰视图。
图6是表示图5的电子装置中的电子部件搭载用基板的俯视图。
图7的(a)是图5的(a)所示的电子装置的A-A线处的纵剖视图，(b)是图5的(a)的B-B线处的纵剖视图。
图8的(a)是表示本发明的第三实施方式的电子装置的俯视图，(b)是(a)的仰视图。
图9是表示图8的电子装置中的电子部件搭载用基板的俯视图。
图10的(a)是表示本发明的第四实施方式的电子装置的俯视图，(b)是(a)的仰视图。
图11是图10的(a)所示的电子装置的A-A线处的纵剖视图。
附图标记说明
1····电子部件搭载用基板
11····基板
12····搭载电极
12a···第一缝隙
13····平面电极
13a···第二缝隙
14····连接电极
14a···第三缝隙
15····外部电极
16····过孔导体
2····电子部件
3····连接构件
4····密封件
5····模块用基板
51····连接焊盘
6····接合材料
具体实施方式
参照附图来说明本发明的几个例示的实施方式。
(第一实施方式)
如图1～图4所示的例子那样，本发明的第一实施方式的电子装置包括电子部件搭载用基板1和设置于电子部件搭载用基板1的主面的电子部件2。如图4所示的例子那样，电子装置使用接合材料6而连接于例如构成电子模块的模块用基板5上的连接焊盘51。
本实施方式的电子部件搭载用基板1具有：基板11；搭载电极12，其将电子部件2搭载于基板11的主面，以隔着第一缝隙12a的方式设置；平面电极13，其在俯视下包围搭载电极12，以具有第二缝隙13a的方式设置；连接电极14，其将搭载电极12与平面电极13连接；以及外部电极15，其设置于与主面相对的另一主面。在基板11的内部设置有过孔导体16。在俯视透视下，连接电极14与外部电极15重叠，外部电极15的外缘以包围连接电极14的方式设置。在图1～图3中，电子装置安装于假想的xyz空间中的xy平面。在图1～图3中，上方向是指假想的z轴的正向。需要说明的是，以下的说明中的上下的区别为了方便起见，并不限定实际使用电子部件搭载用基板1等时的上下。
在图1的(a)以及图2所示的例子中，用虚线示出过孔导体16的侧面在俯视透视下与平面电极13重叠的区域。另外，在图1的(b)所示的例子中，用虚线示出连接电极14的缘部以及过孔导体16的侧面在俯视透视下与外部电极15重叠的区域。
基板11具有主面(在图1～图3中为上表面)以及另一主面(在图1～图3中为下表面)。基板11为在俯视下在主面以及另一主面分别具有两组对置的边(四边)的矩形的板状的形状。基板11作为用于支承电子部件2的支承体而发挥功能，电子部件2经由焊料凸点等连接构件3而粘接固定于在基板11的一主面设置的搭载电极12上。
基板11例如可以使用氧化铝质烧结体(氧化铝陶瓷)、氮化铝质烧结体、莫来石质烧结体或玻璃陶瓷烧结体等陶瓷。对于基板11，若例如为氧化铝质烧结体的情况，则向氧化铝(Al2O3)、氧化硅(SiO2)、氧化镁(MgO)、氧化钙(CaO)等原料粉末添加混合适当的有机粘结剂以及溶剂等来制作泥浆物。采用以往周知的刮板法或压延辊法等将该泥浆物成形为片状来制作陶瓷生片。接着，对该陶瓷生片实施适当的冲裁加工，并且根据需要层叠多张陶瓷生片而形成生成形体，以高温(约1600℃)对该生成形体进行烧成而制作由多个绝缘层构成的基板11。
搭载电极12、平面电极13、连接电极14、外部电极15、过孔导体16用于将搭载于搭载电极12的电子部件2与模块用基板5电连接。另外，搭载电极12用于将电子部件搭载用基板1与电子部件2接合。外部电极15用于将电子部件搭载用基板1与模块用基板5接合。
搭载电极12、平面电极13、连接电极14设置于基板11的主面。搭载电极12以隔着第一缝隙12a的方式设置于基板11的主面，作为一对电极而形成。第一缝隙12a的宽度W1设置为0.02mm～0.2mm左右。平面电极13以在俯视下包围搭载电极12的方式设置于基板11的主面。平面电极13以具有第二缝隙13a的方式设置，作为一对电极而形成。第二缝隙13a的宽度W2设置为0.02mm～0.2mm左右。连接电极14设置于搭载电极12与平面电极13之间，以将搭载电极12与平面电极13连接的方式分别设置。将各搭载电极12与平面电极13连接的各连接部14在图1以及2所示的例子中以隔着电子部件2的搭载部的方式对置设置。第一缝隙12a以及第二缝隙13a在图1以及图2所示的例子中设置为直线状。
外部电极15设置于与基板11的主面相对的基板11的另一主面。外部电极15如图1的(b)所示的例子那样在俯视透视下与连接电极14重叠，外部电极15的外缘以包围连接电极14的方式设置。外部电极15以在俯视透视下例如与连接电极14的整个区域重叠的方式设置。另外，外部电极15以在俯视透视下也与搭载电极12的一部分以及平面电极13的一部分重叠的方式配置。
过孔导体16设置于基板11的内部、即基板11的厚度方向。过孔导体16将设置于基板11的主面的平面电极13与设置于基板11的另一主面的外部电极15连接。在图1～图3所示的例子中，由三个过孔导体16将平面电极13与外部电极15连接。
搭载电极12、平面电极13、连接电极14、外部电极15、过孔导体16的材料是以例如钨(W)、钼(Mo)、锰(Mn)、银(Ag)或铜(Cu)等为主要成分的金属粉末化物。搭载电极12、平面电极13、连接电极14、外部电极15通过网版印刷法等印刷手段向例如基板11用的陶瓷生片印刷涂布搭载电极12、平面电极13、连接电极14、外部电极15用的金属化糊剂，并与基板11用的陶瓷生片一起烧成来形成。另外，过孔导体16例如通过如下方式形成：通过基于模具或冲孔进行的冲裁加工或激光加工等加工方法而在基板11用的陶瓷生片形成过孔导体16用的贯通孔，通过网版印刷法等印刷手段而向该贯通孔填充过孔导体16用的金属化糊剂，与基板11用的陶瓷生片一起进行烧成。上述的金属化糊剂通过向上述的金属粉末添加适当的溶剂以及粘结剂并混炼而调整为适度的粘度来制作。需要说明的是，金属化糊剂也可以为了提高与基板11的接合强度而包含玻璃粉末、陶瓷粉末。
在搭载电极12、平面电极13、连接电极14、外部电极15的从基板11露出的表面被覆有镍、金等耐腐蚀性优异的金属镀层。能够减轻搭载电极12、平面电极13、连接电极14、外部电极15腐蚀的情况，并且能够实现搭载电极12与电子部件2的接合、搭载电极12与连接构件3的连接、或模块用基板5与外部电极15的牢固接合。例如，在搭载电极12、平面电极13、连接电极14、外部电极15的从基板11露出的表面上依次被覆厚度1～10μm左右的镍镀层和厚度0.1～3μm左右的金镀层。
另外，镀层并不限定于镍镀层/金镀层，也可以是镍镀层/金镀层/银镀层、或者包含镍镀层/钯镀层/金镀层等的其他金属镀层。
另外，也可以是，在搭载电子部件2的搭载电极12上，在例如上述的镍镀层和金镀层的基底层例如被覆厚度10～80μm左右的铜镀层来作为金属镀层，由此容易使电子部件2的热量经由铜镀层而向电子部件搭载用基板1侧良好地散出。
另外，也可以是，在外部电极15上，在例如上述的镍镀层和金镀层的基底层例如被覆厚度10～80μm左右的铜镀层来作为金属镀层，由此容易使电子部件搭载用基板1的热量经由铜镀层而向模块用基板5侧良好地散出。
可以通过在设置于电子部件搭载用基板1的一主面的搭载电极12上搭载电子部件2来制作电子装置。搭载于电子部件搭载用基板1的电子部件2是IC芯片、LSI芯片等半导体元件、发光元件、水晶振子、压电振子等压电元件以及各种传感器等。例如在电子部件2为倒装芯片型的半导体元件的情况下，半导体元件经由焊料凸点、金凸点或导电性树脂(各向异性导电树脂等)等连接构件3而将半导体元件的电极与搭载电极12电连接以及机械连接，由此搭载于电子部件搭载用基板1。另外，例如在电子部件2为引线接合型的半导体元件的情况下，半导体元件通过低熔点钎料或导电性树脂等接合构件而固定于搭载电子部件2的一方的搭载电极12上之后，经由接合线等连接构件3而将半导体元件的电极与另一方的搭载电极12电连接，由此搭载于电子部件搭载用基板1。另外，在电子部件搭载用基板1上，也可以搭载多个电子部件2，也可以根据需要而搭载电阻元件、电容元件、齐纳二极管等其他电子部件。另外，电子部件2根据需要而被由树脂或玻璃等构成的密封件4、由树脂或玻璃、陶瓷、金属等构成的盖体等密封。
如图4所示的例子那样，本实施方式的电子装置经由焊料等接合材料6而模块用基板5的连接焊盘51连接，成为电子模块。
根据本实施方式的电子部件搭载用基板1，具有：基板11；搭载电极12，其将电子部件2搭载于基板11的主面，以隔着第一缝隙12a的方式设置；平面电极13，其在俯视下包围搭载电极12，以具有第二缝隙13a的方式设置；连接电极14，其将搭载电极12与平面电极13连接；以及外部电极15，其设置于与主面相对的另一主面，在俯视透视下，连接电极14与外部电极15重叠，外部电极15的外缘以包围连接电极14的方式设置，由此例如在将平面电极13与外部电极15经由过孔导体16连接的情况下，抑制过孔导体16的热量经由连接电极14而向电子部件2侧大量传递的情况，与连接电极14侧相比容易向外部电极15侧传递，由此能够抑制电子部件搭载用基板1的变形，能够减少电子部件2的剥离、电子部件2的破损。
另外，当在搭载电极12与平面电极13之间具有第三缝隙14a，第三缝隙14a以隔着连接电极14的方式设置时，能够减小搭载电极12与平面电极13的传热路径，例如在将平面电极13与外部电极15经由过孔导体16而连接的情况下，能够有效抑制过孔导体16的热量经由连接电极14而向电子部件2侧大量传递，能够减少电子部件2的剥离、电子部件2的破损。
如图2所示的例子那样，连接电极14由两个第三缝隙14a夹持。第三缝隙14a的宽度W3与第一缝隙12a以及第二缝隙13a同样，被设为0.02mm～0.2mm左右。
根据本实施方式的电子装置，通过具有上述结构的电子部件搭载用基板1和搭载于电子部件搭载用基板1的电子部件2，能够提高电可靠性。
根据本实施方式的电子模块，具有上述结构的电子装置和与电子装置连接的模块用基板5，因此能够形成长期可靠性优异的电子模块。
本实施方式的电子部件搭载用基板1能够较佳地使用于薄型且高输出的电子装置，能够提高电子部件搭载用基板1的可靠性。例如，在作为电子部件2而搭载发光元件的情况下，能够较佳地用作薄型且高亮度的发光装置用的电子部件搭载用基板1。
(第二实施方式)
接着，参照图5～图7来说明本发明的第二实施方式的电子装置。
在本发明的第二实施方式的电子装置中，与上述的实施方式的电子装置的不同点在于，过孔导体16配置于从假想直线N以及第二缝隙13a离开的位置，其中，假想直线N是将搭载部的中央部与连接电极14连结的直线。
在图5的(a)以及图6所示的例子中，用虚线示出过孔导体16的侧面在俯视透视下与平面电极13重叠的区域。另外，在图5的(b)所示的例子中，用虚线示出连接电极14的缘部以及过孔导体16的侧面在俯视透视下与外部电极15重叠的区域。
搭载部的中央部是指搭载电子部件2的区域的中心。在第二实施方式的电子部件搭载用基板1中，如图5以及图7所示的例子那样，电子部件2搭载于基板11的中央部，因此搭载部的中央部是指基板11的中心。将各搭载电极12与平面电极13连接的各连接部14在图5以及6所示的例子中以隔着电子部件2的搭载部的方式对置设置，假想直线N位于将对置设置的连接部14连结的位置。
根据本发明的第二实施方式的电子部件搭载用基板1，与第一实施方式同样，在例如平面电极13与外部电极15经由过孔导体16而连接的情况下，抑制过孔导体16的热量经由连接电极14而向电子部件2侧大量传递，与连接电极14侧相比容易向外部电极15侧传递热量，由此能够抑制电子部件搭载用基板1的变形，能够减少电子部件2的剥离、电子部件2的破损。
另外，具有将平面电极13与外部电极15连接的过孔导体16，过孔导体16在俯视透视下与平面电极13以及外部电极15重叠，过孔导体16配置于从将搭载电子部件2的搭载部的中央部与连接电极14连结的假想直线N离开的位置，因此更加远离搭载电极12与平面电极13的传热路径即连接电极14，能够有效抑制过孔导体16的热量经由连接电极14而向电子部件2侧大量传递，能够减少电子部件2的剥离、电子部件2的破损。
另外，若多个过孔导体16如图5～图7所示的例子那样隔着电子部件2的搭载部而点对称地配置，即不向基板11的一方的侧面侧偏倚地配置，则能够抑制过孔导体16的热量向基板11的一侧偏倚，能够抑制电子部件搭载用基板1的变形，能够减少电子部件2的剥离、电子部件2的破损。在图5～图7所示的例子中，与第一实施方式的电子部件搭载用基板1同样，就过孔导体16而言，在俯视透视下在基板11的左侧以及右侧分别设置有三个过孔导体16。在第二实施方式的电子部件搭载用基板1中，在基板11的左侧，在比假想直线N靠上侧的位置设置有两个过孔导体16，在比假想直线N靠下侧的位置设置有一个过孔导体16。另外，在基板11的右侧，在比假想直线N靠上侧的位置设置有一个过孔导体16，在比假想直线N靠下侧的位置设置有两个过孔导体16。以在将电子部件搭载用基板1在俯视下四分割时，配置于对角的区域的过孔导体16的数量相同的方式配置过孔导体16。
第二实施方式的电子部件搭载用基板1能够较佳地使用于薄型且高输出的电子装置，能够提高电子部件搭载用基板1的可靠性。例如，在作为电子部件2而搭载发光元件的情况下，能够较佳地用作薄型且高亮度的发光装置用的电子部件搭载用基板1。
第二实施方式的电子部件搭载用基板1可以使用与上述的第一实施方式的电子部件搭载用基板1同样的制造方法来制作。
(第三实施方式)
接着，参照图8以及图9来说明本发明的第三实施方式的电子装置。
在本发明的第三实施方式的电子装置中，与上述的实施方式的电子装置的不同点在于，设置有多个将一个搭载电极12与一个平面电极13连接的连接电极14。在图8所示的例子中，在一个搭载电极12与一个平面电极13之间设置有三个连接电极14。
在图8的(a)以及图9所示的例子中，用虚线示出过孔导体16的侧面在俯视透视下与平面电极13重叠的区域。另外，在图8的(b)所示的例子中，用虚线示出连接电极14的缘部以及过孔导体16的侧面在俯视透视下与外部电极15重叠的区域。
根据本发明的第三实施方式的电子部件搭载用基板1，与第一实施方式同样，抑制过孔导体16的热量经由连接电极14而向电子部件2侧大量传递，与连接电极14侧相比容易向外部电极15侧传递热量，由此能够抑制电子部件搭载用基板1的变形，能够减少电子部件2的剥离、电子部件2的破损。
需要说明的是，若过孔导体16配置于从将搭载电子部件2的搭载部的中央部与各连接电极14连结的假想直线N离开的位置，则更加远离搭载电极12与平面电极13的传热路径即连接电极14，能够有效抑制过孔导体16的热量经由连接电极14而向电子部件2侧大量传递，能够减少电子部件2的剥离、电子部件2的破损。
第三实施方式的电子部件搭载用基板1能够较佳地使用于薄型且高输出的电子装置，能够提高电子部件搭载用基板1的可靠性。例如，在作为电子部件2而搭载发光元件的情况下，能够较佳地用作薄型且高亮度的发光装置用的电子部件搭载用基板1。
第三实施方式的电子部件搭载用基板1可以使用与上述的第一实施方式的电子部件搭载用基板1同样的制造方法来制作。
(第四实施方式)
接着，参照图10以及图11来说明本发明的第四实施方式的电子装置。
在本发明的第四实施方式的电子装置中，与上述的实施方式的电子装置的不同点在于，基板11由多个绝缘层11a形成。基板11在图11所示的例子中由两层的绝缘层11a形成。
在图10的(a)所示的例子中，用虚线示出过孔导体16的侧面在俯视透视下与平面电极13重叠的区域。另外，在图10的(b)所示的例子中，用虚线示出连接电极14的缘部以及过孔导体16的侧面在俯视透视下与外部电极15重叠的区域。
根据本发明的第四实施方式的电子部件搭载用基板1，与第一实施方式同样，抑制过孔导体16的热量经由连接电极14而向电子部件2侧大量传递，与连接电极14侧相比容易向外部电极15侧传递热量，由此能够抑制电子部件搭载用基板1的变形，能够减少电子部件2的剥离、电子部件2的破损。
另外，也可以是，如图10以及图11的例子所示，设置于基板11的主面侧的过孔导体16与设置于基板11的另一主面侧的过孔导体16的位置在俯视下错开。设置于基板11的主面侧的过孔导体16与设置于基板11的另一主面侧的过孔导体16采用与搭载电极12、平面电极13、连接电极14同样的材料或制造方法来制作，通过设置于基板11的内部的布线而电连接。在该情况下，当另一主面侧的过孔导体16位于比主面侧的过孔导体16靠基板11的外周侧、即在俯视透视下远离搭载电极12的区域时，能够抑制热量集中于基板11的中央侧，抑制电子部件搭载用基板1的变形，能够减少电子部件2的剥离、电子部件2的破损。
第四实施方式的电子部件搭载用基板1能够较佳地使用于薄型且高输出的电子装置，能够提高电子部件搭载用基板1的可靠性。例如，在作为电子部件2而搭载发光元件的情况下，能够较佳地用作薄型且高亮度的发光装置用的电子部件搭载用基板1。
第四实施方式的电子部件搭载用基板1可以使用与上述的第一实施方式的实施方式的电子部件搭载用基板1同样的制造方法来制作。
本发明并不限定于上述的实施方式的例子，能够进行各种变更。例如，也可以是在基板11的角部沿着基板11的厚度方向形成有倒角部或者圆弧状的缺口部的电子部件搭载用基板1。
搭载电极12、平面电极13、连接电极14、外部电极15在上述的实施方式中使用共烧法来形成，但也可以是使用以往周知的后烧法或者薄膜法等而形成的金属层。在该情况下，能够形成位置精度优异的电子部件搭载用基板1以及电子装置。
另外，在第一～第四实施方式的电子部件搭载用基板1中，在俯视下，通过三个过孔导体16而将一个搭载电极12与一个外部电极15连接，但也可以通过四个以上的过孔导体16来将一个搭载电极12与一个外部电极15连接。
另外，在上述的例子中，基板11通过一层或两层的绝缘层而形成，但也可以由三层以上的绝缘层形成。
另外，也可以组合第一～第四实施方式的电子部件搭载用基板1的形态。例如，也可以在第四实施方式的电子部件搭载用基板1中，在一个搭载电极12与一个平面电极13之间设置多个连接电极14。

Claims (6)

1.一种电子部件搭载用基板，其特征在于，具有：
基板；
搭载电极，其将电子部件搭载于该基板的主面，以隔着第一缝隙的方式设置；
平面电极，其在俯视下包围所述搭载电极，以具有第二缝隙的方式设置；
连接电极，其将所述搭载电极与所述平面电极连接；以及
外部电极，其设置于与所述主面相对的另一主面，
在俯视透视下，所述连接电极与所述外部电极重叠，所述外部电极的外缘以包围所述连接电极的方式设置。
2.根据权利要求1所述的电子部件搭载用基板，其特征在于，
在所述搭载电极与所述平面电极之间具有第三缝隙，
该第三缝隙以隔着所述连接电极的方式设置。
3.根据权利要求1或2所述的电子部件搭载用基板，其特征在于，
所述电子部件搭载用基板具有将所述平面电极与所述外部电极连接的过孔导体，
该过孔导体在俯视透视下与所述平面电极以及所述外部电极重叠，并且，该过孔导体配置于从假想直线离开的位置，所述假想直线是将搭载电子部件的搭载部的中央部与所述连接电极连结的直线。
4.根据权利要求3所述的电子部件搭载用基板，其特征在于，
所述过孔导体隔着所述搭载部而点对称地配置。
5.一种电子装置，其特征在于，具有：
权利要求1至4中任一项所述的电子部件搭载用基板；以及
搭载于该电子部件搭载用基板的电子部件。
6.一种电子模块，其特征在于，具有：
权利要求5所述的电子装置；以及
与该电子装置连接的模块用基板。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113474884A (zh) * 2019-02-27 2021-10-01 京瓷株式会社 布线基板、电子装置以及电子模块

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3637963B1 (en) * 2018-10-12 2024-02-07 AT&S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier structures connected by cooperating magnet structures
JP7136926B2 (ja) * 2018-12-26 2022-09-13 京セラ株式会社 配線基板、電子装置および電子モジュール
CN111987084B (zh) * 2019-05-24 2022-07-26 方略电子股份有限公司 电子装置及其制造方法
JP7449768B2 (ja) * 2020-04-23 2024-03-14 新光電気工業株式会社 セラミックス基板及びその製造方法、静電チャック、基板固定装置、半導体装置用パッケージ

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206601A (ja) * 1992-01-28 1993-08-13 Fujitsu Isotec Ltd プリント基板及びそのアース方法
US5453580A (en) * 1993-11-23 1995-09-26 E-Systems, Inc. Vibration sensitive isolation for printed circuit boards
BRPI0719890A2 (pt) * 2006-10-10 2014-05-06 Tir Technology Lp Painel de circuito impresso e métodos de preparar e de montar um painel de circuito impresso
JP2014086630A (ja) * 2012-10-25 2014-05-12 Kyocera Corp 発光素子搭載用部品および発光装置
JP2015122487A (ja) * 2013-11-19 2015-07-02 デクセリアルズ株式会社 発光装置、発光装置製造方法
JP6400928B2 (ja) * 2014-03-26 2018-10-03 京セラ株式会社 配線基板および電子装置
JP6728676B2 (ja) * 2015-12-26 2020-07-22 日亜化学工業株式会社 発光装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113474884A (zh) * 2019-02-27 2021-10-01 京瓷株式会社 布线基板、电子装置以及电子模块

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