CN107993618A - The level generation circuit of display device - Google Patents
The level generation circuit of display device Download PDFInfo
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- CN107993618A CN107993618A CN201711059773.7A CN201711059773A CN107993618A CN 107993618 A CN107993618 A CN 107993618A CN 201711059773 A CN201711059773 A CN 201711059773A CN 107993618 A CN107993618 A CN 107993618A
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- 238000001914 filtration Methods 0.000 claims description 21
- 230000005611 electricity Effects 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 9
- 239000003381 stabilizer Substances 0.000 claims description 9
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 230000009467 reduction Effects 0.000 claims description 2
- 230000000087 stabilizing effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 101100102598 Mus musculus Vgll2 gene Proteins 0.000 description 9
- 101100102583 Schizosaccharomyces pombe (strain 972 / ATCC 24843) vgl1 gene Proteins 0.000 description 9
- 102100023478 Transcription cofactor vestigial-like protein 1 Human genes 0.000 description 9
- 102100023477 Transcription cofactor vestigial-like protein 2 Human genes 0.000 description 9
- 230000008569 process Effects 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 230000009993 protective function Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Dc-Dc Converters (AREA)
Abstract
This application discloses the level generation circuit of display device, including：Power supply module, for producing the first supply voltage and the second supply voltage；First reference voltage generation module, for producing the first reference voltage according to second supply voltage；Second reference voltage generation module, for producing the second reference voltage according to first supply voltage；Driving voltage generation module, for producing the first driving voltage and the second driving voltage according to first supply voltage, first driving voltage and second driving voltage provide the operating voltage needed for late-class circuit；And first capacitance, it is connected between the output terminal of the first reference voltage generation module and the output terminal of the second reference voltage generation module so that first reference voltage is less than second reference voltage.Level generation circuit disclosed in the present application may insure that late-class circuit works normally.
Description
Technical field
The present invention relates to technical field of liquid crystal display, more particularly, to the level generation circuit of TFT liquid crystal displays.
Background technology
TFT-LCD (amorphous silicon film transistor liquid crystal display panel) is because of its technology maturation, application in daily life
More and more extensive, the stability of further liquid crystal display-driving voltage receives much concern.In actual test, thin film transistor (TFT) is opened
Open that voltage VGH power down during power down is too fast or power down slowly all can cause late-class circuit not work normally.Power down
The cut-in voltage VGH power down of thin film transistor (TFT) is too fast in journey, causes under-voltage locking, and power supply can not provide the work needed for late-class circuit
Make voltage, cause late-class circuit not work normally.The cut-in voltage VGH power down of thin film transistor (TFT) is slow during power down, electricity
When pressure VGH persistently provides the operating voltage needed for level shifting circuit, the first reference voltage VGL1 and the second reference voltage VGL2
Sequence is disorderly, causes late-class circuit can not be worked by protection.Wherein, late-class circuit is level shifting circuit.
Due to chip differences and the difference of element itself, there are the difference of electrifying timing sequence, some elements will to electrifying timing sequence
Ask stringent.When sequential can not meet element oneself requirement when powering on, element autoprotection can be caused, cause chip normal
Work.For example, before product N1405R1 improvement, because it can not meet that low voltage starting abnormal phenomenon occurs in minimum operating voltage.Figure
1 shows the schematic diagram of electrical level transferring chip in the level generation circuit of display device in the prior art；Fig. 2 is shown in the prior art
Waveform diagram of the level generation circuit of display device in working status.With reference to Fig. 1, Fig. 2, electrical level transferring chip G2583B
There is defencive function, during normal powering down, the cut-in voltage VGH power down of thin film transistor (TFT) is slow, causes voltage VGH persistently to carry
For the operating voltage of late-class circuit, there is sequential disorder, the sequential in the first reference voltage VGL1 and the second reference voltage VGL2
Disorder causes late-class circuit to be protected.When input voltage is less than a certain value, chip does not work in guard mode：And with guarantor
Some chips of protective function are when electrifying timing sequence can not meet oneself requirement, element autoprotection, will all cause late-class circuit without
Method works normally.
Therefore, it is necessary to improved technical solution is provided to overcome above-mentioned technical problem existing in the prior art.
The content of the invention
In view of this, the main technical problem to be solved in the present invention is to provide a kind of level generation circuit of display device,
Prevent that the late-class circuit caused by the problems such as sequential is disorderly from being protected, and the operating voltage needed for late-class circuit is provided, it is ensured that after
Level circuit normal work.
The present invention provides a kind of level generation circuit of display device, including：Power supply module, for producing the first power supply electricity
Pressure and the second supply voltage；First reference voltage generation module, is electrically connected with the power supply module, for being supplied according to described second
Piezoelectric voltage produces the first reference voltage；Second reference voltage generation module, is electrically connected with the power supply module, for according to
First supply voltage produces the second reference voltage；Driving voltage generation module, is electrically connected with the power supply module, for according to institute
State the first supply voltage and produce the first driving voltage and the second driving voltage, first driving voltage and described second drive
Dynamic voltage provides the operating voltage needed for late-class circuit；And first capacitance, it is connected to the first reference voltage generation module
Output terminal and the second reference voltage generation module output terminal between so that first reference voltage is less than described the
Two reference voltages.
Preferably, the power supply module includes the first filter module, the second filter module, the first inductance and Charge Management
Chip.
Preferably, first filter module includes：First resistor, receives externally fed voltage；And two in parallel
Capacitance, to output after the externally fed voltage filter to the feeder ear of the charging management chip.
Preferably, second filter module includes：Four capacitances in parallel, pass through after being filtered to input signal by the first electricity
Sense is exported to the boosting adjusting switch pin of the charging management chip.
Preferably, input signal after the charging management chip accepts filter simultaneously is driven after handling processing by negative charge pump
Dynamic output pin output the second supply voltage to the first reference voltage generation module, passes through adjusting switch pin output first of boosting
Supply voltage is to the second reference voltage generation module or driving voltage generation module.
Preferably, first reference voltage, second reference voltage, first driving voltage and described second
Driving voltage is synchronous, wherein first reference voltage and second reference voltage are with first driving voltage and described
The reduction of second driving voltage and increase, first reference voltage and second reference voltage are with first driving voltage
And second driving voltage increase and reduce.
Preferably, the first reference voltage generation module includes：Second capacitance, the 3rd capacitance, second switch pipe, second
Resistance, 3rd resistor, the 4th resistance and the 3rd filter module, the 3rd filter module include two capacitances in parallel；Its
Second supply voltage of middle reception is exported via the second capacitance to second switch pipe by the low level output end of second switch pipe
Low-voltage via the 3rd capacitor filtering after, all the way by after the 3rd filter module secondary filtering pass through by the 4th resistance export first
Reference voltage, another way after second resistance and 3rd resistor twice partial pressure by being respectively connected to the charging management chip
The reference voltage output terminal of negative charge pump feedback end and charging management chip, the high level output end ground connection of second switch pipe.
Preferably, the second reference voltage generation module includes：4th capacitance, the 5th capacitance, first switch pipe, second
Switching tube, the 5th resistance, the 6th resistance, the first voltage-stabiliser tube and the 4th filter module, the 4th filter module include two
Capacitance in parallel；The first supply voltage wherein received passes through the low of second switch pipe via the 4th capacitance to second switch pipe
The low-voltage of level output end output is via the 5th capacitor filtering by being passed through after the 4th filter module secondary filtering by the 6th resistance
Export the second reference voltage, the high level output end ground connection of second switch pipe, the first path terminal of first switch pipe and second
Path terminal connects the 5th capacitance and the 4th filter module respectively, and the 5th resistor coupled in parallel is in the first path terminal of first switch pipe and
Between one control terminal, the first control terminal is grounded by the first voltage-stabiliser tube.
Preferably, the driving voltage generation module includes：Second voltage-stabiliser tube, the 6th capacitance, the 7th capacitance, the 7th electricity
Resistance, the 8th resistance, the 9th resistance and the 5th filter module, the 5th filter module include four capacitances in parallel；Wherein
Receive the first supply voltage via the second voltage-stabiliser tube all the way by the 5th filter module filter after export the second driving voltage or
Via the 9th resistance by exporting the first driving voltage after the 7th capacitor filtering, all the way via the 7th resistance and the 8th resistance point
Exported after pressure by the 6th capacitor filtering to the pressure feedback port of the charging management chip.
Preferably, the second switch pipe includes the diodes of two series connection, the cathode of first diode and second
The anode connection of diode, the common ports of two diodes are the input terminal of the second switch pipe, first diode it is negative
Extremely low level output end, the just extremely high level output end of second diode.
Level generation circuit disclosed in the present application may insure that late-class circuit works normally.
Brief description of the drawings
By the description to the embodiment of the present invention referring to the drawings, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings：
Fig. 1 shows the schematic diagram of electrical level transferring chip in the level generation circuit of display device in the prior art；
Fig. 2 shows waveform diagram of the level generation circuit of display device in the prior art in working status；
Fig. 3 shows the structural schematic block diagram of the level generation circuit of display device of the embodiment of the present invention
Fig. 4 shows the circuit diagram of the level generation circuit of display device of the embodiment of the present invention；
Fig. 5 shows waveform diagram of the level generation circuit of display device of the embodiment of the present invention in working status；
Embodiment
Hereinafter reference will be made to the drawings is more fully described the present invention.In various figures, identical element is using similar attached
Icon is remembered to represent.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to it is not shown some
Known part.
It describe hereinafter many specific details of the present invention, such as the structure of device, material, size, processing work
Skill and technology, to be more clearly understood that the present invention.But just as the skilled person will understand, it can not press
The present invention is realized according to these specific details.
The present invention can be presented in a variety of manners, some of them embodiment explained below.
Fig. 3 shows the structure diagram of the level generation circuit of the display device of the present invention.Level generation circuit includes supplying
Electric module 310, the first reference voltage generation module 320, the second reference voltage generation module 330, the first capacitance C1 and driving
Voltage generation module 340.First reference voltage generation module 320, the second reference voltage generation module 330 and driving voltage life
It is electrically connected respectively with power supply module 310 into module 340.Power supply module 310 includes the first filter module 311, the second filter module
312nd, the first inductance L1 and charging management chip 313.First filter module 311 is by the externally fed voltage VS filtering of reception
Output is to charging management chip 313 after reason, for powering to charging management chip 313.Second filter module 312 is by the defeated of reception
Filtered after entering signal VIN filtering process through being exported by the first inductance L1 to charging management chip 313, the reception of charging management chip 313
Input signal after ripple simultaneously exports the first supply voltage VO1 and the second supply voltage VO2 after treatment.First reference voltage is given birth to
The second supply voltage that the output of charging management chip 313 is received into module 320 generates the first reference voltage VGL1.Second with reference to electricity
Press generation module 330 to receive the first supply voltage that charging management chip 313 exports and generate the second reference voltage VGL2.First ginseng
Examine and connect the first capacitance C1 between the output terminal of voltage generation module 320 and the output terminal of the second reference voltage generation module 330,
So that the first reference voltage VGL1 of generation is in any working status in thin film transistor (TFT) cut-in voltage VGH is all consistently less than the
Two reference voltage VGL2, prevent that late-class circuit from being protected, it is ensured that late-class circuit works normally.Driving voltage generation module 340 connects
Receive the first supply voltage generation the first driving voltage AVDD of output and the second driving voltage that charging management chip 313 exports
VDDA, for providing the operating voltage needed for analog circuit, it is ensured that late-class circuit works normally, when re-powering, rear class electricity
Road works normally, display device normal work.
Fig. 4 shows the circuit diagram of the level generation circuit of the display device of the embodiment of the present invention.Level generation circuit
Including power supply module 310, the first reference voltage generation module 320, the second reference voltage generation module 330, driving voltage generation
340 and first capacitance C1 of module.
With reference to Fig. 3 as shown in figure 4, the first filter module 311 after the externally fed voltage VS filtering process of input to exporting
To the feeder ear VDD of charging management chip 313, for chip power supply.First filter module 311 include first resistor R1 and
The capacitance C8 and capacitance C9 being connected in parallel, first resistor R1 are connected to charging valve by the first common port of two capacitances in parallel
Manage the feeder ear VDD of chip 313, the second common end grounding of in parallel two capacitances.Second filter module 312 is to input signal
Through being exported by the first inductance L1 to the boosting adjusting switch pin LX of charging management chip 313 after VIN filtering process, pass through charging
The generation output of managing chip 313 first supply voltage VO1 and the second supply voltage VO2.Second filter module 312 includes parallel connection
Capacitance C12, capacitance C13, capacitance C14 and the capacitance C15 of connection, the first common port of in parallel four capacitances receive input letter
Number VIN is connected to the first inductance L1, the second common end grounding of in parallel four capacitances.The boosting tune of charging management chip 313
Section switch pin LX exports the first supply voltage VO1, and negative charge pump driving output pin DRVN exports the second supply voltage VO2.
The direct current of input is become alternating current by power supply module 310, is given birth to the first reference voltage generation module 320, the second reference voltage
Input voltage is provided respectively into module 330 and driving voltage generation module 340.
First reference voltage generation module 320 receives the second supply voltage VO2, via the second capacitance C2 to second switch pipe
M2, the low-voltage exported by the low level output end of second switch pipe M2 pass through the 3rd all the way after being filtered via the 3rd capacitance C3
Passed through after 321 secondary filtering of filter module and the first reference voltage VGL1 is exported by the 4th resistance R4；All the way by second resistance R2 with
And 3rd resistor R3 is respectively connected to the negative charge pump feedback end FBN and charging valve of charging management chip 313 after partial pressure twice
Manage the reference voltage output terminal REF of chip 313.3rd filter module 321 includes capacitance C10 and C11 in parallel, second switch
The high level output end ground connection of pipe M2, the 4th resistance R4 shield circuit.
Second reference voltage generation module 330 receives the first supply voltage VO1, via the 4th capacitance C4 to second switch pipe
M2, the low-voltage exported by the low level output end of second switch pipe M2 pass through the 4th filter module via the 5th capacitor filtering
Passed through after 331 secondary filterings and the second reference voltage VGL2 is exported by the 6th resistance R6.The high level output termination of second switch pipe M2
Ground, the 6th resistance R6 shield circuit.4th filter module 331 includes capacitance C16 and C17 in parallel, and first opens
The first path terminal and alternate path end for closing pipe M1 connect the 5th capacitance and the 4th filter module 331 respectively, and the 5th resistance is simultaneously
It is coupled between the first path terminal and the first control terminal of first switch pipe M1, the first control terminal is grounded by the first voltage-stabiliser tube D1.
First capacitance C1 is connected to the output terminal and the second reference voltage generation module of the first reference voltage generation module 320
Between 330 output terminal, capacitance both ends not mutability is utilized so that the first reference voltage VGL1 is consistently less than second with reference to electricity
Press VGL2.
Driving voltage generation module 340 receives the first supply voltage VO1, passes through the 5th filter via mono- tunnels of the second voltage-stabiliser tube D2
Ripple module 341 exports the second driving voltage VDDA or exports the after being filtered via the 9th resistance R9 by the 7th capacitance C7 after filtering
One driving voltage AVDD；All the way via after the 7th resistance R7, the 8th resistance R8 partial pressures by the 6th capacitance C6 filter after export to
The pressure feedback port FB of charging management chip 313.
The filter unit output terminal of first reference voltage generation module 320 is defeated with the second reference voltage generation module 330
The first capacitance C1 of a 0.1uF is connected between outlet, since capacitance both ends have not mutability, during whole power down
First reference voltage VGL1 is consistently less than the second reference voltage VGL2, prevents that late-class circuit from being protected, it is ensured that late-class circuit is normal
Work.Driving voltage generation module 340 in level generation circuit generates the first driving voltage AVDD and the second driving voltage
VDDA, for providing the operating voltage needed for late-class circuit, it is ensured that late-class circuit works normally, when re-powering, rear class electricity
Road works normally, display device normal work.
In this example, second switch pipe includes the diodes of two series connection, the cathode of first diode and second two
The anode of pole pipe is connected, and the common port of two diodes is the input terminal of second switch pipe, and the anode of first diode is
Low level output end, the just extremely high level output end of second diode.It should illustrate it must is Charge Management in the present embodiment
Chip 313 use SY7630 chips, but the present invention be practiced without limitation to this.
Fig. 5 shows waveform diagram of the level generation circuit of display device of the embodiment of the present invention in working status.Knot
Fig. 4 such as Fig. 5 is closed, the cut-in voltage VGH of thin film transistor (TFT), the first reference voltage VGL1 and the second reference voltage VGL2 are synchronous,
When voltage VGH is in different working condition, the first reference voltage VGL1 is consistently less than the second reference voltage VGL2, i.e., the first reference
Voltage and the second reference voltage sequential are normal, prevent that late-class circuit from being protected, it is ensured that late-class circuit works normally.Input voltage from
3.3V is down to display device during 2.4V and works normally, and exception can be shown in 2.4V to display device between 2V, voltage recover to
More than 2.4V rear indicators work normally.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant are intended to
Non-exclusive inclusion, so that process, method, article or equipment including a series of elements not only will including those
Element, but also including other elements that are not explicitly listed, or further include as this process, method, article or equipment
Intrinsic key element.In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that
Also there are other identical element in process, method, article or equipment including the key element.
According to the embodiment of the present invention as described above, these embodiments do not have all details of detailed descriptionthe, not yet
It is only the specific embodiment to limit the invention.Obviously, as described above, can make many modifications and variations.This explanation
Book is chosen and specifically describes these embodiments, is in order to preferably explain the principle of the present invention and practical application, so that affiliated
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.
Claims (10)
- A kind of 1. level generation circuit of display device, it is characterised in that including：Power supply module, for producing the first supply voltage and the second supply voltage；First reference voltage generation module, for producing the first reference voltage according to second supply voltage；Second reference voltage generation module, for producing the second reference voltage according to first supply voltage；Driving voltage generation module, for producing the first driving voltage and the second driving electricity according to first supply voltage Pressure, first driving voltage and second driving voltage provide the operating voltage needed for late-class circuit；AndFirst capacitance, is connected to the output terminal of the first reference voltage generation module and the second reference voltage generation module Output terminal between so that first reference voltage is less than second reference voltage.
- 2. the level generation circuit of display device according to claim 1, it is characterised in that the power supply module includes the One filter module, the second filter module, the first inductance and charging management chip.
- 3. the level generation circuit of display device according to claim 2, it is characterised in that the first filter module bag Include：First resistor, receives externally fed voltage；AndTwo capacitances in parallel, to output after the externally fed voltage filter to the feeder ear of the charging management chip.
- 4. the level generation circuit of display device according to claim 3, it is characterised in that the second filter module bag Include：Four capacitances in parallel, pass through after being filtered to input signal and are exported by the first inductance to the boosting tune of the charging management chip Section switch pin.
- 5. the level generation circuit of display device according to claim 4, it is characterised in that the charging management chip connects Receiving filtered input signal and handling drives output pin to export the second supply voltage to first after processing by negative charge pump Reference voltage generation module, by boost adjusting switch pin export the first supply voltage to the second reference voltage generation module or Person's driving voltage generation module.
- 6. the level generation circuit of display device according to claim 1, it is characterised in that first reference voltage, Second reference voltage, first driving voltage and second driving voltage are synchronous, wherein the first reference electricity Pressure and second reference voltage increase with the reduction of first driving voltage and second driving voltage, and described the One reference voltage and second reference voltage subtract with the increase of first driving voltage and second driving voltage It is small.
- 7. the level generation circuit of display device according to claim 5, it is characterised in that the first reference voltage life Include into module：Second capacitance, the 3rd capacitance, second switch pipe, second resistance, 3rd resistor, the 4th resistance and the 3rd filter Ripple module, the 3rd filter module include two capacitances in parallel；Wherein, for the second supply voltage of reception via the second capacitance to second switch pipe, the low level by second switch pipe is defeated After the low-voltage of outlet output is via the 3rd capacitor filtering, all the way by being passed through after the 3rd filter module secondary filtering by the 4th resistance Export the first reference voltage, another way after second resistance and 3rd resistor twice partial pressure by being respectively connected to the charging valve Manage the negative charge pump feedback end of chip and the reference voltage output terminal of charging management chip, the high level output of second switch pipe End ground connection.
- 8. the level generation circuit of display device according to claim 5, it is characterised in that the second reference voltage life Include into module：4th capacitance, the 5th capacitance, first switch pipe, second switch pipe, the 5th resistance, the 6th resistance, the first voltage stabilizing Pipe and the 4th filter module, the 4th filter module include two capacitances in parallel；Wherein, for the first supply voltage of reception via the 4th capacitance to second switch pipe, the low level by second switch pipe is defeated The low-voltage of outlet output is via the 5th capacitor filtering by being passed through after the 4th filter module secondary filtering by the 6th resistance output the Two reference voltages, the high level output end ground connection of second switch pipe, the first path terminal of first switch pipe and alternate path end The 5th capacitance and the 4th filter module are connected respectively, and the 5th resistor coupled in parallel is controlled in the first path terminal of first switch pipe and first Between end, the first control terminal is grounded by the first voltage-stabiliser tube.
- 9. the level generation circuit of display device according to claim 5, it is characterised in that the driving voltage generates mould Block includes：Second voltage-stabiliser tube, the 6th capacitance, the 7th capacitance, the 7th resistance, the 8th resistance, the 9th resistance and the 5th filtering mould Block, the 5th filter module include four capacitances in parallel；Output second is driven after the first supply voltage wherein received is filtered by the 5th filter module all the way via the second voltage-stabiliser tube Dynamic voltage or via the 9th resistance by exporting the first driving voltage after the 7th capacitor filtering, all the way via the 7th resistance and the Exported after eight electric resistance partial pressures by the 6th capacitor filtering to the pressure feedback port of the charging management chip.
- 10. the level generation circuit of the display device according to claim 7 or 8, it is characterised in that the second switch pipe Include the diodes of two series connection, the cathode of first diode is connected with the anode of second diode, two diodes Common port is the input terminal of the second switch pipe, and the anode of first diode is low level output end, second diode Just extremely high level output end.
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| CN201711059773.7A CN107993618B (en) | 2017-11-01 | 2017-11-01 | Level generating circuit of display device |
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|---|---|---|---|
| CN201711059773.7A CN107993618B (en) | 2017-11-01 | 2017-11-01 | Level generating circuit of display device |
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| CN107993618B CN107993618B (en) | 2020-09-29 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110930958A (en) * | 2019-11-26 | 2020-03-27 | Tcl华星光电技术有限公司 | Shutdown ghost eliminating circuit, array substrate and display device |
| CN114242010A (en) * | 2021-12-15 | 2022-03-25 | 惠州视维新技术有限公司 | Level conversion circuit and display device |
| CN114242015A (en) * | 2021-12-17 | 2022-03-25 | 惠州视维新技术有限公司 | Control method of display panel circuit and display panel circuit |
| CN117392951A (en) * | 2023-12-05 | 2024-01-12 | 上海视涯技术有限公司 | Power supply detection circuit, silicon-based display panel and display device |
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| CN114242010A (en) * | 2021-12-15 | 2022-03-25 | 惠州视维新技术有限公司 | Level conversion circuit and display device |
| CN114242010B (en) * | 2021-12-15 | 2023-03-10 | 惠州视维新技术有限公司 | Level conversion circuit and display device |
| CN114242015A (en) * | 2021-12-17 | 2022-03-25 | 惠州视维新技术有限公司 | Control method of display panel circuit and display panel circuit |
| CN114242015B (en) * | 2021-12-17 | 2023-01-20 | 惠州视维新技术有限公司 | Control method of display panel circuit and display panel circuit |
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