CN107993618B - Level generating circuit of display device - Google Patents
Level generating circuit of display device Download PDFInfo
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- CN107993618B CN107993618B CN201711059773.7A CN201711059773A CN107993618B CN 107993618 B CN107993618 B CN 107993618B CN 201711059773 A CN201711059773 A CN 201711059773A CN 107993618 B CN107993618 B CN 107993618B
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- 239000003990 capacitor Substances 0.000 claims abstract description 61
- 238000001914 filtration Methods 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 10
- 230000033228 biological regulation Effects 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 230000000087 stabilizing effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 10
- 102100023478 Transcription cofactor vestigial-like protein 1 Human genes 0.000 description 9
- 102100023477 Transcription cofactor vestigial-like protein 2 Human genes 0.000 description 9
- 101100102598 Mus musculus Vgll2 gene Proteins 0.000 description 8
- 101100102583 Schizosaccharomyces pombe (strain 972 / ATCC 24843) vgl1 gene Proteins 0.000 description 8
- 239000010409 thin film Substances 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 101710176146 Transcription cofactor vestigial-like protein 1 Proteins 0.000 description 1
- 101710176144 Transcription cofactor vestigial-like protein 2 Proteins 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
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- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- 239000000463 material Substances 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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Abstract
The application discloses level generation circuit of display device includes: the power supply module is used for generating a first power supply voltage and a second power supply voltage; the first reference voltage generation module is used for generating a first reference voltage according to the second power supply voltage; the second reference voltage generation module is used for generating a second reference voltage according to the first power supply voltage; the driving voltage generating module is used for generating a first driving voltage and a second driving voltage according to the first power supply voltage, and the first driving voltage and the second driving voltage provide working voltage required by a rear-stage circuit; and a first capacitor connected between the output terminal of the first reference voltage generation module and the output terminal of the second reference voltage generation module, so that the first reference voltage is smaller than the second reference voltage. The level generating circuit disclosed by the application can ensure that a rear-stage circuit works normally.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to a level generating circuit of TFT liquid crystal display.
Background
The TFT-LCD (amorphous silicon thin film transistor liquid crystal display panel) has been widely used in daily life due to its mature technology, and further, the stability of the driving voltage of the liquid crystal display has been paid much attention. In actual tests, the later-stage circuit cannot work normally due to the fact that the power failure of the starting voltage VGH of the thin film transistor is too fast or slow in the power failure process. In the power failure process, the starting voltage VGH of the thin film transistor is too fast to cause undervoltage locking, and the power supply cannot provide the working voltage required by the rear-stage circuit, so that the rear-stage circuit cannot work normally. In the power-down process, the power-down of the starting voltage VGH of the thin film transistor is slow, the voltage VGH continuously provides the working voltage required by the level conversion circuit, and the time sequences of the first reference voltage VGL1 and the second reference voltage VGL2 are disordered, so that the rear-stage circuit is protected and cannot work. Wherein, the latter stage circuit is a level conversion circuit.
Due to the difference of chips and the difference of elements, the power-on sequence is different, and the requirements of some elements on the power-on sequence are strict. When the timing sequence cannot meet the requirements of the elements during power-up, the elements can be protected, so that the chip cannot work normally. For example, before the improvement of the product N1405R1, a low-voltage start-up abnormality occurs because it cannot satisfy the minimum operating voltage. Fig. 1 is a schematic diagram illustrating a level shifter chip in a level generating circuit of a display device in the related art; fig. 2 is a waveform diagram illustrating a level generating circuit of a display device in an operating state according to the related art. With reference to fig. 1 and 2, the level shift chip G2583B has a protection function, and in a normal power failure process, the power failure of the on voltage VGH of the thin film transistor is slow, so that the voltage VGH continuously provides the working voltage of the subsequent circuit, and the timing sequence disorder occurs in the first reference voltage VGL1 and the second reference voltage VGL2, which causes the subsequent circuit to be protected. When the input voltage is lower than a certain value, the chip does not work and is in a protection state: and when the power-on sequence of some chips with the protection function can not meet the self requirement, the elements are protected by themselves, so that the subsequent circuit can not work normally.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
Accordingly, the present invention is directed to a level generating circuit of a display device, which prevents a subsequent circuit from being protected due to timing disorder, and provides an operating voltage required by the subsequent circuit to ensure the subsequent circuit to operate normally.
The present invention provides a level generating circuit of a display device, comprising: the power supply module is used for generating a first power supply voltage and a second power supply voltage; the first reference voltage generation module is electrically connected with the power supply module and used for generating a first reference voltage according to the second power supply voltage; the second reference voltage generation module is electrically connected with the power supply module and used for generating a second reference voltage according to the first power supply voltage; the driving voltage generating module is electrically connected with the power supply module and used for generating a first driving voltage and a second driving voltage according to the first power supply voltage, and the first driving voltage and the second driving voltage provide working voltage required by a rear-stage circuit; and a first capacitor connected between the output terminal of the first reference voltage generation module and the output terminal of the second reference voltage generation module, so that the first reference voltage is smaller than the second reference voltage.
Preferably, the power supply module includes a first filtering module, a second filtering module, a first inductor, and a charging management chip.
Preferably, the first filtering module includes: a first resistor receiving an external supply voltage; and the two capacitors are connected in parallel, and filter the external power supply voltage and then output to the power supply end of the charging management chip.
Preferably, the second filtering module includes: and the four capacitors are connected in parallel, and output the input signal to a boosting regulation switch pin of the charging management chip through the first inductor after filtering the input signal.
Preferably, the charge management chip receives the filtered input signal, processes the filtered input signal, outputs the second supply voltage to the first reference voltage generation module through the negative charge pump driving output pin, and outputs the first supply voltage to the second reference voltage generation module or the driving voltage generation module through the boost regulation switch pin.
Preferably, the first reference voltage, the second reference voltage, the first driving voltage and the second driving voltage are synchronized, wherein the first reference voltage and the second reference voltage increase with decreasing of the first driving voltage and the second driving voltage, and the first reference voltage and the second reference voltage decrease with increasing of the first driving voltage and the second driving voltage.
Preferably, the first reference voltage generating module includes: the filter comprises a first capacitor, a second switch tube, a second resistor, a third resistor, a fourth resistor and a third filter module, wherein the third filter module comprises two capacitors connected in parallel; the received second power supply voltage is transmitted to a second switch tube through a second capacitor, the low voltage output by the low level output end of the second switch tube is filtered by a third capacitor, the first reference voltage is output by a fourth resistor after the first reference voltage is filtered by a third filtering module for the second time, the second reference voltage is connected to the negative charge pump feedback end of the charge management chip and the reference voltage output end of the charge management chip after the second reference voltage is divided by a second resistor and a third resistor for the second time, and the high level output end of the second switch tube is grounded.
Preferably, the second reference voltage generating module includes: the filter comprises a fourth capacitor, a fifth capacitor, a first switch tube, a second switch tube, a fifth resistor, a sixth resistor, a first voltage regulator tube and a fourth filter module, wherein the fourth filter module comprises two capacitors connected in parallel; the received first power supply voltage is transmitted to the second switch tube through the fourth capacitor, the low voltage output by the low level output end of the second switch tube is filtered by the fifth capacitor, passes through the fourth filter module for secondary filtering and then is output as a second reference voltage through the sixth resistor, the high level output end of the second switch tube is grounded, the first pass end and the second pass end of the first switch tube are respectively connected with the fifth capacitor and the fourth filter module, the fifth resistor is connected between the first pass end and the first control end of the first switch tube in parallel, and the first control end is grounded through the first voltage stabilizing tube.
Preferably, the driving voltage generating module includes: the filter comprises a first voltage regulator tube, a sixth capacitor, a seventh resistor, an eighth resistor, a ninth resistor and a fifth filter module, wherein the fifth filter module comprises four capacitors connected in parallel; the first power supply voltage is filtered by a fifth filtering module through one path of a second voltage-stabilizing tube and then outputs a second driving voltage or filtered by a seventh capacitor through a ninth resistor and then outputs a first driving voltage, and one path of the first power supply voltage is divided by a seventh resistor and an eighth resistor and then filtered by a sixth capacitor and then output to a voltage feedback end of the charging management chip.
Preferably, the second switch tube includes two diodes connected in series, an anode of the first diode is connected to a cathode of the second diode, a common end of the two diodes is an input end of the second switch tube, a cathode of the first diode is a low-level output end, and an anode of the second diode is a high-level output end.
The level generating circuit disclosed by the application can ensure that a rear-stage circuit works normally.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a schematic diagram illustrating a level shifter chip in a level generating circuit of a display device in the related art;
fig. 2 is a waveform diagram illustrating a level generating circuit of a display device in an operating state according to the prior art;
FIG. 3 is a block diagram showing a schematic structure of a level generating circuit of a display device according to an embodiment of the present invention
FIG. 4 is a circuit diagram of a level generating circuit of a display device according to an embodiment of the invention;
FIG. 5 is a waveform diagram illustrating a level generating circuit of a display device according to an embodiment of the present invention in an operating state;
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The present invention may be embodied in various forms, some of which will be described below.
Fig. 3 is a schematic diagram showing a structure of a level generating circuit of a display device according to the present invention. The level generating circuit includes a power supply module 310, a first reference voltage generating module 320, a second reference voltage generating module 330, a first capacitor C1, and a driving voltage generating module 340. The first reference voltage generation module 320, the second reference voltage generation module 330, and the driving voltage generation module 340 are electrically connected to the power supply module 310, respectively. The power supply module 310 includes a first filtering module 311, a second filtering module 312, a first inductor L1, and a charging management chip 313. The first filtering module 311 filters the received external power supply voltage VS and outputs the filtered external power supply voltage VS to the charging management chip 313, so as to supply power to the charging management chip 313. The second filtering module 312 filters the received input signal VIN and outputs the filtered input signal VIN to the charge management chip 313 through the first inductor L1, and the charge management chip 313 receives the filtered input signal and outputs the first supply voltage VO1 and the second supply voltage VO2 after processing. The first reference voltage generation module 320 receives the second power supply voltage output by the charging management chip 313 to generate the first reference voltage VGL 1. The second reference voltage generation module 330 receives the first power supply voltage output by the charging management chip 313 to generate a second reference voltage VGL 2. The first capacitor C1 is connected between the output terminal of the first reference voltage generation module 320 and the output terminal of the second reference voltage generation module 330, so that the generated first reference voltage VGL1 is always smaller than the second reference voltage VGL2 in any operating state of the tft turn-on voltage VGH, thereby preventing the rear-stage circuit from being protected and ensuring the normal operation of the rear-stage circuit. The driving voltage generating module 340 receives the first power supply voltage output by the charging management chip 313 to generate and output a first driving voltage AVDD and a second driving voltage VDDA, which are used to provide a working voltage required by the analog circuit to ensure that the rear-stage circuit works normally.
Fig. 4 is a circuit diagram showing a level generating circuit of a display device according to an embodiment of the present invention. The level generating circuit includes a power supply module 310, a first reference voltage generating module 320, a second reference voltage generating module 330, a driving voltage generating module 340, and a first capacitor C1.
As shown in fig. 4 with reference to fig. 3, the first filtering module 311 filters the input external power supply voltage VS and outputs the filtered external power supply voltage VS to the power supply terminal VDD of the charge management chip 313 for supplying power to the chip. The first filtering module 311 includes a first resistor R1, and a capacitor C8 and a capacitor C9 connected in parallel, the first resistor R1 is connected to the power supply terminal VDD of the charge management chip 313 through a first common terminal of the two capacitors connected in parallel, and a second common terminal of the two capacitors connected in parallel is grounded. The second filtering module 312 filters the input signal VIN, outputs the filtered input signal VIN to the boost regulating switch pin LX of the charge management chip 313 through the first inductor L1, and generates and outputs the first supply voltage VO1 and the second supply voltage VO2 through the charge management chip 313. The second filtering module 312 includes a capacitor C12, a capacitor C13, a capacitor C14, and a capacitor C15 connected in parallel, where a first common terminal of the four capacitors connected in parallel receives the input signal VIN and is connected to the first inductor L1, and a second common terminal of the four capacitors connected in parallel is grounded. The boost regulation switch pin LX of the charge management chip 313 outputs a first supply voltage VO1, and the negative charge pump driver output pin DRVN outputs a second supply voltage VO 2. The power supply module 310 converts the input dc power into ac power, and provides input voltages to the first reference voltage generation module 320, the second reference voltage generation module 330, and the driving voltage generation module 340, respectively.
The first reference voltage generating module 320 receives the second supply voltage VO2, passes through the second capacitor C2 to the second switch tube M2, filters the low voltage output from the low level output terminal of the second switch tube M2 through the third capacitor C3, and outputs the first reference voltage VGL1 through the fourth resistor R4 after the first path of the filtered low voltage passes through the third filtering module 321 and is filtered twice; one path is connected to the negative charge pump feedback terminal FBN of the charge management chip 313 and the reference voltage output terminal REF of the charge management chip 313 after twice voltage division through the second resistor R2 and the third resistor R3. The third filtering module 321 includes capacitors C10 and C11 connected in parallel, the high level output terminal of the second switch transistor M2 is grounded, and the fourth resistor R4 protects the circuit.
The second reference voltage generating module 330 receives the first power supply voltage VO1, and outputs the second reference voltage VGL2 through the fourth capacitor C4 to the second switching tube M2, and the low voltage output from the low level output terminal of the second switching tube M2 is filtered by the fifth capacitor, is filtered by the fourth filtering module 331 for the second time, and then is output by the sixth resistor R6. The high level output end of the second switch tube M2 is grounded, and the sixth resistor R6 protects the circuit. The fourth filtering module 331 includes capacitors C16 and C17 connected in parallel, a first path end and a second path end of the first switch tube M1 are respectively connected to the fifth capacitor and the fourth filtering module 331, the fifth resistor is connected in parallel between the first path end and a first control end of the first switch tube M1, and the first control end is grounded through a first voltage regulator tube D1.
The first capacitor C1 is connected between the output terminal of the first reference voltage generation module 320 and the output terminal of the second reference voltage generation module 330, and the first reference voltage VGL1 is always smaller than the second reference voltage VGL2 by utilizing the non-abrupt change of the two ends of the capacitor.
The driving voltage generating module 340 receives the first power supply voltage VO1, and outputs the second driving voltage VDDA after being filtered by the fifth filtering module 341 through one path of the second regulator D2 or outputs the first driving voltage AVDD after being filtered by the seventh capacitor C7 through the ninth resistor R9; one path is divided by the seventh resistor R7 and the eighth resistor R8, filtered by the sixth capacitor C6, and output to the voltage feedback terminal FB of the charge management chip 313.
A first capacitor C1 of 0.1uF is connected between the output end of the filtering unit of the first reference voltage generation module 320 and the output end of the second reference voltage generation module 330, and because the two ends of the capacitor have non-mutability, the first reference voltage VGL1 is always smaller than the second reference voltage VGL2 in the whole power-down process, so that the rear-stage circuit is prevented from being protected, and the normal operation of the rear-stage circuit is ensured. The driving voltage generating module 340 in the level generating circuit generates a first driving voltage AVDD and a second driving voltage VDDA for providing a working voltage required by the rear-stage circuit to ensure that the rear-stage circuit works normally.
In this example, the second switch tube includes two diodes connected in series, an anode of the first diode is connected to a cathode of the second diode, a common end of the two diodes is an input end of the second switch tube, the cathode of the first diode is a low level output end, and the anode of the second diode is a high level output end. It should be noted that the charging management chip 313 in this embodiment adopts a SY7630 chip, but the implementation of the present invention is not limited thereto.
Fig. 5 is a waveform diagram illustrating a level generating circuit of a display device according to an embodiment of the invention in an operating state. Referring to fig. 5 in conjunction with fig. 4, the on-voltage VGH of the tft, the first reference voltage VGL1 and the second reference voltage VGL2 are synchronous, and when the voltage VGH is in different operating states, the first reference voltage VGL1 is always smaller than the second reference voltage VGL2, that is, the timing sequence of the first reference voltage and the second reference voltage is normal, so as to prevent the rear-stage circuit from being protected and ensure the rear-stage circuit to operate normally. The display device works normally when the input voltage is reduced to 2.4V from 3.3V, the display device can display abnormity between 2.4V and 2V, and the display device works normally after the voltage is recovered to be more than 2.4V.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.
Claims (10)
1. A level generating circuit of a display device, comprising:
the power supply module is used for generating a first power supply voltage and a second power supply voltage;
the first reference voltage generation module is used for generating a first reference voltage according to the second power supply voltage;
the second reference voltage generation module is used for generating a second reference voltage according to the first power supply voltage;
the driving voltage generating module is used for generating a first driving voltage and a second driving voltage according to the first power supply voltage, and the first driving voltage and the second driving voltage provide working voltage required by a rear-stage circuit; and
and the first capacitor is connected between the output end of the first reference voltage generation module and the output end of the second reference voltage generation module, so that the first reference voltage is smaller than the second reference voltage, the rear-stage circuit is not in a protection state, the rear-stage circuit is a level conversion circuit, and the first reference voltage and the second reference voltage are negative voltages provided for the rear-stage circuit.
2. The circuit of claim 1, wherein the power supply module comprises a first filtering module, a second filtering module, a first inductor, and a charging management chip.
3. The level generating circuit of claim 2, wherein the first filtering module comprises:
a first resistor receiving an external supply voltage; and
and the two capacitors are connected in parallel, and filter the external power supply voltage and then output to the power supply end of the charging management chip.
4. The level generating circuit of claim 3, wherein the second filtering module comprises:
and the four capacitors are connected in parallel, and output the input signal to a boosting regulation switch pin of the charging management chip through the first inductor after filtering the input signal.
5. The circuit of claim 4, wherein the charge management chip receives the filtered input signal, processes the filtered input signal by a manager, and outputs the second supply voltage to the first reference voltage generation module through a negative charge pump driving output pin, and outputs the first supply voltage to the second reference voltage generation module or the driving voltage generation module through a boost regulation switch pin.
6. The level generating circuit according to claim 1, wherein the first reference voltage, the second reference voltage, the first driving voltage, and the second driving voltage are synchronized, wherein the first reference voltage and the second reference voltage increase as the first driving voltage and the second driving voltage decrease, and wherein the first reference voltage and the second reference voltage decrease as the first driving voltage and the second driving voltage increase.
7. The level generating circuit of claim 5, wherein the first reference voltage generating module comprises: the filter comprises a first capacitor, a second switch tube, a second resistor, a third resistor, a fourth resistor and a third filter module, wherein the third filter module comprises two capacitors connected in parallel;
the received second power supply voltage is transmitted to the second switch tube through the second capacitor, the low voltage output by the low level output end of the second switch tube is filtered by the third capacitor, the first reference voltage is output by the fourth resistor after the first reference voltage is filtered by the third filter module for the second time, the second reference voltage is connected to the negative charge pump feedback end of the charge management chip and the reference voltage output end of the charge management chip after the second reference voltage and the third reference voltage are divided twice through the second resistor and the third resistor, and the high level output end of the second switch tube is grounded.
8. The level generating circuit of claim 5, wherein the second reference voltage generating module comprises: the filter comprises a fourth capacitor, a fifth capacitor, a first switch tube, a second switch tube, a fifth resistor, a sixth resistor, a first voltage regulator tube and a fourth filter module, wherein the fourth filter module comprises two capacitors connected in parallel;
the received first power supply voltage is transmitted to the second switch tube through the fourth capacitor, the low voltage output by the low level output end of the second switch tube is filtered by the fifth capacitor, filtered by the fourth filter module for the second time, and then is transmitted to the sixth resistor to output the second reference voltage, the high level output end of the second switch tube is grounded, the first pass end and the second pass end of the first switch tube are respectively connected with the fifth capacitor and the fourth filter module, the fifth resistor is connected between the first pass end and the first control end of the first switch tube in parallel, and the first control end is grounded through the first voltage stabilizing tube.
9. The level generating circuit of claim 5, wherein the driving voltage generating module comprises: the filter comprises a first voltage regulator tube, a sixth capacitor, a seventh resistor, an eighth resistor, a ninth resistor and a fifth filter module, wherein the fifth filter module comprises four capacitors connected in parallel;
the first power supply voltage is filtered by a fifth filtering module through one path of a second voltage-stabilizing tube and then outputs a second driving voltage or filtered by a seventh capacitor through a ninth resistor and then outputs a first driving voltage, and one path of the first power supply voltage is divided by a seventh resistor and an eighth resistor and then filtered by a sixth capacitor and then output to a voltage feedback end of the charging management chip.
10. The circuit of claim 7 or 8, wherein the second switch tube comprises two diodes connected in series, the anode of the first diode is connected to the cathode of the second diode, the common terminal of the two diodes is the input terminal of the second switch tube, the cathode of the first diode is the low output terminal, and the anode of the second diode is the high output terminal.
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| CN110930958A (en) * | 2019-11-26 | 2020-03-27 | Tcl华星光电技术有限公司 | Shutdown ghost eliminating circuit, array substrate and display device |
| CN114242010B (en) * | 2021-12-15 | 2023-03-10 | 惠州视维新技术有限公司 | Level conversion circuit and display device |
| CN114242015B (en) * | 2021-12-17 | 2023-01-20 | 惠州视维新技术有限公司 | Control method of display panel circuit and display panel circuit |
| CN117392951B (en) * | 2023-12-05 | 2024-03-19 | 上海视涯技术有限公司 | Power supply detection circuit, silicon-based display panel and display device |
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