CN106847215A - Display device - Google Patents
Display device Download PDFInfo
- Publication number
- CN106847215A CN106847215A CN201710121270.1A CN201710121270A CN106847215A CN 106847215 A CN106847215 A CN 106847215A CN 201710121270 A CN201710121270 A CN 201710121270A CN 106847215 A CN106847215 A CN 106847215A
- Authority
- CN
- China
- Prior art keywords
- clock signal
- signal
- transistor
- pole
- display device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000013078 crystal Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 14
- 238000010586 diagram Methods 0.000 description 12
- 230000005611 electricity Effects 0.000 description 12
- 210000002858 crystal cell Anatomy 0.000 description 5
- 239000010409 thin film Substances 0.000 description 4
- 102100039435 C-X-C motif chemokine 17 Human genes 0.000 description 3
- 101000889048 Homo sapiens C-X-C motif chemokine 17 Proteins 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000004134 energy conservation Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a kind of display device, including：Display panel；Power supply chip, is connected with display panel, for providing supply voltage for display panel, and produces first group of clock signal；Driving chip, for producing gain selection signals and grayscale signal to drive display panel display image according to second group of clock signal；First time sequence adjusting circuit, is connected between driving chip and power supply chip, for first group of clock signal to be converted into second group of clock signal.The display device that the present invention is provided, second group of clock signal needed for first group of clock signal that power supply chip is provided is converted into driving chip by the first time sequence adjusting circuit, solves the problems, such as that the sequential that power supply chip is provided can not normally show with the caused liquid crystal display device of sequential mismatch needed for driving chip.
Description
Technical field
The invention belongs to display technology field, more particularly, to a kind of display device.
Background technology
Because liquid crystal display device has the advantages that frivolous, energy-conservation, low-power consumption, TV, computer, hand have been widely used in it
In the electronic equipments such as machine, digital camera.
Fig. 1 shows the schematic block diagram of the display device according to prior art.As shown in figure 1, display device includes display
Panel 10, driving chip (Driver IC) 20 and power supply chip (Power IC) 30.Although display panel 10 does not enter especially
Row diagram, but it is configured with multiple pixels in a matrix form on the glass substrate, and each pixel has the film being connected in series brilliant
Body pipe and liquid crystal cell.Liquid crystal cell to each pixel applies common electric potential Vcom.The selection terminal of thin film transistor (TFT) is arranging
For unit is connected to controlling grid scan line G1~Gm, the signal terminal of thin film transistor (TFT) with behavior unit be connected to gated sweep
The source data line S1~Sn configured on the direction that line G1~Gm intersects.
In Fig. 1, driving chip 20 includes time schedule controller 21, gate drivers 22 and source electrode driver 23, grid
Driver 22 is connected with a plurality of controlling grid scan line G1~Gm, for providing grid power supply, source electrode driver 23 and a plurality of source electrode number
Connected according to line S1~Sn, for providing gray scale voltage.Time schedule controller 21 respectively with gate drivers 22 and source electrode driver
23 are connected, so as to provide various clock signals to gate drivers 22 and source electrode driver 23.Within a frame period, lead to
Crossing in units of controlling grid scan line turns on the thin film transistor (TFT) of pixel to select controlling grid scan line, controlling grid scan line each
Apply grayscale voltage during selection (during level shows) from source data line S1~Sn to liquid crystal cell.The gray scale electricity for being applied
The capacitive component for being retained as liquid crystal cell before select next time because thin film transistor (TFT) is cut off is pressed, liquid crystal cell is kept
Shutter (shutter) state of part.
The time schedule controller 21 of liquid crystal display device needs the power supply chip 30 of outside to provide DC voltage+5V or+12V.
For example, the power supply chip 30 of outside to driving chip 20 provide source electrode malleation VSP, source electrode negative pressure VSN, grid malleation VGH and
Grid negative pressure VGL, but the sequential and time schedule controller 21 of VSP, VSN, VGH and VGL of the offer of the power supply chip 30 of outside
The sequential of VSP, VSN, VGH and VGL of required outside is possible to inconsistent.
First group of oscillogram of clock signal that power supply chip is provided in the display device that Fig. 2 a show according to prior art.
As shown in Figure 2 a, the electrifying timing sequence that outside power supply chip 30 is provided is for VSP, VGH, VSN while upper electricity；And VGL VSP,
Upper electricity after VGH, VSN.Second group of clock signal in the display device that Fig. 2 b show according to prior art needed for driving chip
Oscillogram.As shown in Figure 2 b, the electrifying timing sequence of the offer of driving chip 20 is：After VGH goes up the upper electricity of electricity, VGL again after the upper electricity of VSP
VSN goes up electricity again.As described above, the required electrifying timing sequence of electrifying timing sequence and driving chip 20 that provides of power supply chip 30 is not
Match somebody with somebody, cause liquid crystal display device normally to show, or even driving chip 20 can be caused to damage, influence service life.
The content of the invention
It is an object of the invention to provide a kind of display device.
According to an aspect of the present invention, there is provided a kind of display device, including：Display panel；Power supply chip, with the display
Panel is connected, and for providing supply voltage for the display panel, and produces first group of clock signal；Driving chip, with institute
Display panel connection is stated, for producing gain selection signals and grayscale signal to drive the display according to second group of clock signal
Display panel image；First time sequence adjusting circuit, is connected between the driving chip and power supply chip, during for by first group
Sequential signal is converted to second group of clock signal.
Preferably, the display panel has a plurality of gate line intersected with each other and a plurality of data lines and in the grid
Multiple pixels that the infall of line and the data wire is formed；And the supply voltage includes grid voltage and source voltage.
Preferably, the driving chip includes：Time schedule controller, for providing second group of clock signal and display data
Signal；Gate drivers, for producing gain selection signals according to the grid voltage and applying the gain selection signals
To the gate line；Source electrode driver, for producing GTG corresponding with the display data signal according to the source voltage
Voltage, and the gray scale voltage is applied to the data wire.
Preferably, first group of clock signal includes the 3rd clock signal and the 4th clock signal, at described second group
Sequential signal includes the 5th clock signal and the 6th clock signal.
Preferably, first time sequence adjusting circuit includes：First sequential adjustment unit, for the 3rd clock signal to be turned
Change the 5th clock signal into；Second sequential adjustment unit, for the 4th clock signal to be converted into the 6th clock signal；Wherein,
Grid negative pressure and the clock signal of source electrode negative pressure that 3rd clock signal is provided for power supply chip；4th clock signal
The grid malleation and the clock signal of source electrode malleation provided for power supply chip；5th clock signal is for needed for driving chip
The clock signal of grid negative pressure and source electrode negative pressure；Grid malleation and source electrode of 6th clock signal for needed for driving chip are just
The clock signal of pressure.
Preferably, the first sequential adjustment unit includes the first transistor and first resistor, wherein, the first crystal
The control pole of pipe is connected with the first signal input part；First pole of the first transistor is connected by first resistor with earth terminal
Connect；Second pole of the first transistor is connected with secondary signal input；The control pole of the first transistor and the first letter
Number output end is connected；Node between first pole of the first transistor and first resistor is connected with secondary signal output end；
First signal input part is connected with grid negative pressure；The secondary signal input is connected with source electrode negative pressure.
Preferably, second adjustment unit includes transistor seconds and second resistance；Wherein, the transistor seconds
Control pole is connected with the 3rd signal input part；First pole of the transistor seconds passes through second resistance and the transistor seconds
Control pole connection；Node between first pole of the transistor seconds and second resistance is connected with the 4th signal input part；
The control pole of the transistor seconds is connected with the 3rd signal output part；Second pole of the transistor seconds is defeated with the 4th signal
Go out end to be connected；
3rd signal input part is connected with source electrode malleation, and the 4th signal input part is connected with grid malleation.
Preferably, the display device also includes the second time sequence adjusting circuit, for according to the first of driving chip the control
Signal and the first supply voltage generate the second control signal, wherein, second control signal is used to make power supply chip work
And produce first group of clock signal.
Preferably, the driving chip produces first control signal according to second source voltage, wherein, described first
Control signal is universal input/output interface signal.
Preferably, second time sequence adjusting circuit includes third transistor and 3rd resistor, wherein, the 3rd crystal
The control pole of pipe is connected with first control signal；First pole of the third transistor passes through 3rd resistor and the described 3rd
The control pole connection of transistor；Node between first pole of the third transistor and 3rd resistor is believed with second source voltage
Number be connected；Second pole of the third transistor is connected with power supply chip, for exporting the second control signal.
Display device provided in an embodiment of the present invention, power supply chip is provided by the first time sequence adjusting circuit first group
Clock signal be converted into driving chip needed for second group of clock signal, solve power supply chip offer sequential and driving chip
Required sequential mismatches the problem that caused liquid crystal display device can not normally show.The second time sequence adjusting circuit is utilized simultaneously
Driving chip is completed power supply chip normal work after initialization, supply voltage is provided to driving chip, make display normal, steady
It is fixed, improve the reliability of display device.
Brief description of the drawings
By description referring to the drawings to the embodiment of the present invention, of the invention above-mentioned and other purposes, feature and
Advantage will be apparent from, in the accompanying drawings：
Fig. 1 shows the schematic block diagram of the display device according to prior art；
First group of oscillogram of clock signal that power supply chip is provided in the display device that Fig. 2 a show according to prior art；
Second group of oscillogram of clock signal in the display device that Fig. 2 b show according to prior art needed for driving chip；
Fig. 3 shows the schematic block diagram of display device according to embodiments of the present invention；
Fig. 4 shows the circuit diagram of the first time sequence adjusting circuit of display device according to embodiments of the present invention.
Fig. 5 shows the schematic block diagram of display device according to embodiments of the present invention；
Fig. 6 shows the circuit diagram of the second time sequence adjusting circuit of display device according to embodiments of the present invention.
Specific embodiment
Various embodiments of the present invention are more fully described hereinafter with reference to accompanying drawing.In various figures, identical element
Represented using same or similar reference.For the sake of clarity, the various pieces in accompanying drawing are not necessarily to scale.
The present invention can be presented in a variety of manners, some of them example explained below.
Fig. 3 shows the schematic block diagram of the display device of offer according to embodiments of the present invention.As shown in figure 3, described aobvious
Showing device includes display panel 10, driving chip 20, the time sequence adjusting circuit 40 of power supply chip 30 and first.
Display panel 10 has a plurality of gate lines G 1-Gm and a plurality of data lines S1-Sn intersected with each other and in the grid
Multiple pixels that the infall of polar curve G1-Gm and the data wire S1-Sn is formed.
Power supply chip 30 provides supply voltage and generation first group of clock signal for the display panel, wherein, it is described
Supply voltage includes grid voltage and source voltage.Grid voltage is the open and close voltage of switching tube on pixel, is added in out
Close on the grid of pipe, including grid malleation VGH, grid negative pressure VGL, wherein, VGH high level is opened and charged to pixel electric capacity,
VGL negative voltage closing switch pipes.Source voltage is liquid crystal drive power supply, charges to the electric capacity of control pixel printing opacity, bag
Include source electrode malleation VSP, source electrode negative pressure VSN.
Driving chip 20 is connected with the display panel 10, and gain selection signals and ash are produced according to second group of clock signal
Rank signal is driving the display image of the display panel 10.
In the present embodiment, driving chip 20 includes time schedule controller 21, gate drivers 22 and source electrode driver 23, its
In, time schedule controller 21 is used to provide second group of clock signal and display data signal；Gate drivers 22 are used for according to institute
Grid voltage is stated to produce gain selection signals (VGH, VGL) and the gain selection signals are applied into the gate lines G 1-Gm；
Source electrode driver 23 is used to produce GTG electricity corresponding with the display data signal according to the source voltage (VSP, VSN)
Pressure, and the gray scale voltage is applied to the data wire S1-Sn.
First time sequence adjusting circuit 40, is connected between the driving chip 20 and power supply chip 30, for by first group
Clock signal is converted to second group of clock signal.
In the present embodiment, first group of clock signal includes the 3rd clock signal and the 4th clock signal, described the
Two groups of clock signals include the 5th clock signal and the 6th clock signal.First group of clock signal and second group of clock signal are
Clock signal between VGH, VGL, VSP, VSN.3rd clock signal is the sequential letter of the VSN that power supply chip 30 is provided and VGL
Number, the 4th clock signal is the clock signal of the VSP that power supply chip 30 is provided and VGH；5th clock signal is driving chip 20
Required VSN and the clock signal of VGL, the clock signal of VSP and VGH of the 6th clock signal for needed for driving chip 20.
Fig. 4 shows the circuit diagram of the first time sequence adjusting circuit of display device according to embodiments of the present invention.Such as Fig. 4 institutes
Show, first time sequence adjusting circuit 40 includes the first sequential adjustment unit 41 and the second sequential adjustment unit 42, wherein, first
Sequential adjustment unit 41 is used to for the 3rd clock signal to be converted into the 5th clock signal；Second sequential adjustment unit 42 is used for the
Four clock signals are converted into the 6th clock signal.
The first sequential adjustment unit 41 includes the first transistor Q1 and first resistor R1, wherein, the first crystal
The control pole of pipe Q1 is connected with the first signal input part；First pole of the first transistor Q1 passes through first resistor R1 and earth terminal
GND is connected；Second pole of the first transistor Q1 is connected with secondary signal input；The control pole of the first transistor Q1 and the
One signal output part is connected；Node and secondary signal output end phase between first pole of the first transistor Q1 and first resistor R1
Even.
Wherein, first signal input part is connected with grid negative pressure VGL；The secondary signal input and source electrode negative pressure
VSN is connected.
In the present embodiment, the first transistor Q1 is P-channel enhancement type MOS transistor, and control extremely grid, first are extremely
Source electrode, second extremely drain, with cut-in voltage UGS(th), wherein, UGS(th)<0.Work as UGS<UGS(th)When, at the first transistor Q1
In conducting state, you can become resistance area；Work as UGS>UGS(th)When, the first transistor Q1 is in cut-off state.
When power supply chip 30 first exports VSN, grid and the source electrode of the first transistor Q1 are low level, the first transistor
Q1 is in cut-off state, is input to the VSN=0 of driving chip 20.After grid negative pressure VGL is output, at the first transistor Q1
In conducting state, now source electrode negative pressure VSN is exported from secondary signal output end, i.e., only after grid negative pressure VGL is output, source
Pole negative pressure VSN could be exported to driving chip 20, realized that grid negative pressure VGL is first exported and export after source electrode negative pressure VSN to driving core
The sequential of piece 20.
Second adjustment unit 42 includes transistor seconds Q2 and second resistance R2；Wherein, the transistor seconds Q2
Control pole be connected with the 3rd signal input part；First pole of transistor seconds Q2 passes through second resistance R2 and second crystal
The control pole connection of pipe Q2；Node and the 4th signal input part phase between first pole of transistor seconds Q2 and second resistance R2
Even；The control pole of transistor seconds Q2 is connected with the 3rd signal output part；Second pole of transistor seconds Q2 is defeated with the 4th signal
Go out end to be connected.
Wherein, the 3rd signal input part is connected with source electrode malleation VSP, the 4th signal input part and grid malleation
VGH is connected.
In the present embodiment, transistor seconds Q2 is P-channel enhancement type MOS transistor, and control extremely grid, first are extremely
Source electrode, second extremely drain, with cut-in voltage UGS(th), wherein, UGS(th)<0.Work as UGS<UGS(th)When, at transistor seconds Q2
In conducting state, you can become resistance area；Work as UGS>UGS(th)When, transistor seconds Q2 is in cut-off state.
When power supply chip 30 exports VGH, the grid voltage of transistor seconds Q2 is equal with source voltage, transistor seconds
In cut-off state, the VGH=0 of driving chip 20 is input to, when source electrode malleation VSP is output, transistor seconds Q2 is in
Conducting state, now grid malleation VGH exported from the 4th signal output part, i.e., only after source electrode malleation VSP is output, grid
Malleation VGH can just be exported to driving chip 20, realize that source electrode malleation VSP is first exported and export after grid malleation VGH to driving core
The sequential of piece 20.
Display device provided in an embodiment of the present invention, power supply chip is provided by the first time sequence adjusting circuit first group
Clock signal be converted into driving chip needed for second group of clock signal, solve power supply chip offer sequential and driving chip
Required sequential mismatches the problem that caused liquid crystal display device can not normally show.
Fig. 5 shows the schematic block diagram of the display device of offer according to embodiments of the present invention.As shown in figure 5, described aobvious
Showing device includes display panel 10, driving chip 20, power supply chip 30, the first time sequence adjusting circuit 40 and the second sequential adjustment electricity
Road 50.
Display panel 10 has a plurality of gate lines G 1-Gm and a plurality of data lines S1-Sn intersected with each other and in the grid
Multiple pixels that the infall of polar curve G1-Gm and the data wire S1-Sn is formed.
Power supply chip 30 provides supply voltage and generation first group of clock signal for the display panel, wherein, it is described
Supply voltage includes grid voltage and source voltage.Grid voltage is the open and close voltage of switching tube on pixel, is added in out
Close on the grid of pipe, including grid malleation VGH, grid negative pressure VGL, wherein, VGH high level is opened and charged to pixel electric capacity,
VGL negative voltage closing switch pipes.Source voltage is liquid crystal drive power supply, charges to the electric capacity of control pixel printing opacity, bag
Include source electrode malleation VSP, source electrode negative pressure VSN.
Driving chip 20 is connected with the display panel 10, and gain selection signals and ash are produced according to second group of clock signal
Rank signal is driving the display image of the display panel 10.
In the present embodiment, driving chip 20 includes time schedule controller 21, gate drivers 22 and source electrode driver 23, its
In, time schedule controller 21 is used to provide second group of clock signal and display data signal；Gate drivers 22 are used for according to institute
Grid voltage is stated to produce gain selection signals (VGH, VGL) and the gain selection signals are applied into the gate lines G 1-Gm；
Source electrode driver 23 is used to produce GTG electricity corresponding with the display data signal according to the source voltage (VSP, VSN)
Pressure, and the gray scale voltage is applied to the data wire S1-Sn.
First time sequence adjusting circuit 40, is connected between the driving chip 20 and power supply chip 30, for by first group
Clock signal is converted to second group of clock signal.
In the present embodiment, first group of clock signal includes the 3rd clock signal and the 4th clock signal, described the
Two groups of clock signals include the 5th clock signal and the 6th clock signal.First group of clock signal and second group of clock signal are
Clock signal between VGH, VGL, VSP, VSN.3rd clock signal is the sequential letter of the VSN that power supply chip 30 is provided and VGL
Number, the 4th clock signal is the clock signal of the VSP that power supply chip 30 is provided and VGH；5th clock signal is driving chip 20
Required VSN and the clock signal of VGL, the clock signal of VSP and VGH of the 6th clock signal for needed for driving chip 20.
Fig. 4 shows the circuit diagram of the first time sequence adjusting circuit of display device according to embodiments of the present invention.Such as Fig. 4 institutes
Show, first time sequence adjusting circuit 40 includes the first sequential adjustment unit 41 and the second sequential adjustment unit 42, wherein, first
Sequential adjustment unit 41 is used to for the 3rd clock signal to be converted into the 5th clock signal；Second sequential adjustment unit 42 is used for the
Four clock signals are converted into the 6th clock signal.
The first sequential adjustment unit 41 includes the first transistor Q1 and first resistor R1, wherein, the first crystal
The control pole of pipe Q1 is connected with the first signal input part；First pole of the first transistor Q1 passes through first resistor R1 and earth terminal
GND is connected；Second pole of the first transistor Q1 is connected with secondary signal input；The control pole of the first transistor Q1 and the
One signal output part is connected；Node and secondary signal output end phase between first pole of the first transistor Q1 and first resistor R1
Even.
Wherein, first signal input part is connected with grid negative pressure VGL；The secondary signal input and source electrode negative pressure
VSN is connected.
In the present embodiment, the first transistor Q1 is P-channel enhancement type MOS transistor, and control extremely grid, first are extremely
Source electrode, second extremely drain, with cut-in voltage UGS(th), wherein, UGS(th)<0.Work as UGS<UGS(th)When, at the first transistor Q1
In conducting state, you can become resistance area；Work as UGS>UGS(th)When, the first transistor Q1 is in cut-off state.
When power supply chip 30 first exports VSN, grid and the source electrode of the first transistor Q1 are low level, the first transistor
Q1 is in cut-off state, is input to the VSN=0 of driving chip 20.After grid negative pressure VGL is output, at the first transistor Q1
In conducting state, now source electrode negative pressure VSN is exported from secondary signal output end, i.e., only after grid negative pressure VGL is output, source
Pole negative pressure VSN could be exported to driving chip 20, realized that grid negative pressure VGL is first exported and export after source electrode negative pressure VSN to driving core
The sequential of piece 20.
Second adjustment unit 42 includes transistor seconds Q2 and second resistance R2；Wherein, the transistor seconds Q2
Control pole be connected with the 3rd signal input part；First pole of transistor seconds Q2 passes through second resistance R2 and second crystal
The control pole connection of pipe Q2；Node and the 4th signal input part phase between first pole of transistor seconds Q2 and second resistance R2
Even；The control pole of transistor seconds Q2 is connected with the 3rd signal output part；Second pole of transistor seconds Q2 is defeated with the 4th signal
Go out end to be connected.
Wherein, the 3rd signal input part is connected with source electrode malleation VSP, the 4th signal input part and grid malleation
VGH is connected.
In the present embodiment, transistor seconds Q2 is P-channel enhancement type MOS transistor, and control extremely grid, first are extremely
Source electrode, second extremely drain, with cut-in voltage UGS(th), wherein, UGS(th)<0.Work as UGS<UGS(th)When, at transistor seconds Q2
In conducting state, you can become resistance area；Work as UGS>UGS(th)When, transistor seconds Q2 is in cut-off state.
When power supply chip 30 exports VGH, the grid voltage of transistor seconds Q2 is equal with source voltage, transistor seconds
In cut-off state, the VGH=0 of driving chip 20 is input to, when source electrode malleation VSP is output, transistor seconds Q2 is in
Conducting state, now grid malleation VGH exported from the 4th signal output part, i.e., only after source electrode malleation VSP is output, grid
Malleation VGH can just be exported to driving chip 20, realize that source electrode malleation VSP is first exported and export after grid malleation VGH to driving core
The sequential of piece 20.
Second time sequence adjusting circuit 50 is used for according to the first control signal GPIO of driving chip 20 and the first power supply electricity
Pressure VCC1 generates the second control signal EN.
In the present embodiment, the driving chip 20 produces the first control signal according to second source voltage VCC2, described
First control signal is universal input/output interface (General-Purpose Input/Output Ports, GPIO) signal.
Fig. 6 shows the circuit diagram of the second time sequence adjusting circuit of display device according to embodiments of the present invention.Such as Fig. 6 institutes
Show, second time sequence adjusting circuit 50 includes third transistor Q3 and 3rd resistor R3, wherein, the third transistor Q3's
Control pole is connected with the first control signal GPIO；First pole of third transistor Q3 passes through 3rd resistor R3 and the described 3rd
The control pole connection of transistor Q3；Node and second source voltage between first pole of third transistor Q3 and 3rd resistor R3
VCC2 signals are connected；Second pole of third transistor Q3 is connected with power supply chip 30, for exporting the second control signal EN.Its
In, the second control signal EN is used to make power supply chip 30 work and produce first group of clock signal.
In the present embodiment, third transistor Q3 is P-channel enhancement type MOS transistor, and control extremely grid, first are extremely
Source electrode, second extremely drain, with cut-in voltage UGS(th), wherein, UGS(th)<0.Work as UGS<UGS(th)When, at third transistor Q3
In conducting state, you can become resistance area；Work as UGS>UGS(th)When, third transistor Q3 is in cut-off state.
After first supply voltage VCC1 is supplied to driving chip 20, driving chip 20 proceeds by initialization, has initialized
GPIO signals are exported by GPIO interface into rear.When second source voltage VCC2 is provided, the grid electricity of third transistor Q3
Pressure is equal with source voltage, and third transistor Q3 is in cut-off state, the VGH=0 of driving chip 20 is input to, when source electrode malleation
When VSP is output, third transistor Q3 is in the conduction state, and now second source voltage VCC2 is provided to power supply chip 30 and makes
Power supply chip 30 is started working.I.e. only after the completion of the initialization of driving chip 20, power supply chip 30 just starts normal work, real
Existing first supply voltage VCC1 is first supplied to driving chip 20 to be initialized, second source voltage VCC2 quilts after the completion of initialization
Being supplied to power supply chip 30 makes power supply chip 30 start the sequential of normal work.
Display device provided in an embodiment of the present invention, power supply chip is provided by the first time sequence adjusting circuit first group
Clock signal be converted into driving chip needed for second group of clock signal, solve power supply chip offer sequential and driving chip
Required sequential mismatches the problem that caused liquid crystal display device can not normally show.The second time sequence adjusting circuit is utilized simultaneously
Driving chip is completed power supply chip normal work after initialization, supply voltage is provided to driving chip, make display normal, steady
It is fixed, improve the reliability of display device.
According to embodiments of the invention as described above, these embodiments do not have all of details of detailed descriptionthe, not yet
It is only described specific embodiment to limit the invention.Obviously, as described above, can make many modifications and variations.This explanation
Book is chosen and specifically describes these embodiments, is in order to preferably explain principle of the invention and practical application, so that affiliated
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.Protection model of the invention
The scope that enclosing should be defined by the claims in the present invention is defined.
Claims (10)
1. a kind of display device, it is characterised in that including：
Display panel；
Power supply chip, is connected with the display panel, for providing supply voltage for the display panel, and produces first group
Clock signal；
Driving chip, is connected with the display panel, for producing gain selection signals and GTG according to second group of clock signal
Signal is driving the display panel display image；
First time sequence adjusting circuit, is connected between the driving chip and power supply chip, for first group of clock signal to be turned
It is changed to second group of clock signal.
2. display device according to claim 1, it is characterised in that the display panel has a plurality of grid intersected with each other
Polar curve and a plurality of data lines and multiple pixels of the infall formation in the gate line and the data wire；And
The supply voltage includes grid voltage and source voltage.
3. display device according to claim 2, it is characterised in that the driving chip includes：
Time schedule controller, for providing second group of clock signal and display data signal；
Gate drivers, for producing gain selection signals according to the grid voltage and being applied to the gain selection signals
The gate line；
Source electrode driver, for producing gray scale voltage corresponding with the display data signal according to the source voltage, and will
The gray scale voltage is applied to the data wire.
4. display device according to claim 3, it is characterised in that first group of clock signal includes the 3rd sequential letter
Number and the 4th clock signal, second group of clock signal include the 5th clock signal and the 6th clock signal.
5. display device according to claim 4, it is characterised in that first time sequence adjusting circuit includes：
First sequential adjustment unit, for the 3rd clock signal to be converted into the 5th clock signal；
Second sequential adjustment unit, for the 4th clock signal to be converted into the 6th clock signal；
Wherein, the 3rd clock signal is provided for power supply chip grid negative pressure and the clock signal of source electrode negative pressure；
Grid malleation and the clock signal of source electrode malleation that 4th clock signal is provided for power supply chip；
Grid negative pressure and the clock signal of source electrode negative pressure that 5th clock signal is provided for driving chip；
Grid malleation and the clock signal of source electrode malleation that 6th clock signal is provided for driving chip.
6. display device according to claim 5, it is characterised in that the first sequential adjustment unit includes first crystal
Pipe and first resistor,
Wherein, the control pole of the first transistor is connected with the first signal input part；The first of the first transistor is extremely led to
First resistor is crossed to be connected with earth terminal；Second pole of the first transistor is connected with secondary signal input；
The control pole of the first transistor is connected with the first signal output part；
Node between first pole of the first transistor and first resistor is connected with secondary signal output end；
First signal input part is connected with grid negative pressure；The secondary signal input is connected with source electrode negative pressure.
7. display device according to claim 5, it is characterised in that second adjustment unit include transistor seconds and
Second resistance；
Wherein, the control pole of the transistor seconds is connected with the 3rd signal input part；The first of the transistor seconds is extremely led to
Second resistance is crossed to be connected with the control pole of the transistor seconds；Between first pole of the transistor seconds and second resistance
Node is connected with the 4th signal input part；
The control pole of the transistor seconds is connected with the 3rd signal output part；
Second pole of the transistor seconds is connected with the 4th signal output part；
3rd signal input part is connected with source electrode malleation, and the 4th signal input part is connected with grid malleation.
8. the display device according to claim any one of 1-7, it is characterised in that also including the second time sequence adjusting circuit,
The second control signal is generated for the first control signal according to driving chip and the first supply voltage, wherein, described second
Control signal is used to make power supply chip work and produce first group of clock signal.
9. display device according to claim 8, it is characterised in that the driving chip is produced according to second source voltage
First control signal, wherein, first control signal is universal input/output interface signal.
10. display device according to claim 9, it is characterised in that second time sequence adjusting circuit includes that the 3rd is brilliant
Body pipe and 3rd resistor,
Wherein, the control pole of the third transistor is connected with first control signal；First pole of the third transistor
It is connected with the control pole of the third transistor by 3rd resistor；Between first pole of the third transistor and 3rd resistor
Node be connected with second source voltage signal；
Second pole of the third transistor is connected with power supply chip, for exporting the second control signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710121270.1A CN106847215B (en) | 2017-03-02 | 2017-03-02 | Display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710121270.1A CN106847215B (en) | 2017-03-02 | 2017-03-02 | Display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106847215A true CN106847215A (en) | 2017-06-13 |
| CN106847215B CN106847215B (en) | 2019-07-26 |
Family
ID=59138826
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710121270.1A Active CN106847215B (en) | 2017-03-02 | 2017-03-02 | Display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106847215B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108172178A (en) * | 2017-12-13 | 2018-06-15 | 深圳市华星光电技术有限公司 | Power supply circuit, the liquid crystal display device of sequence controller |
| CN108389555A (en) * | 2018-02-06 | 2018-08-10 | 昆山龙腾光电有限公司 | Driving circuit and display device |
| CN109192177A (en) * | 2018-11-14 | 2019-01-11 | 维沃移动通信有限公司 | A kind of control circuit, liquid crystal driving mould group and liquid crystal display device |
| WO2019011064A1 (en) * | 2017-07-13 | 2019-01-17 | 昆山国显光电有限公司 | Method and apparatus for controlling power source of display screen, and storage medium and electronic device |
| CN110544452A (en) * | 2018-05-28 | 2019-12-06 | 京东方科技集团股份有限公司 | power supply time sequence control circuit and control method, display driving circuit and display device |
| CN115019740A (en) * | 2022-04-19 | 2022-09-06 | 京东方科技集团股份有限公司 | Sequential control circuit, display module and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1912974A (en) * | 2005-08-11 | 2007-02-14 | Lg.菲利浦Lcd株式会社 | Light emitting display |
| CN103474018A (en) * | 2013-08-19 | 2013-12-25 | 矽创电子股份有限公司 | Power supply circuit of display device |
| CN104123922A (en) * | 2014-07-21 | 2014-10-29 | 昆山龙腾光电有限公司 | Grid driving circuit and driving system and display device utilizing grid driving circuit |
| EP2983167A1 (en) * | 2014-08-08 | 2016-02-10 | Thales | Lcd display with line addressing by sampling and conversion, and display method |
| CN106023935A (en) * | 2016-07-27 | 2016-10-12 | 深圳市华星光电技术有限公司 | Liquid crystal display device and driving method thereof |
-
2017
- 2017-03-02 CN CN201710121270.1A patent/CN106847215B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1912974A (en) * | 2005-08-11 | 2007-02-14 | Lg.菲利浦Lcd株式会社 | Light emitting display |
| CN103474018A (en) * | 2013-08-19 | 2013-12-25 | 矽创电子股份有限公司 | Power supply circuit of display device |
| CN104123922A (en) * | 2014-07-21 | 2014-10-29 | 昆山龙腾光电有限公司 | Grid driving circuit and driving system and display device utilizing grid driving circuit |
| EP2983167A1 (en) * | 2014-08-08 | 2016-02-10 | Thales | Lcd display with line addressing by sampling and conversion, and display method |
| CN106023935A (en) * | 2016-07-27 | 2016-10-12 | 深圳市华星光电技术有限公司 | Liquid crystal display device and driving method thereof |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019011064A1 (en) * | 2017-07-13 | 2019-01-17 | 昆山国显光电有限公司 | Method and apparatus for controlling power source of display screen, and storage medium and electronic device |
| CN109256075A (en) * | 2017-07-13 | 2019-01-22 | 昆山国显光电有限公司 | Display screen power control method, device, storage medium and electronic equipment |
| JP2020503567A (en) * | 2017-07-13 | 2020-01-30 | クンシャン ゴー−ビシオノクス オプト−エレクトロニクス カンパニー リミテッドＫｕｎｓｈａｎ Ｇｏ−Ｖｉｓｉｏｎｏｘ Ｏｐｔｏ−Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．， Ｌｔｄ． | Display power control method, apparatus, recording medium, and electronic device |
| JP7030817B2 (en) | 2017-07-13 | 2022-03-07 | クンシャン ゴー－ビシオノクス オプト－エレクトロニクス カンパニー リミテッド | Display power control methods, devices, recording media and electronic devices |
| US11282908B2 (en) | 2017-07-13 | 2022-03-22 | Kunshan Go-Visionox Opto-Electronics Co., Ltd. | Control methods and control devices for display power supply |
| CN108172178A (en) * | 2017-12-13 | 2018-06-15 | 深圳市华星光电技术有限公司 | Power supply circuit, the liquid crystal display device of sequence controller |
| CN108389555A (en) * | 2018-02-06 | 2018-08-10 | 昆山龙腾光电有限公司 | Driving circuit and display device |
| CN110544452A (en) * | 2018-05-28 | 2019-12-06 | 京东方科技集团股份有限公司 | power supply time sequence control circuit and control method, display driving circuit and display device |
| CN109192177A (en) * | 2018-11-14 | 2019-01-11 | 维沃移动通信有限公司 | A kind of control circuit, liquid crystal driving mould group and liquid crystal display device |
| CN109192177B (en) * | 2018-11-14 | 2023-03-17 | 维沃移动通信有限公司 | Control circuit, liquid crystal display driving module and liquid crystal display device |
| CN115019740A (en) * | 2022-04-19 | 2022-09-06 | 京东方科技集团股份有限公司 | Sequential control circuit, display module and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106847215B (en) | 2019-07-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106847215B (en) | Display device | |
| CN107958656B (en) | GOA circuit | |
| CN107464517A (en) | Driving method, drive device, display panel and the display device of display panel | |
| CN100478750C (en) | Apparatus and method for driving a liquid crystal display | |
| CN106228942B (en) | Gate driving circuit for liquid crystal display | |
| CN106504720A (en) | Shift register cell and its driving method, gate drive apparatus and display device | |
| CN107633832A (en) | Liquid crystal display device and its driving method | |
| KR20080111233A (en) | Driving apparatus for liquid crystal display and liquid crystal display including the same | |
| CN105047155B (en) | Liquid crystal display device and its GOA scanning circuits | |
| CN100468133C (en) | Active matrix type liquid crystal display device | |
| CN101236738B (en) | LCD device repairing line operation amplification circuit and its drive method | |
| CN105513552A (en) | Driving circuit, driving method and display device | |
| CN102598108B (en) | Pixel circuit and display device | |
| CN107610666A (en) | Eliminate the circuit and method of power-off ghost shadow | |
| CN102770898B (en) | Source driver circuit of liquid crystal display device | |
| TW201003627A (en) | Discharge circuit and display device with the same | |
| CN108665865A (en) | Drive element of the grid and display device | |
| CN104269151A (en) | Gate drive circuit capable of achieving signal bidirectional transmission | |
| CN103412427A (en) | Liquid crystal display panel | |
| CN101882430B (en) | Method for driving liquid crystal display device | |
| CN106251821A (en) | Gate driver circuit | |
| CN101556776B (en) | Driving circuit for realizing rapid discharge of pixel thin film transistor | |
| CN107274851A (en) | display panel and its driving method and display device | |
| CN108615510A (en) | A kind of top rake circuit and control method | |
| CN103105712B (en) | Display module and liquid crystal display |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee after: InfoVision Optoelectronics(Kunshan)Co.,Ltd. Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee before: INFOVISION OPTOELECTRONICS (KUNSHAN) Co.,Ltd. |
|
| CP01 | Change in the name or title of a patent holder |