CN103699026A - Control device and method for realizing multi-source power-on timing sequence and power-down timing sequence - Google Patents
Control device and method for realizing multi-source power-on timing sequence and power-down timing sequence Download PDFInfo
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Abstract
The invention discloses a control device and a control method for realizing a multi-source power-on timing sequence and a multi-source power-down timing sequence, relating to the field of power supply control. The device comprises a power supply, wherein the anode of the power supply is connected with the input end of a power conversion chip, and the cathode of the power supply is grounded; the power conversion chip is respectively connected with a second divider resistor R2 and the inverted input end of a comparator U1 through a first divider resistor R1, and the other end of the second divider resistor R2 is grounded; the power conversion chip is respectively connected with a fourth divider resistor R4 and the in-phase input end of the comparator U1 through a third divider resistor R3, and the other end of the third divider resistor R3 is connected with a GND; the comparator U1 is connected with the input interface of a programmable logic device; the three output ports of the programmable logic device are respectively connected with a first enabling pin, a second enabling pin and a third enabling pin. According to the control device and the control method, the power-on timing sequence, the power-down timing sequence, a power-on time interval and a power-down time interval can be precisely controlled to meet the requirements of a user, and the working quality is better.
Description
Technical field
The present invention relates to the power supply control field of high speed optical communication interiors of products, be specifically related to a kind of control device and method that realizes many power supplys power-on and power-off sequential.
Background technology
Along with social progress, optical communication product high speed development, optical communication product is at a high speed had relatively high expectations to power supply, and optical communication product not only requires electrifying timing sequence and lower electric sequential, and the time having powered on has all been proposed to accurate requirement.After optical communication product powers on, once the general supply of optical communication product disappears, the control chip of optical communication product just cannot be worked, and then cannot play the effect of controlling electricity under optical communication product; Therefore, the lower electric sequential control of optical communication product belongs to a larger difficult point.
At present, the power management chip occurring on the market can be controlled the electrifying timing sequence of optical communication product, and still, power management chip exists following defect while using:
(1) the lower electric sequential of the uncontrollable optical communication product of power management chip, when power management chip is controlled a plurality of device of optical communication interiors of products, controllable power-on time interval and the lower electricity time interval can only be set to second this order of magnitude, for example 2 seconds, this time is larger comparatively speaking, degree of accuracy is lower, and power management chip has been difficult to meet the demand of the optical communication product of high speed development.
(2) electrifying timing sequence of power management chip and the lower electricity time interval are fixed, user cannot adjust power-on time interval and the lower electricity time interval of optical communication interiors of products device according to the actual requirements, the time interval of the time interval that power management chip can be managed and the actual demand of optical communication interiors of products device is not inconsistent, and at this moment just can not adopt power management chip.
Summary of the invention
For the defect existing in prior art, the object of the present invention is to provide a kind of control device and method that realizes many power supply electrifyings sequential and lower electric sequential, not only can accurately control electrifying timing sequence and the lower electric sequential of optical communication product, and can control accurately power-on time interval and the lower some time interval, the demand that meets user, work quality is better.
For reaching above object, the technical scheme that the present invention takes is: a kind of control device of realizing many power supply electrifyings sequential and lower electric sequential, comprises power supply, power conversion chip, comparer U1, programmable logic device (PLD), the first divider resistance R1, the second divider resistance R2, the 3rd divider resistance R3 and the 4th divider resistance R4, capacitor C 1, the first pull down resistor R5, the second pull down resistor R6, the 3rd pull down resistor R7, the first power supply chip, second source chip and the 3rd power supply chip; Comparer U1 comprises positive power pin and negative power pin; Programmable logic device (PLD) comprises power end, input interface, the first output interface, the second output interface, the 3rd output interface and earth terminal;
The positive pole of described power supply is connected with the input end of power conversion chip, the minus earth of power supply; The output terminal of described power conversion chip is connected with the inverting input of the second divider resistance R2, comparer U1 respectively by the first divider resistance R1, and the second divider resistance R2 is away from one end ground connection of comparer U1; The input end of described power conversion chip is connected with the in-phase input end of the 4th divider resistance R4, comparer U1 respectively by the 3rd divider resistance R3, and the 4th divider resistance R4 is away from one end ground connection of comparer U1;
The positive power pin of described comparer U1 is connected with the output terminal of power conversion chip, and the positive power pin of comparer U1 is passed through capacitor C 1 ground connection, the negative power pin ground connection of comparer U1, and the output terminal of comparer U1 is connected with the input interface of programmable logic device (PLD); The first output interface of programmable logic device (PLD) is connected with the first enable pin of the first power supply chip, and the first enable pin is by the first pull down resistor R5 ground connection; The second output interface of programmable logic device (PLD) is connected with the second enable pin of second source chip, and the second enable pin is by the second pull down resistor R6 ground connection; The 3rd output interface of programmable logic device (PLD) is connected with the 3rd enable pin of the 3rd power supply chip, and the 3rd enable pin is by the 3rd pull down resistor R7 ground connection; The power end of programmable logic device (PLD) is connected with the output terminal of power conversion chip, the earth terminal ground connection of programmable logic device (PLD).
On the basis of technique scheme, the resistance of described the first divider resistance R1 is 10k Ω, and the resistance of the second divider resistance R2 is 30.1k Ω, and the resistance of the 3rd divider resistance R3 is 30.1k Ω, and the resistance of the 4th divider resistance R4 is 10k Ω.
On the basis of technique scheme, the capacity of described capacitor C 1 is 0.1 μ F.
On the basis of technique scheme, the resistance of described the first pull down resistor R5 is 10k Ω or 4.75k Ω, and the resistance of the second pull down resistor R6 is 10k Ω or 4.75k Ω, and the resistance of the 3rd pull down resistor R7 is 10k Ω or 4.75k Ω.
A control method that realizes many power supply electrifyings sequential and lower electric sequential for said apparatus, is characterized in that, comprises the following steps:
A, power supply transfer to the input end input supply voltage of power conversion chip, and power conversion chip is converted into output voltage by supply voltage; Output voltage, by the first divider resistance R1 and the second divider resistance R2 dividing potential drop, produces the inverting input that reverse inter-input-ing voltage inputs to comparer U1; Supply voltage, by the 3rd divider resistance R3 and the 4th divider resistance R4 dividing potential drop, produces the in-phase input end that homophase input voltage inputs to comparer U1;
The output terminal output indicator signal of B, comparer U1 is to the input interface of programmable logic device (PLD); According to programmable logic device (PLD) default first, power on and power on interval time, second interval time, first time electric interval time and second time electric interval time;
The level of C, monitoring indicator signal, if the level of indicator signal is more than 2V, programmable logic device (PLD) is exported three level to the first enable pin, the second enable pin and the 3rd enable pins more than 2V successively, be first to power on interval time the interval time between the first enable pin and the second enable pin, and be second to power on interval time the interval time between the second enable pin and the 3rd enable pin; If the level of indicator signal is below 0.8V, programmable logic device (PLD) is exported three level to the first enable pin, the second enable pin and the 3rd enable pins below 0.8V successively, be first time electric interval time the interval time between the first enable pin and the second enable pin, and be second time electric interval time the interval time between the second enable pin and the 3rd enable pin.
On the basis of technique scheme, supply voltage described in steps A is 11.4V～12.6V, and the output voltage of described power conversion chip is 3.15V～3.45V.
On the basis of technique scheme, supply voltage described in steps A is 12V, and the output voltage of described power conversion chip is 3.3V.
On the basis of technique scheme, be 10 milliseconds or 20 milliseconds described first interval time that powers on, and be 1 millisecond described second interval time that powers on.
On the basis of technique scheme, be 20 nanoseconds described first time electric interval time, and be 20 nanoseconds described second time electric interval time.
Compared with prior art, the invention has the advantages that:
(1) when the present invention uses, after DC-DC power down, the output voltage V CC of DC-DC can also keep one end time, and then CPLD can be worked on a period of time.Even if externally fed suddenly disappears, CPLD still can, according to first time electric interval time and second time electric interval time, control electricity under the first enable pin EN1, the second enable pin EN2 and the 3rd enable pin EN3.Therefore, the present invention can pass through DC-DC, comparer and CPLD control electrifying timing sequence and lower electric sequential.
(2) when the present invention uses, operating personnel can adopt CPLD programming to set power-on time interval and the lower electricity time interval, compare at more than 2 seconds power supply chips with power-on time interval in prior art and the lower electricity time interval, it is much flexible that the present invention wants, the present invention can be according to actual product need free setting power-on time interval and the lower electricity time interval, time interval maximum can establish how many, ability by CPLD counter determines, the time interval, I established how many, and decide in other words by the clock period for the crystal oscillator being used by designer.CPLD can be accurate to power-on time interval and the lower electricity time interval millisecond, delicate or nanosecond rank, and degree of accuracy is higher, not only can meet the demand of the optical communication product of high speed development, and the present invention easily realizes, and not only cost is lower, and work quality is better.
(3) when the present invention uses, only need to use the 12V supply voltage of high speed optical communication product motherboard, can use by the device inside on the various system boards of optical communication product, the scope of application is more extensive.
Accompanying drawing explanation
Fig. 1 realizes the structural representation of the control device of many power supply electrifyings sequential and lower electric sequential in the embodiment of the present invention;
Fig. 2 is input supply voltage V1, output voltage V CC in the embodiment of the present invention, homophase input voltage V+, reverse inter-input-ing voltage V-, DROP signal level VDROP and the variation diagram of time;
Fig. 3 is that the voltage of input supply voltage V1, output voltage V CC in the embodiment of the present invention, the first power supply chip output terminal out1, the voltage of the voltage of second source chip output out2, the 3rd power supply chip output terminal out3 are schemed over time.
In figure: comparer-U1, the first divider resistance-R1, the second divider resistance-R2, three divider resistance-R3, four divider resistance-R4, electric capacity-C1, the first pull down resistor-R5, the second pull down resistor-R6, three pull down resistor-R7.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.
Shown in Figure 1, the control device of realizing many power supply electrifyings sequential and lower electric sequential in the embodiment of the present invention, comprises power supply, power conversion chip (DC-DC), comparer U1, programmable logic device (PLD) (CPLD), the first divider resistance R1, the second divider resistance R2, the 3rd divider resistance R3 and the 4th divider resistance R4, capacitor C 1, the first pull down resistor R5, the second pull down resistor R6, the 3rd pull down resistor R7, the first power supply chip, second source chip and the 3rd power supply chip.
Comparer U1 comprises positive power pin and negative power pin; CPLD comprises power end VDD, input interface IO, the first output interface IO1, the second output interface IO2, the 3rd output interface IO3 and earth terminal GND.
The positive pole of power supply is connected with the input end Vin of DC-DC, the minus earth of power supply.The output end vo ut of DC-DC is connected with the inverting input U-of the second divider resistance R2, comparer U1 respectively by the first divider resistance R1, and the second divider resistance R2 is away from one end ground connection of comparer U1; The input end Vin of DC-DC is connected with the in-phase input end U+ of the 4th divider resistance R4, comparer U1 respectively by the 3rd divider resistance R3, and the 4th divider resistance R4 is away from one end ground connection of comparer U1.
The positive power pin of comparer U1 is connected with the output terminal of DC-DC, and comparer U1 powers by DC-DC.The positive power pin of comparer U1 is by capacitor C 1 ground connection, the negative power pin ground connection of comparer U1.The output terminal of comparer U1 is connected with the input interface IO of CPLD.
The first output interface IO1 of CPLD is connected with the enable pin EN1 of the first power supply chip, and the first enable pin EN1 is by the first pull down resistor R5 ground connection, and the output terminal out1 of the first power supply chip is connected with the internal components of optical communication product.
The second output interface IO2 of CPLD is connected with the enable pin EN2 of second source chip, and the second enable pin EN2 is by the second pull down resistor R6 ground connection, second source chip output terminal out2 be connected with the internal components of optical communication product.
The 3rd output interface IO3 of CPLD is connected with the enable pin EN3 of the 3rd power supply chip, and the 3rd enable pin EN3 is by the 3rd pull down resistor R7 ground connection, and the output terminal out3 of the 3rd power supply chip is connected with the internal components of optical communication product.
The power end VDD of CPLD is connected with the output end vo ut of DC-DC, the earth terminal GND ground connection of CPLD.
In the embodiment of the present invention, the resistance of the first divider resistance R1 is 10k Ω, the resistance of the second divider resistance R2 is 30.1k Ω, the resistance of the 3rd divider resistance R3 is 30.1k Ω, the resistance of the 4th divider resistance R4 is 10k Ω, and the capacity of capacitor C 1 is 0.1 μ F, and the resistance of the first pull down resistor R5 is 10k Ω or 4.75k Ω, the resistance of the second pull down resistor R6 is 10k Ω or 4.75k Ω, and the resistance of the 3rd pull down resistor R7 is 10k Ω or 4.75k Ω.
The control method that realizes many power supply electrifyings sequential and lower electric sequential in the embodiment of the present invention is as follows:
S1: power supply transfers to the input end Vin input supply voltage V1 of DC-DC, and DC-DC is converted into output voltage V CC by supply voltage V1.
S2: output voltage V CC, by the first divider resistance R1 and the second divider resistance R2 dividing potential drop, produces the inverting input U-that reverse inter-input-ing voltage V-inputs to comparer U1; Supply voltage V1, by the 3rd divider resistance R3 and the 4th divider resistance R4 dividing potential drop, produces the in-phase input end U+ that homophase input voltage V+ inputs to comparer U1.
S3: the output terminal output indicator signal (DROP signal) of comparer U1 is to the input interface IO of CPLD.
S4: the programmable logic device (PLD) of using according to reality is programmed, default first powers on powers on interval time, first time electric interval time and second time electric interval time interval time, second.
S5: the level of monitoring DROP signal, if the level of DROP signal, more than 2V, forwards step S6 to; If the level of DROP signal, below 0.8V, forwards step S7 to.
S6:CPLD exports three level to the first enable pin EN1, the second enable pin EN2 and the 3rd enable pin EN3 more than 2V successively, be first to power on interval time the interval time between the first enable pin EN1 and the second enable pin EN2, and be second to power on interval time the interval time between the second enable pin EN2 and the 3rd enable pin EN3.
S7:CPLD exports three level to the first enable pin EN1, the second enable pin EN2 and the 3rd enable pin EN3 below 0.8V successively, be first time electric interval time the interval time between the first enable pin EN1 and the second enable pin EN2, and be second time electric interval time the interval time between the second enable pin EN2 and the 3rd enable pin EN3.
The principle of work of control method that realizes many power supply electrifyings sequential and lower electric sequential in the embodiment of the present invention is as follows:
Power supply is (being after DC-DC powers on) after DC-DC input supply voltage V1, because supply voltage V1 is greater than the output voltage V CC of DC-DC, the first divider resistance R1 of pressure-dividing output voltage VCC, the second divider resistance R2, the 3rd divider resistance R3 with dividing voltage supply voltage V1, the distributing position of the 4th divider resistance R4 is different, so the homophase input voltage V+ of comparer U1 is greater than reverse inter-input-ing voltage V-, the output terminal of comparer U1 is high level to the level of CPLD output, CPLD can export three high level to the first enable pin EN1 successively, the second enable pin EN2 and the 3rd enable pin EN3.
When power supply is no longer powered for DC-DC, the supply voltage V1 of the input end Vin of DC-DC starts to decline (being that general supply starts power down), and the homophase input voltage V+ of comparer U1 starts to decline.Because the output voltage V CC of DC-DC is that supply voltage V1 changes generation by DC-DC, therefore after supply voltage V1 power down, output voltage V CC still can keep a period of time, and then makes the reverse inter-input-ing voltage V-that output voltage V CC dividing potential drop produces keep a period of time; After the supply voltage V1 of DC-DC drops to a certain degree, output voltage V CC just can start to decline, and then makes reverse inter-input-ing voltage V-start to decline.
In the process of the voltage drop of the input end Vin of DC-DC, when the homophase input voltage V+ of comparer U1 is greater than reverse inter-input-ing voltage V-, the level that comparer U1 exports the DROP signal of CPLD to (belongs to high level) more than 2V; When the homophase input voltage V+ of comparer U1 is less than reverse inter-input-ing voltage V-, the level that comparer U1 exports the DROP signal of CPLD to (belongs to low level) below 0.8V, and comparer U1 output low level is to CPLD.
CPLD receives when the level of DROP signal is low level, and CPLD inputs 3 low level to the first enable pin EN1, the second enable pin EN2 and the 3rd enable pin EN3 successively.After supply voltage V1 power down, the output voltage V CC of DC-DC can keep a period of time, and then CPLD can be worked on a period of time.Therefore,, even if general supply suddenly disappears, CPLD still can be according to controlling first time electric interval time and second time electric interval time electricity under the first enable pin EN1, the second enable pin EN2 and the 3rd enable pin EN3.
In actual applications, supply voltage V1 is 11.4V～12.6V, and the output voltage V CC of DC-DC is 3.15V～3.45V, and first powers on powers on arrange according to the actual requirements interval time, first time electric interval time and second time electric interval time interval time, second.
After supply voltage V1 power down, the time shorter (generally in several milliseconds) that the output voltage V CC of DC-DC can keep disappears, if output voltage V CC power down, CPLD, with regard to electricity under uncontrollable the first enable pin EN1 and the second enable pin EN2, therefore need arrange shorter being advisable first time electric interval time between the first enable pin EN1 and the second enable pin EN2.Because the 3rd enable pin EN3 is electricity under last, so control electricity under the 3rd enable pin EN3 even without CPLD, after DC-DC power down, the 3rd enable pin EN3 also can be lower electric voluntarily.Therefore, therefore second time electric time interval between the second enable pin EN2 and the 3rd enable pin EN3 do not have the strict requirement that arranges; If require the 3rd enable pin EN3 lower electricity in sometime in practical application, programming personnel can be on CPLD second time electric time interval of programming Control voluntarily.
Supply voltage V1 in the embodiment of the present invention is 12V, and output voltage V CC is 3.3V, and be 10 milliseconds or 20 milliseconds first interval time that powers on, and be 1 millisecond second interval time that powers on, and be 20 nanoseconds first time electric interval time, and be 20 nanoseconds second time electric interval time.
Below, by 1 embodiment, describe principle of work of the present invention in detail.
Shown in Fig. 1, Fig. 2, power supply transfers to the supply voltage V1 of the input end Vin input 12V of DC-DC, and DC-DC is converted into supply voltage V1 the output voltage V CC of 3.3V.Output voltage V CC is by the first divider resistance R1 and the second divider resistance R2 dividing potential drop, and the reverse inter-input-ing voltage V-that produces 2.4V inputs to the inverting input U-of comparer U1; Supply voltage V1 is by the 3rd divider resistance R3 and the 4th divider resistance R4 dividing potential drop, and the homophase input voltage V+ that produces 2.8V inputs to the in-phase input end U+ of comparer U1.When homophase input voltage V+ is greater than reverse inter-input-ing voltage V-, the DROP signal that comparer U1 output level is 3.3V is to the input interface IO of CPLD.When homophase input voltage V+ is less than reverse inter-input-ing voltage V-, comparer U1 output is less than the DROP signal of 0.8V to the input interface IO of CPLD.By CPLD, programme, be 10 milliseconds default first interval time that powers on, and be 1 millisecond second interval time that powers on, and be 20 nanoseconds first time electric interval time, and be 20 nanoseconds second time electric interval time.
The level of monitoring DROP signal, shown in Fig. 2, Fig. 3, after DC-DC powers on, the homophase input voltage V+ of comparer U1 is greater than reverse inter-input-ing voltage V-all the time, comparer U1 exports the level of DROP signal of CPLD in about 3.3V, and CPLD exports three high level to the first enable pin EN1, the second enable pin EN2 and the 3rd enable pin EN3 successively; Be 10 milliseconds the interval time between the first enable pin EN1 and the second enable pin EN2, and be 1 millisecond the interval time between the second enable pin EN2 and the 3rd enable pin EN3.
When general supply voltage V1 drops to 10V when following, the reverse inter-input-ing voltage V-of comparer U1 is greater than homophase input voltage V+, and the level that comparer U1 exports the DROP signal of CPLD to is less than 0.8V(and belongs to low level), comparer U1 output low level is to CPLD.
Shown in Figure 3, CPLD receives when the level of DROP signal is low level, CPLD exports 3 low level to the first enable pin EN1, the second enable pin EN2 and the 3rd enable pin EN3 successively, CPLD controls the output terminal out1 of the first power supply chip successively, the output terminal out3 of the output terminal out2 of second source chip and the 3rd power supply chip.Shown in Figure 2, after the supply voltage V1 of the input end Vin of DC-DC declines, the output voltage V CC of DC-DC just starts greatly to decline after 5 milliseconds, and output voltage V CC drops to inoperable threshold voltage and may also have 2 milliseconds of left and right from starting to drop to.Therefore, CPLD can also work on 7 milliseconds, shown in Figure 3, CPLD can be by controlling electricity under the first enable pin EN1, the second enable pin EN2 and the 3rd enable pin EN3, and then the output terminal out1 of control the first power supply chip, the output terminal out3 of the output terminal out2 of second source chip and the 3rd power supply chip, the output terminal out1 of the first power supply chip, the lower electricity time interval between the output terminal out3 of the output terminal out2 of second source chip and the 3rd power supply chip is also determined by the characteristic of power supply chip, specifically with actual measurement, is as the criterion.Shown in Figure 3, under the output terminal out1 of the first power supply chip, under the output terminal out2 of electricity and second source chip, the time interval between electricity is approximately 20 microseconds, and under the output terminal out2 of second source chip, under the output terminal out3 of electricity and the 3rd power supply chip, the time interval between electricity is approximately 1 millisecond.
The present invention is not limited to above-mentioned embodiment, for those skilled in the art, under the premise without departing from the principles of the invention, can also make some improvements and modifications, within these improvements and modifications are also considered as protection scope of the present invention.The content not being described in detail in this instructions belongs to the known prior art of professional and technical personnel in the field.
Claims (9)
1. a control device of realizing many power supply electrifyings sequential and lower electric sequential, is characterized in that: comprise power supply, power conversion chip, comparer U1, programmable logic device (PLD), the first divider resistance R1, the second divider resistance R2, the 3rd divider resistance R3 and the 4th divider resistance R4, capacitor C 1, the first pull down resistor R5, the second pull down resistor R6, the 3rd pull down resistor R7, the first power supply chip, second source chip and the 3rd power supply chip; Comparer U1 comprises positive power pin and negative power pin; Programmable logic device (PLD) comprises power end, input interface, the first output interface, the second output interface, the 3rd output interface and earth terminal;
The positive pole of described power supply is connected with the input end of power conversion chip, the minus earth of power supply; The output terminal of described power conversion chip is connected with the inverting input of the second divider resistance R2, comparer U1 respectively by the first divider resistance R1, and the second divider resistance R2 is away from one end ground connection of comparer U1; The input end of described power conversion chip is connected with the in-phase input end of the 4th divider resistance R4, comparer U1 respectively by the 3rd divider resistance R3, and the 4th divider resistance R4 is away from one end ground connection of comparer U1;
The positive power pin of described comparer U1 is connected with the output terminal of power conversion chip, and the positive power pin of comparer U1 is passed through capacitor C 1 ground connection, the negative power pin ground connection of comparer U1, and the output terminal of comparer U1 is connected with the input interface of programmable logic device (PLD); The first output interface of programmable logic device (PLD) is connected with the first enable pin of the first power supply chip, and the first enable pin is by the first pull down resistor R5 ground connection; The second output interface of programmable logic device (PLD) is connected with the second enable pin of second source chip, and the second enable pin is by the second pull down resistor R6 ground connection; The 3rd output interface of programmable logic device (PLD) is connected with the 3rd enable pin of the 3rd power supply chip, and the 3rd enable pin is by the 3rd pull down resistor R7 ground connection; The power end of programmable logic device (PLD) is connected with the output terminal of power conversion chip, the earth terminal ground connection of programmable logic device (PLD).
2. the control device of realizing many power supply electrifyings sequential and lower electric sequential as claimed in claim 1, it is characterized in that: the resistance of described the first divider resistance R1 is 10k Ω, the resistance of the second divider resistance R2 is 30.1k Ω, the resistance of the 3rd divider resistance R3 is 30.1k Ω, and the resistance of the 4th divider resistance R4 is 10k Ω.
3. the control device of realizing many power supply electrifyings sequential and lower electric sequential as claimed in claim 1, is characterized in that: the capacity of described capacitor C 1 is 0.1 μ F.
4. the control device of realizing many power supply electrifyings sequential and lower electric sequential as claimed in claim 1, it is characterized in that: the resistance of described the first pull down resistor R5 is 10k Ω or 4.75k Ω, the resistance of the second pull down resistor R6 is 10k Ω or 4.75k Ω, and the resistance of the 3rd pull down resistor R7 is 10k Ω or 4.75k Ω.
5. the control method that realizes many power supply electrifyings sequential and lower electric sequential based on installing described in claim 1 to 4 any one, is characterized in that, comprises the following steps:
A, power supply transfer to the input end input supply voltage of power conversion chip, and power conversion chip is converted into output voltage by supply voltage; Output voltage, by the first divider resistance R1 and the second divider resistance R2 dividing potential drop, produces the inverting input that reverse inter-input-ing voltage inputs to comparer U1; Supply voltage, by the 3rd divider resistance R3 and the 4th divider resistance R4 dividing potential drop, produces the in-phase input end that homophase input voltage inputs to comparer U1;
The output terminal output indicator signal of B, comparer U1 is to the input interface of programmable logic device (PLD); According to programmable logic device (PLD) default first, power on and power on interval time, second interval time, first time electric interval time and second time electric interval time;
The level of C, monitoring indicator signal, if the level of indicator signal is more than 2V, programmable logic device (PLD) is exported three level to the first enable pin, the second enable pin and the 3rd enable pins more than 2V successively, be first to power on interval time the interval time between the first enable pin and the second enable pin, and be second to power on interval time the interval time between the second enable pin and the 3rd enable pin; If the level of indicator signal is below 0.8V, programmable logic device (PLD) is exported three level to the first enable pin, the second enable pin and the 3rd enable pins below 0.8V successively, be first time electric interval time the interval time between the first enable pin and the second enable pin, and be second time electric interval time the interval time between the second enable pin and the 3rd enable pin.
6. the control method that realizes many power supply electrifyings sequential and lower electric sequential as claimed in claim 5, is characterized in that: supply voltage described in steps A is 11.4V～12.6V, and the output voltage of described power conversion chip is 3.15V～3.45V.
7. the control method that realizes many power supply electrifyings sequential and lower electric sequential as claimed in claim 6, is characterized in that: supply voltage described in steps A is 12V, and the output voltage of described power conversion chip is 3.3V.
8. the control method that realizes many power supply electrifyings sequential and lower electric sequential as described in claim 5 to 7 any one, is characterized in that: be 10 milliseconds or 20 milliseconds described first interval time that powers on, and be 1 millisecond described second interval time that powers on.
9. the control method that realizes many power supply electrifyings sequential and lower electric sequential as described in claim 5 to 7 any one, is characterized in that: be 20 nanoseconds described first time electric interval time, and be 20 nanoseconds described second time electric interval time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310727086.3A CN103699026B (en) | 2013-12-25 | 2013-12-25 | Realize control device and the method for many power supply electrifyings sequential and lower electric sequential |
Applications Claiming Priority (1)
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| CN201310727086.3A CN103699026B (en) | 2013-12-25 | 2013-12-25 | Realize control device and the method for many power supply electrifyings sequential and lower electric sequential |
Publications (2)
| Publication Number | Publication Date |
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| CN103699026A true CN103699026A (en) | 2014-04-02 |
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| CN105116777A (en) * | 2015-09-08 | 2015-12-02 | 上海航天测控通信研究所 | Security control time sequence processing system |
| CN105843136A (en) * | 2016-05-30 | 2016-08-10 | 南京国电南自美卓控制***有限公司 | Circuit for controlling power up-down sequence of multi-channel power supply of processor and control method |
| CN106990727A (en) * | 2017-03-13 | 2017-07-28 | 山东和远智能科技股份有限公司 | The control method and device of i.MX6 series processors electric sequences |
| CN107086644A (en) * | 2017-06-29 | 2017-08-22 | 中国联合网络通信集团有限公司 | Method of supplying power to and electric supply installation |
| CN107272809A (en) * | 2017-08-14 | 2017-10-20 | 迈普通信技术股份有限公司 | Automatic switch electric installation and system |
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| CN105116777A (en) * | 2015-09-08 | 2015-12-02 | 上海航天测控通信研究所 | Security control time sequence processing system |
| CN105116777B (en) * | 2015-09-08 | 2018-03-16 | 上海航天测控通信研究所 | One kind peace control sequential processing system |
| CN105843136A (en) * | 2016-05-30 | 2016-08-10 | 南京国电南自美卓控制***有限公司 | Circuit for controlling power up-down sequence of multi-channel power supply of processor and control method |
| CN106990727A (en) * | 2017-03-13 | 2017-07-28 | 山东和远智能科技股份有限公司 | The control method and device of i.MX6 series processors electric sequences |
| CN106990727B (en) * | 2017-03-13 | 2023-06-13 | 和远智能科技股份有限公司 | Method and device for controlling powering-on sequence of MX6 series processor |
| CN107086644A (en) * | 2017-06-29 | 2017-08-22 | 中国联合网络通信集团有限公司 | Method of supplying power to and electric supply installation |
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| CN107272809A (en) * | 2017-08-14 | 2017-10-20 | 迈普通信技术股份有限公司 | Automatic switch electric installation and system |
| CN109992030B (en) * | 2017-12-29 | 2021-08-24 | 中兴通讯股份有限公司 | Power-off time sequence circuit, power supply system and control method |
| CN109992030A (en) * | 2017-12-29 | 2019-07-09 | 中兴通讯股份有限公司 | A kind of lower electric sequence circuit, power-supply system and control method |
| CN107978275A (en) * | 2018-01-19 | 2018-05-01 | 昆山国显光电有限公司 | Control signal transmission circuit and method |
| CN108646173A (en) * | 2018-08-07 | 2018-10-12 | 郑州云海信息技术有限公司 | It is a kind of to solve the not dull method and system of VR timing sequence test PG signals |
| CN108646173B (en) * | 2018-08-07 | 2021-04-27 | 郑州云海信息技术有限公司 | Method and system for solving problem of monotonous PG signal in VR time sequence test |
| CN109188242A (en) * | 2018-08-29 | 2019-01-11 | 郑州云海信息技术有限公司 | A kind of time sequence test method, device and VR chip |
| CN109188242B (en) * | 2018-08-29 | 2021-08-31 | 郑州云海信息技术有限公司 | Time sequence testing method and device and VR chip |
| CN109617544A (en) * | 2018-12-04 | 2019-04-12 | 凌云光技术集团有限责任公司 | A kind of novel electrifying timing sequence control equipment, system and method |
| CN109617544B (en) * | 2018-12-04 | 2023-06-13 | 凌云光技术股份有限公司 | Power-on time sequence control equipment, system and method |
| CN111324052A (en) * | 2018-12-17 | 2020-06-23 | 北京华航无线电测量研究所 | Power supply power management device based on TTL level control |
| CN110737234A (en) * | 2019-10-21 | 2020-01-31 | 江苏云涌电子科技股份有限公司 | internal network safety monitoring device |
| CN111082801A (en) * | 2019-12-06 | 2020-04-28 | 杭州迪普科技股份有限公司 | Time sequence control system and electronic equipment |
| CN111082801B (en) * | 2019-12-06 | 2023-09-26 | 杭州迪普科技股份有限公司 | Time sequence control system and electronic equipment |
| CN111181161A (en) * | 2020-02-14 | 2020-05-19 | 成都泛美视界科技有限公司 | Power supply control system applied to flight simulator |
| CN111181161B (en) * | 2020-02-14 | 2021-07-06 | 成都泛美视界科技有限公司 | Power supply control system applied to flight simulator |
| CN111694607B (en) * | 2020-05-27 | 2023-08-29 | 上海移远通信技术股份有限公司 | Automatic starting circuit of communication module and communication module |
| CN111694607A (en) * | 2020-05-27 | 2020-09-22 | 上海移远通信技术股份有限公司 | Automatic starting circuit of communication module and communication module |
| CN114520581A (en) * | 2020-11-05 | 2022-05-20 | 中移物联网有限公司 | Power-on time sequence control method and control circuit of distributed power system |
| CN114995262A (en) * | 2022-08-05 | 2022-09-02 | 成都万创科技股份有限公司 | Power supply time sequence control method and system of X86 platform |
| CN117477917A (en) * | 2023-12-26 | 2024-01-30 | 钰泰半导体股份有限公司 | Control circuit with fixed output discharge time and multistage cascading power rail |
| CN117477917B (en) * | 2023-12-26 | 2024-02-23 | 钰泰半导体股份有限公司 | Control circuit with fixed output discharge time and multistage cascading power rail |
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