CN107960139B - 各向异性导电膜和连接结构体 - Google Patents

各向异性导电膜和连接结构体 Download PDF

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CN107960139B
CN107960139B CN201680027076.0A CN201680027076A CN107960139B CN 107960139 B CN107960139 B CN 107960139B CN 201680027076 A CN201680027076 A CN 201680027076A CN 107960139 B CN107960139 B CN 107960139B
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anisotropic conductive
conductive film
conducting particles
terminal
film
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CN107960139A (zh
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林慎一
齐藤雅男
阿久津恭志
塚尾怜司
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Dozai Co Ltd
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Dozai Co Ltd
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Abstract

各向异性导电膜(1A)包含绝缘粘接剂层(10)和配置于该绝缘粘接剂层(10)的导电粒子(2)。各向异性导电膜(1A)中，粒子间距(P1)的导电粒子(2)的排列轴(A1)在各向异性导电膜(1A)的大致膜宽度方向上延伸，该排列轴(A1)在各向异性导电膜(1A)的长边方向上以轴间距(P2)连续地排列。当由各向异性导电膜(1A)连接的电子部件的端子排列区域和各向异性导电膜(1A)按照各端子的长边方向与膜宽度方向匹配的方式重叠时，根据端子(21)的外形确定排列轴(A1)中的粒子间距(P1)、排列轴的轴间距(P2)以及排列轴(A1)与膜宽度方向所成的角度(排列轴的倾斜角)(θ)，以使各端子(21)上存在3个以上40个以下的导电粒子(2)。由此，即使在微间距的连接中，也会因使用各向异性导电膜而获得稳定的连接可靠性，并且抑制导电粒子的过度的密度增加。

Description

各向异性导电膜和连接结构体
技术领域
本发明涉及各向异性导电膜和由各向异性导电膜连接而成的连接结构体。
背景技术
各向异性导电膜在将IC芯片等电子部件安装于基板时被广泛使用。近年来，手机、笔记本电脑等小型电子设备中要求配线的高密度化，作为使各向异性导电膜对应于该高密度化的方法，已知将导电粒子以格子状均等配置于各向异性导电膜的绝缘粘接剂层的技术。
然而，即使均等配置导电粒子，也会出现连接电阻不均这样的问题。这是因为，各向异性导电连接前位于端子边缘上的导电粒子由于绝缘性粘接剂的熔融而从空隙流出，难以被上下的端子夹持。对于该问题，提出了将导电粒子的第一排列方向设为各向异性导电膜的长边方向，使与第一排列方向交叉的第二排列方向相对于与各向异性导电膜的长边方向正交的方向倾斜5°以上15°以下(专利文献1)。
现有技术文献
专利文献
专利文献1：日本特许4887700号公报
发明内容
发明要解决的课题
然而，如果由各向异性导电膜连接的电子部件的端子尺寸进一步变小，则能够被端子捕捉的导电粒子数也进一步变少，就专利文献1中记载的各向异性导电膜而言，有无法充分获得导通可靠性的情况。尤其是，在将用于控制液晶画面等的IC连接于玻璃基板上的透明电极的所谓COG(Chip on Glass，玻璃覆晶)连接中，伴随着液晶画面高精细化的多端子化和IC芯片的小型化，端子尺寸变小，此外，在进行将用于电视机的显示器的玻璃基板与柔性印刷配线板(FPC：Flexible Printed Circuits)连接的FOG(Film on Glass，玻璃覆膜)连接的情况下，端子也为微间距，使能够被端子捕捉的导电粒子数增加而提高连接可靠性成为课题。
对此，作为使被端子捕捉的导电粒子数增加的方法，考虑了提高各向异性导电膜中导电粒子的密度。然而，如果提高各向异性导电膜中导电粒子的密度，则产生各向异性导电膜的制造成本变高的问题。
另外，如果使被端子捕捉的导电粒子过度增加，则随着因微间距化而端子个数本身增加，各向异性导电连接时端子的压入所需的按压力变得过高，在以往的连接装置中难以实现良好的各向异性导电连接。因此，产生了为了用于应对按压力的增加而导入装置、改良，从而花费成本这样的问题。
这里，本发明的课题在于，即使在微间距的FOG连接、COG连接中，也能使用各向异性导电膜获得稳定的连接可靠性，并且抑制与导电粒子的密度增加相伴随的各向异性导电膜的制造成本的升高，另外，能够利用以往的设备进行各向异性导电连接。
解决课题的方法
本发明人发现，如果使用导电粒子以预定的粒子间距排列而成的排列轴在各向异性导电膜的长边方向上连续排列的各向异性导电膜，并且当使电子部件的端子的长边方向与该各向异性导电膜的膜宽度方向匹配时，根据端子的外形确定导电粒子的排列轴中的粒子间距、该排列轴的轴间距、以及排列轴与膜宽度方向所成的角度(以下称为排列轴的倾斜角)，以使3个以上40个以下的导电粒子位于各端子，则能够在确保充分的导通可靠性的同时减少对连接没有帮助的导电粒子，另外，当使预定个数的导电粒子存在于预定的面积的区域中、使该区域的导电粒子的排列轴在各向异性导电膜的宽度方向上倾斜、并且使该区域在各向异性导电膜的长边方向上重复存在的情况下，也能够在确保充分的导通可靠性的同时减少对连接没有帮助的导电粒子，并获得了本发明。
即，提供一种各向异性导电膜，其是包含绝缘粘接剂层和配置于该绝缘粘接剂层的导电粒子的各向异性导电膜，
预定的粒子间距的导电粒子的排列轴在各向异性导电膜的大致膜宽度方向上延伸，该排列轴在各向异性导电膜的长边方向上以预定的轴间距连续排列，
当由各向异性导电膜连接的电子部件的端子排列区域和各向异性导电膜按照各端子的长边方向与膜宽度方向匹配的方式重叠时，根据端子的外形确定排列轴中的粒子间距、排列轴的轴间距、以及排列轴的倾斜角，以使各端子上存在3个以上40个以下的导电粒子。
另外，将本发明替换为其他的表现形式，则提供一种各向异性导电膜，其是包含绝缘粘接剂层和配置于该绝缘粘接剂层的导电粒子的各向异性导电膜，
在任意选择的长度为膜的长边方向上的5～400μm、宽度为膜宽度的区域内，存在3～3200个导电粒子，该区域中预定的粒子间距的导电粒子的排列轴与各向异性导电膜的膜宽度方向斜交，该排列轴在各向异性导电膜的长边方向上并排排列。
进一步，本发明提供一种连接结构体，第一电子部件与第二电子部件通过上述的各向异性导电膜而被各向异性导电连接。
发明效果
根据本发明的各向异性导电膜，当使由该各向异性导电膜连接的电子部件的端子的长边方向与该膜宽度方向匹配时，各端子中存在3个以上的导电粒子，因此能够对使用了各向异性导电膜的连接结构体赋予充分的导通可靠性。这种情况下，除了使各向异性导电膜的膜宽度方向与端子的长边方向匹配之外，无需使各向异性导电膜与端子的位置匹配。
另外，由于各端子中存在的导电粒子的数量为40个以下，因此对连接没有帮助的导电粒子不会过度增加，能够抑制与导电粒子的密度增加相伴随的各向异性导电膜的制造成本的升高，另外能够适当地调整被端子捕捉的导电粒子数，因此也可以省去新连接设备的导入。
进一步，根据本发明的各向异性导电膜，导电粒子的排列轴中的粒子间距、该排列轴的轴间距、以及排列轴的倾斜角是根据由该各向异性导电膜连接的电子部件的端子的外形而被规定，因此能够正确地控制每个端子的导电粒子的个数。
从其他观点考虑，本发明的各向异性导电膜由于在任意选择的长度为膜的长边方向上的5～400μm、宽度为膜宽度的区域内，存在3～3200个导电粒子，该区域中预定的粒子间距的导电粒子的排列轴与各向异性导电膜的膜宽度方向斜交，该排列轴在各向异性导电膜的长边方向上并排排列，因此对连接没有帮助的导电粒子的个数不会过度增加，能够抑制与导电粒子的密度增加相伴随的各向异性导电膜的制造成本的升高。
附图说明
[图1]图1为各向异性导电膜1A中导电粒子的配置图。
[图2A]图2A为图1的导电粒子的配置中轴间距最小的情况的放大图。
[图2B]图2B为图1的导电粒子的配置中轴间距最大的情况的放大图。
[图3A]图3A为图2A所示的导电粒子的配置图的变形例。
[图3B]图3B为图2B所示的导电粒子的配置图的变形例。
[图4]图4为各向异性导电膜1B中的导电粒子的配置图。
[图5]图5为各向异性导电膜1C中的导电粒子的配置图。
[图6]图6为各向异性导电膜1D中的导电粒子的配置图。
[图7]图7为实施例1、2的各向异性导电膜中的导电粒子的配置图。
[图8]图8为实施例3、7的各向异性导电膜中的导电粒子的配置图。
[图9]图9为实施例4、8的各向异性导电膜中的导电粒子的配置图。
[图10]图10为实施例5、9的各向异性导电膜中的导电粒子的配置图。
[图11]图11为实施例6、10的各向异性导电膜中的导电粒子的配置图。
[图12]图12为比较例2的各向异性导电膜中的导电粒子的配置图。
具体实施方式
以下，参照附图详细说明本发明。需要说明的是，各图中，相同符号表示相同或等同的构成要素。
图1为本发明的一实施例的各向异性导电膜1A中的导电粒子2的配置图，图2A为与图1的配置图的输出侧端子相对应的导电粒子的排列区域的放大图，且轴间距为最小的情况的图，图2B是同样的放大图、且轴间距为最大的情况的图。
该各向异性导电膜1A具有绝缘粘接剂层10和配置于绝缘粘接剂层10的导电粒子2。导电粒子2以预定的粒子间距P1大致在各向异性导电膜1A的膜宽度方向上延伸，形成相对于膜宽度方向稍有倾斜的排列轴A1，该排列轴A1在各向异性导电膜1A的长边方向上以预定的轴间距P2连续地形成。
图1中，极细的矩形轮廓线表示由该各向异性导电膜1A连接的IC芯片等电子部件20的端子面，由点填涂的矩形区域表示电子部件20的输出侧端子21和输入侧端子24。输出侧端子21和输入侧端子24分别具有预定的端子宽度和端子长度，以预定的端子间距在端子宽度方向上排列。因此，如果使电子部件20的端子21、24的长边方向与各向异性导电膜1A的膜宽度方向匹配，则端子21、24在各向异性导电膜1A的膜长边方向上排列。
该各向异性导电膜1A具有一个端子可存在3个以上的导电粒子2的排列轴A1，根据该端子21、24的外形确定排列轴A1的粒子间距P1、轴间距P2、排列轴A1的倾斜角θ，以使各端子21、24由这样的三根以上的排列轴横穿，由此，各端子21、24上存在3个以上40个以下的导电粒子2。
更具体而言，如图2A、图2B所示，将导电粒子2的排列轴A1设为连通位于矩形的输出侧端子21的对角的角落部的导电粒子2a、2b和中央部的导电粒子2c的直线的情况下，将端子21的端子长度设为L1、端子宽度设为L2、端子中的对角线的长度设为L3、端子间距离设为L4、1个间距(端子宽度L2+端子间距离L4)与端子长度L1所成的矩形中的对角线的长度设为L5、将导电粒子2的粒径设为D时，排列轴A1与各向异性导电膜的膜宽度方向所成的角度θ可以按照下式的方式求出。
图2A的情况Tanθ＝(L2-D)/(L1-D)≈L2/L1式(1)
图2B的情况Tanθ＝(L2+L4-D)/(L1-D)≈(L2+L4)/L1 式(2)
这里，当相对于导电粒子的粒径D，端子长度L1、端子宽度L2足够大的情况下，可近似为：(L2/L1)≤Tanθ≤(L2+L4)/L1。
另外，如果将端子21上的排列轴A1上可存在的导电粒子的最大数设为n个，则排列轴A1中的粒子间距P1的范围可由下式求出。
图2A的情况粒子间距P1＝(L3-D)/(n-1)≈L3/2
图2B的情况粒子间距P1＝(L5-D)/(n-1)≈L5/2
如图2A所示，当n＝3、相对于导电粒子的粒径D、端子的对角线的长度L3充分大的情况下，可以近似为P1≈L3/2，
如图2B所示，可以近似为P1≈L5/2。
排列轴A1的轴间距P2的范围可由下式求出。
图2A的情况轴间距P2＝(L2-D)/2
图2B的情况轴间距P2＝{(L2+L4)-D}/2
需要说明的是，就上述的图2A和图2B所示的粒子配置而言，导电粒子2a、2b存在于端子21的端部22a、22b。这种情况下，各向异性连接时导电粒子2a、2b由于树脂流动等只要与端子21的端部22a、22b发生微小的偏离，导电粒子的捕捉数就会减少。在这里，为了具有设计上的裕度，如图3A和图3B所示那样，可以将导电粒子2配置于端子21的端部22a、22b的内侧。具体而言，作为导电粒子的排列的最小重复单元的单元形状(单元格子)距离端子21的外周部可以仅以导电粒径D的1～3倍量的长度将导电粒子2配置于端子21的内侧。该单元形状在膜的长边方向上重复，从而仅通过使膜的宽度方向与端子的短边方向匹配，导电粒子的捕捉数变得稳定。
此外，虽然图2A～图3B中未示出，由于仅通过使膜的宽度方向与端子的长边方向匹配来使捕捉数稳定，因此在膜的宽度方向上也可使排列的单元形状重复。这对于端子的长边方向的长度比膜宽度短的情况(例如COG连接)是有效的。另一方面，端子的长边方向的长度相比于膜宽度充分长的情况(例如FOG连接)中，排列的单元形状(单元格子)无需在膜宽度方向上重复。这种情况下，各向异性连接时被器具按压的部分全部有助于连接。
图3A和图3B所示的导电粒子2的配置的情况中，排列轴A1与各向异性导电膜的膜宽度方向所成的角度θ1、粒子间距P1、轴间距P2分别可以通过在上述的图2A、图2B所示的粒子配置中的这些计算式中，从L1、L2、L3或L5减去(0.5×D)～(3×D)而得到的近似式来求出。
本发明中，从导通可靠性的方面考虑，各端子所捕捉的导电粒子数n设为3个以上。另外，为了使导通可靠性更稳定，该导电粒子数n优选设为5个以上，更优选设为6个以上，进一步更优选设为10个以上。另外，从不过度增大导电粒子的个数密度的方面考虑，n设为40个以下。另外，出于同样的理由，优选为35个以下，更优选为30个以下，进一步优选为20个以下。因此，1个间距(L2+L4)内存在的粒子数(即L1×(L2+L4)的区域内的个数)的上限值根据L2与L4的比率(所谓线宽和间距(L/S))来确定，设为40×{(L2+L4)/L2}个以下。因此，个数密度的上限可以通过40×{(L2+L4)/L2个除以L1×(L2+L4)的面积而得到的值来求出。
一般而言，COG连接中，即使连接的IC芯片的外形尺寸不改变，有时端子的面积也会变小、或者L/S变小，而根据本发明，即使在这样的情况下，也会根据输出侧端子21的外形来确定排列轴A1的倾斜角θ、粒子间距P1以及轴间距P2，将排列轴A1在膜的长边方向连续地形成，每1个任意的输出侧端子21配置3个以上40个以下、优选5个以上35个以下、更优选10个以上30个以下的导电粒子。因此，使用该各向异性导电膜1A进行各向异性导电连接时，能够使导电粒子2确实地捕捉到端子，得到良好的导通特性。另外，能够防止过度地增大导电粒子的个数密度，抑制与导电粒子的个数密度的增加相伴随的各向异性导电膜的制造成本升高。同时，也能够将按压力抑制在合适的范围内。
需要说明的是，用于对每1个输出侧端子配置3个以上40个以下的导电粒子的排列轴A1的倾斜角θ、粒子间距P1以及轴间距P2不限于图2A、图2B、图3A、图3B所示的导电粒子2的配置。例如可以在满足0≤Tanθ≤{(L2+L4)/L1}的范围内确定排列轴A1的倾斜角θ。但是，各向异性导电连接后，从减少端子所捕捉的导电粒子个数的不均的方面考虑，角度θ优选设为大于0°。
另外，相比于电子部件20的输出侧端子21，当输入侧端子24的端子宽度大时，输入侧端子24的连接所使用的导电粒子2的排列轴A2与膜宽度方向所成的角度、粒子间距以及轴间距可以与输出侧端子21的连接所使用的导电粒子2的排列轴A1同样地设定。换言之，由各向异性导电膜连接的电子部件具有端子尺寸、L/S不同的多个端子排列区域的情况下，本发明中，使端子宽度或端子面积最小的端子排列的各端子捕捉3个以上40个以下、优选5个以上35个以下、更优选10个以上30个以下的导电粒子2。即使电子部件中有不同大小的端子排列，也能够以匹配小尺寸的端子的方式在一个表面配置导电粒子，从而使电子部件所对应的各向异性导电膜的品种少，因而能够抑制各向异性导电膜的制造成本。
本发明中，为了确保导通可靠性、抑制连接装置所需的按压力的负担增大，导电粒子的配置区域3a、3b中的导电粒子2的密度优选为7.5～80000个/mm2，更优选为25～70000个/mm2，进一步优选为100～60000个/mm2。该粒子密度可根据导电粒子2的粒径和端子宽度、端子长度、排列方式而适宜调整。
另外，本发明中导电粒子存在的位置也可适宜设定。例如COG连接的情况中，膜宽度方向的两端部分是连接所使用的区域，因此只要以充分覆盖该部分的方式设定导电粒子的配置区域3a、3b即可。即，图1所示的各向异性导电膜1A中，设想了在矩形形状的长边侧端部附近具有端子列的某通常COG所用的IC芯片的电子部件20的、与输出侧端子21相对应的导电粒子的排列区域3a和与输入侧端子24相对应的导电粒子的排列区域3b夹着未配置导电粒子的缓冲区域4而在各向异性导电膜1A的长边方向上连续地形成。通过像这样的根据电子部件的端子排列而设置多列导电粒子的排列区域，也能减少对连接没有帮助的导电粒子，抑制各向异性导电膜的制造成本。需要说明的是，缓冲区域4不仅是导电粒子完全不存在的区域，在不对各向异性连接造成阻碍的范围内，也可以包含导电粒子未配置为预定的规则排列的区域。通过允许像这样的区域的存在，即使包含少许导电粒子的配置不良，也能作为各向异性导电膜的制品而提供，能够提高制品的成品率、削减成本。
本发明的各向异性导电膜中，排列轴A1可以相对于膜宽度方向倾斜、也可以平行，但如果使之倾斜，则在提高各端子中的导电粒子的捕捉性的方面优选。另外，为了对应于外形不同的端子，可以根据端子的外形而存在倾斜角不同的多种排列轴A1、A2。
另一方面，就该各向异性导电膜1A而言，与电子部件20的对准标记的外形相对应的导电粒子排列区域5在各向异性导电膜1A的长边方向上周期性形成。
一般而言，对准标记是为了相接合的电子部件的端子彼此位置匹配而在电子部件中形成。另一方面，当导电粒子均等地配置在各向异性导电膜的情况中，没有必要使电子部件的端子与各向异性导电膜的导电粒子的形成区域进行位置匹配，因此各向异性导电膜中不设置对准标记。
对此，就该各向异性导电膜1A而言，与输出侧端子21的排列相对应的导电粒子的排列区域3a、和与输入侧端子24的排列相对应的导电粒子的排列区域3b个别地形成。因此，优选在各向异性导电膜1A上设置与设于贴合有各向异性导电膜1A的电子部件的对准标记相对应的导电粒子排列区域5。通过使导电粒子排列区域5与电子部件的对准标记匹配，从而使电子部件20的输出侧端子21的排列区域与各向异性导电膜1A的导电粒子的排列区域3a匹配、使电子部件的输入侧端子24的排列区域与各向异性导电膜1A的导电粒子的排列区域3b匹配的操作变得容易。
需要说明的是，虽然也考虑了将与电子部件的对准标记相对应的标记用构件配置于各向异性导电膜1A的绝缘粘接剂层10，但由于各向异性导电膜的制造工序上的制约，因而难以实现。另外，虽然也考虑了在绝缘粘接剂层10上直接施以印记、切口等而进行标记，但对准标记过小，实际上的标记的加工是困难的。
对此，如果像上述的导电粒子排列区域5那样，将导电粒子的排列作为对准标记而使用，则各向异性导电膜的制造工序中无需增加新的工序，另外，将各向异性导电膜用于各向异性导电连接的情况下，不产生特别的限制，能够使导电粒子的排列区域3a、3a与电子部件的输出侧端子21的排列、输入侧端子24的排列进行位置匹配。
另外，就该各向异性导电膜1A而言，在确保连接的范围内使端子21、24所捕捉的导电粒子2的数量减少、并且使其排列，因此各向异性导电膜1A的透过性高。因此，能够没有问题地从透明基板侧透视并进行对准操作。为此，可以提高IC芯片侧的对准标记的设计自由度，将IC芯片侧的对准标记设置于端子的形成区域的附近，能够使对准精度提高。或者，使用高精度的CCD等，能够将导电粒子的排列与透明基板的电极和IC芯片的端子进行直接对准。
另外，IC芯片侧的对准标记为矩形形状且与端子具有相似性等的情况、设置与对准标记相对应的导电粒子排列区域的情况中，通过使导电粒子的排列与IC芯片侧的对准标记大体一致，可以期待以更高的精度进行IC芯片的对准。例如，当为了对准而从透明基板侧使用CCD、激光时，通过使焦点与导电粒子的排列(即各向异性导电膜1A的内部)匹配，可以在IC芯片侧的对准标记与透明基板之间设置标线(benchmark)。若使用该标线，则能够期待以更高精度进行IC芯片侧的对准标记的检测。
本发明的各向异性导电膜可以为各种各样的方式。例如，关于图4所示的各向异性导电膜1B，在图1所示的各向异性导电膜1A中，在各向异性导电膜1A的长边方向上周期性形成了与电子部件的对准标记相对应的导电粒子排列区域5。由此，为了使电子部件的对准标记与导电粒子排列区域5的位置匹配，可以减少将各向异性导电膜在膜长边方向上挪动的长度。
关于图5所示的各向异性导电膜1C，去掉了图1所示的各向异性导电膜1A中的缓冲区域4，使与电子部件的输出侧端子21相对应的导电粒子的排列区域和与电子部件的输入侧端子24相对应的导电粒子的排列区域连续。由此，具有与输出侧端子21、输入侧端子24不同的侧端子25的电子部件也可连接。如FOG连接的情况那样，在电子部件的整个面设置多个端子(列)的情况的连接中也能够使用。
需要说明的是，如图5所示，使导电粒子存在于膜整面的情况中，导电粒子的配置优选如上述那样根据端子宽度或端子面积最小的端子排列的端子来设计。
对此，在与布局不同的端子排列相对应的每个区域，可以使导电粒子的配置不同，但在考虑设计导电粒子的排列的工时和导电粒子减少所带来的成本效益的情况中，针对电子部件的每个端子布局来设计排列并不是良策。通过对不同端子布局的电子部件用一个各向异性导电膜，能够抑制各向异性导电膜的品种的数量，带来成本效益。如上述那样在端子配置的设计中仅具有导电粒径D的1～3倍量长度的裕度的情况中，能够期待这样的经济上的效果。
另外，就图1、图4、图5所示的各向异性导电膜而言，通过使导电粒子的排列轴A1在各向异性导电膜的长边方向上以预定的间距连续地形成，该各向异性导电膜中的导电粒子的排列在各向异性导电膜的长边方向上会具有格子轴，但本发明的各向异性导电膜中，导电粒子的排列不限于此。例如，如图6所示的各向异性导电膜1D那样，排列轴A1可以分别在各向异性导电膜的长边方向上以预定的倾斜角φ连续地按照预定的间距形成。如此形成的导电粒子的格子状的排列中，三个方向的格子轴分别与各向异性导电膜的长边方向和膜宽度方向斜交。由此，能够消除各向异性连接时被相对的端子的边缘部夹持为一列的导电粒子一起从端子脱落而导通不稳定的问题。
另外，如图6所示，连续地连接电子部件的情况中，在将膜裁切为预定长度时的、膜长边方向的裁切位置，可以不配置粒子。需要说明的是，未配置该粒子的区域的膜长边方向的长度作为一个例子为0.2～6mm。也可以设为连续地进行连接时的、裁切的记号。
本发明中，可以从多种导电粒子的排列轴形成导电粒子的排列。一个排列轴中的导电粒子的粒子间距可以不固定，例如，可以重复宽窄的间距。针对轴间距，也可以重复宽窄的间距。
换成其他表现方式来描述本发明，端子的长边方向上可以斜交地存在三根以上导电粒子的排列轴。由本发明的各向异性导电膜连接的端子的宽度、或端子的宽度与端子间空隙的合计(端子间距)的距离，作为一个例子最小为端子宽度5μm，最大为端子间距400μm。端子的宽度或端子间距的方向在通常的各向异性导电膜中为膜的长边方向。因此，在任意选择的膜的长边方向的长度5～400μm、宽度为膜宽度的区域R中，三根以上导电粒子的排列轴会斜交。关于此时的粒子个数，最大时在膜长边方向5μm的区域中为3200个((400μm/5μm)×40个＝3200个)，最小时在膜长边方向400μm的区域中为3个，优选为6个。因此，成为了在膜的长边方向上、在5～400μm与膜宽度求积而得到的面积中3～3200个、优选6～3200个的导电粒子作为与膜的长边方向斜交的排列轴并排排列的各向异性导电膜。该区域R可以在膜的长边方向上任意选择。
为了稳定地进行各向异性连接，上述的膜长边方向的5～400μm的区域连续地以500组(set)的长度、也就是最小5μm的区域在2500μm的各向异性连接所使用的长度量同样地存在，这在实用上优选。为了更经济地进行各向异性连接，更优选5000组的长度连续，进一步更优选10000组的长度连续。也就是说，如果将1组用包含最小的5μm的最大400μm进行换算，则为了更经济地进行各向异性连接，优选20cm以上连续，更优选2m以上连续，进一步更优选4m以上连续。
本发明中，关于导电粒子2本身的构成、绝缘粘接剂层10的层构成或构成树脂，可以设为各种各样的方式。
即，作为导电粒子2，可以从公知的各向异性导电膜所使用的导电粒子中适宜选择使用。例如，可列举镍、钴、银、铜、金、钯、焊料等金属粒子、金属被覆树脂粒子等。可以并用两种以上。导电粒子的平均粒径没有特别限定，优选为1～100μm。此外，导电粒径相对于端子的宽度优选为50％以下，更优选为30％以下。导电粒径的偏差度优选CV值为25％以下。
作为绝缘粘接剂层10，可以适宜采用公知的各向异性导电膜所使用的绝缘性树脂层。例如，可以使用包含丙烯酸酯化合物和光自由基聚合引发剂的光自由基聚合型树脂层、包含丙烯酸酯化合物和热自由基聚合引发剂的热自由基聚合型树脂层、包含环氧化合物和热阳离子聚合引发剂的热阳离子聚合型树脂层、包含环氧化合物和热阴离子聚合引发剂的热阴离子聚合型树脂层等。这些树脂层根据需要可以分别制成聚合后的树脂层。另外，绝缘粘接剂层10可以由多个树脂层形成。
绝缘粘接剂层10中，根据需要可以添加二氧化硅微粒、氧化铝、氢氧化铝等绝缘性填料。绝缘性填料的大小优选为10～2000nm，配合量优选设为相对于形成绝缘粘接剂层的树脂100质量份为1～60质量份。由此，即使各向异性导电连接时绝缘粘接剂层10熔融，也能抑制导电粒子2因熔融的树脂而不必要地移动。
关于绝缘性着剂层10的最低熔融粘度，不管是单层还是层叠体，就整体的最低熔融粘度而言，优选为10～10000Pa·s。如果为该范围，则能够将导电粒子精密地固定于任意的位置，并且在各向异性连接中也不构成阻碍。也能应对连接方法、被连接的电子部件的多样化。需要说明的是，关于最低熔融粘度，作为一例，可以使用旋转式流变仪(TAinstrument公司制)，升温速度为10℃/分钟，测定压力固定保持为5g，使用直径8mm的测定板求出。
关于各向异性导电膜的膜长度，在实用上优选为5m以上，更优选为10m以上，进一步更优选为30m以上。另外，上限没有特别规定，但对于以往的连接装置不实施过度的改造可抑制各向异性连接的成本，因此优选5000m以下，更优选1000m以下，进一步更优选500m以下。另外，膜宽度没有特别限制，为了应对通常的电子部件的端子列区域以及窄边框化的端子列区域，优选为0.3mm以上，实用上进一步优选为0.5mm以上，从制造稳定性的观点出发，进一步更优选为0.6mm以上。上限没有特别规定，一般而言为5mm以下。在堆叠IC等用途中，有时要求晶片更大，因此可以为30cm左右。
关于各向异性导电膜，为了如上述那样形成为长条状，可以用接合带接合，另外，也可以是卷绕于卷芯的卷装体。
作为将导电粒子2以上述的配置固定于绝缘粘接剂层10的方法，可以通过机械加工、激光加工、光刻等公知的方法制作具有与导电粒子2的配置相对应的凹部的模具，向该模具加入导电粒子，在其上填充绝缘粘接剂层形成用组合物并使之固化，从模具取出。从这样的模具可以以刚性更低的材质制成模具。
另外，为了将导电粒子2以上述的配置设于绝缘粘接剂层10，可以是在绝缘粘接剂层形成组合物层的上方设置以预定的配置形成有贯通孔的构件，从其上方供给导电粒子2，使其通过贯通孔等的方法。
另外，可以制成排列了导电粒子大小的程度的突起的片体，在突起的顶面形成微粘着层，向其附着导电粒子，并转印至绝缘性粘接剂层。如此，关于本发明的各向异性导电膜的制法没有特别限定。
使用本发明的各向异性导电膜，将包含柔性基板、玻璃基板等透明基板、刚性基板、陶瓷基板等非透明基板的第一电子部件的端子、与FPC、IC芯片、IC模块等第二电子部件的端子进行各向异性导电连接的情况中，例如，使各向异性导电膜1A的长边方向与第一电子部件或第二电子部件的端子的短边方向匹配，进一步使双方的对准标记匹配，进行加热加压。另外，将IC芯片、IC模块堆叠而仅将第二电子部件进行各向异性连接的方式也包含于本发明中。另外，使用本发明的各向异性导电膜连接的电子部件不限定于此。
本发明也包含如此进行各向异性导电连接而成的第一电子部件与第二电子部件的连接结构体。
实施例
以下，基于实施例具体说明本发明。
实施例1～11、比较例1、2
(1)COG连接用的各向异性导电膜的制造
关于实施例1～11、比较例1、2，分别调制表1所示组成的树脂组合物，将其涂布于膜厚50μm的PET膜上，在80℃的烘箱中干燥5分钟，在PET膜上分别按照以下所示的厚度来形成。
[表1]
第一绝缘性树脂(层厚15μm) (质量份)
苯氧树脂(新日铁住金(株)，YP-50(热塑性树脂)) 30
环氧树脂(三菱化学(株)，jER828(热固性树脂)) 40
阳离子系固化剂(三新化学工业(株)，SI-60L(潜在性固化剂)) 2
第二绝缘性树脂(层厚5μm)
苯氧树脂(新日铁住金(株)，YP-50(热塑性树脂)) 30
环氧树脂(三菱化学(株)，jER828(热固性树脂)) 40
阳离子系固化剂(三新化学工业(株)，SI-60L(潜在性固化剂)) 2
填料(日本Aerosil(株)，AEROSIL RX300) 30
另一方面，对应于COG连接的基板的电极端子的配置，制成周期性地具有凸部为预定配置密度的排列图案的模具(实施例1～11)、或凸部以预定的配置密度无规配置的模具(比较例1)、或仅在电极端子内的位置具有导电粒子的排列图案的模具(比较例2、突块形成区域内的导电粒子密度1800个/mm2(每个突块对应导电粒子5个，将突块宽度15μm和突块间距离13μm的合计28μm与突块长度100μm求积，为2800μm2。对其以突块个数1300个进行积分而得到的面积为突块形成区域。(导电粒子5(个/突块)×突块个数1300)/(2800μm2×1300)＝1800个/mm2)，将公知的透明性树脂小球以熔融的状态流入该模具，冷却固化，从而形成了凹部为格子状图案的树脂模具。在该树脂模具的凹部填充导电粒子(积水化学工业(株)、AUL704、粒径4μm)，在其上被覆上述的第二绝缘性树脂层，以60℃、0.5MPa按压从而使其贴附。然后，从模具剥离绝缘性树脂，在第二绝缘性树脂层的存在导电粒子的一侧的界面以60℃、0.5MPa层叠第一绝缘性树脂层，从而制造了表1～3所示的实施例和比较例的各向异性导电膜。
需要说明的是，就进行COG连接的IC芯片与玻璃基板而言，这些端子图案相对应，任一个实施例和比较例中都在膜表面的整面形成了导电粒子排列区域。另外，实施例1、2和比较例1、2中，进行COG连接的芯片尺寸的详细情况如下所示，其他实施例中进行COG连接的芯片的突块尺寸按照表2、表3所示的方式进行了变更。需要说明的是，随着突块宽度和突块间空隙的变更，适宜调整突块个数。另外，在显示这些实施例的图7～图11中，为了容易理解本发明的各向异性连接的效果，在图中左上方的突块的角部配置导电粒子。因此，膜向玻璃基板的预贴合、IC的搭载操作中需要一些劳动量。
另外，IC芯片中，突块列形成于沿着IC芯片的相对长边侧的边的相对区域。关于突块列间的距离，突块长度100μm时为1.5mm，突块长度50μm时为1.6mm。
IC芯片
外形1.8×20mm、厚度0.5mm
厚度0.2mm
突块规格镀金、高度12μm、尺寸15×100μm、突块间距离13μm、突块个数1300个(外形的长边侧各排列650个)
对准标记100μm×100μm
玻璃基板
玻璃材质康宁公司制
外形30×50mm
厚度0.5mm
电极ITO配线
(2)评价
将各实施例和比较例的各向异性导电膜夹持于表2～表4所示的突块尺寸的IC芯片及其相对应的玻璃基板之间，加热加压(180℃、80MPa、5秒)，得到评价用连接物，对该评价用连接物进行以下的试验。
这种情况下，关于玻璃基板和各向异性导电膜的位置匹配，就具有与对准标记相对应的导电粒子形成区域(100μm×100μm)的各向异性导电膜(对每单元面积的导电粒子个数密度不产生影响的程度的个数)而言，首先用实体显微镜确认导电粒子形成区域，通过手动操作进行玻璃基板与各向异性导电膜的位置匹配，预贴合于玻璃基板。然后以60℃、2Mpa、1秒进行预压接。并且，将预压接于玻璃基板的各向异性导电膜与IC芯片进行位置匹配并加热加压而连接IC芯片，得到评价用连接物。这里，IC芯片的连接使用了覆晶粘合剂FC1000(东丽工程(株))。
另一方面，使用不具有与对准标记相对应的导电粒子形成区域的各向异性导电膜将IC芯片与玻璃连接的情况中，在相当于玻璃基板的端子的位置按照表中记载的图那样配置导电粒子的方式，进行与各向异性导电膜的位置匹配，除此之外，与具有和对准标记相对应的导电粒子形成区域的各向异性导电膜同样地操作，得到玻璃基板和IC芯片的评价用连接物。该方法中，向玻璃基板的预贴合所需的时间变得稍长。
各向异性导电膜向玻璃基板的贴合中，将与图中的记载大体一致的情况设成膜对准为0％，将连接的IC的端子宽度的50％有意地在膜的长边方向(端子的宽度方向)上挪动的情况设为50％。
针对不同的情况，按照以下所示的方式评价(a)连接前的端子上的粒子数、(b)初期导通特性、(c)导通可靠性、(d)短路发生率。
(a)连接前的端子上的粒子数
通过从玻璃面侧观察评价用连接前的端子200个，调查每1个端子承载的可捕捉的导电粒子数，按照以下的基准进行评价。
A：10个以上
B：5个以上且小于10个
C：3个以上且小于5个
D：小于3个
(b)初期导通特性
测定评价用连接物的导通电阻，按照以下的基准进行评价。
OK：小于2Ω
NG：2Ω以上
(c)导通可靠性
将评价用连接物在温度85℃、湿度85％RH的恒温槽中放置500小时，测定导通电阻，按照以下的基准进行评价。
OK：小于8Ω
NG：8Ω以上
(d)短路发生率
作为短路发生率的评价用IC，准备如下的IC(7.5μm空隙的梳齿TEG(test elementgroup，测试元件组))。
外径1.5×13mm
厚度0.5mm
突块规格镀金、高度15μm、尺寸25×140μm、突块间距离7.5μm
将各实施例和比较例的各向异性导电膜夹持于短路发生率的评价用IC和与该评价用IC相对应的图案的玻璃基板之间，通过与评价用连接物的制作同样的连接条件，加热加压而得到连接物，求出该连接物的短路发生率。短路发生率是以“短路的发生数/7.5μm空隙总数”计算。
如果短路发生率为200ppm以上，则从制造实用上的连接结构体的方面考虑不优选。因此，将计算的短路发生率按照以下的基准进行评价。
OK：小于200ppm
NG：200ppm以上
[表2]
[表3]
[表4]
从表2～4可知，按照对应于每1个突块存在4～5个导电粒子的方式配置了导电粒子的实施例1～11的各向异性导电膜中，尽管导电粒子的粒子个数密度低至数千个/mm2，没有膜的对准偏差时当然导通特性良好，而膜的对准偏差为50％以上时导通特性也良好。
另外，实施例3和实施例8中，作为在突块的角部以外也配置有导电粒子的情况的例子，调整图8的突块长边方向中的倾斜角度和突块宽度方向的粒子间距。具体而言，关于位于图中左上方的突块角部的导电粒子和位于紧邻右下方的导电粒子，导电粒子的配置仅在突块宽度方向上偏离粒径的1.4倍。实施例3和实施例8为与其他实施例相比并不逊色的结果，由此可知即使膜在膜的长边方向上偏离，捕捉数也稳定。
对此，比较例1中无论有无对准偏差，导通特性都良好，但粒子个数密度高因而短路发生率差，各向异性导电膜的制造成本也变高。
比较例2中可知，形成相对于端子平行的排列，因此对准没有偏差的情况中，能够以比较低的粒子个数密度得到良好的导通特性，但如果存在对准偏差，则导通特性极差。
另外，相对于比较例2，使膜长边方向的对准偏差为0％，按照在膜的短边方向(端子的长边方向)偏离端子长度的50％的方式将膜贴合，除此之外，同样地操作，进行评价。其结果，即使膜长边方向的对准偏差为0％，也变得连接不良。
接下来，实施例1～11中，与上述同样地，使膜长边方向的对准偏差为0％，按照在膜的短边方向(端子的长边方向)上偏离端子长度的50％的方式将膜贴合，除此之外，同样地操作，进行评价。得到了最低限度的导通性能。进一步，即便使膜的长边方向(端子的短边方向)偏离50％，也得到最低限度的导通性能。
将具有与对准标记相对应的导电粒子形成区域的各向异性导电膜(实施例2～6)和没有与对准标记相对应的导电粒子形成区域的各向异性导电膜(实施例7～11)进行比较，则无论有无对准标记，都可得到同等的各向异性连接性能。即，除了将各向异性导电膜预贴合于玻璃基板的时间变得稍长之外，得到了基本不变的结果。需要说明的是，本实施例中，膜向玻璃基板的预贴合通过手动操作进行，但生产线中的各向异性连接可通过机械操作进行预贴合，因此认为对准标记的有无在生产线中不会带来特别的问题。
实施例1～11的排列图案中，按照IC芯片的突块列间距离的90％成为缓冲区域的方式形成模具，除此之外，同样地操作，得到实施例12～22的各向异性导电膜。进行在膜的宽度方向上偏离0％、50％的评价，得到与实施例1～11大致同等的结果。
符号说明
1A、1B、1C、1D 各向异性导电膜
2、2a、2b、2c 导电粒子
3a、3b 导电粒子的排列区域
4 缓冲区域
5 与对准标记相对应的导电粒子排列区域
10 绝缘粘接剂层
20 IC芯片、电子部件
21 输出侧端子、突块
22a、22b 输出侧端子的角落部、端部
24 输入侧端子、突块
25 侧端子
A1、A2 排列轴
D 粒径
L1 端子长度
L2 端子宽度
L3 端子中的对角线的长度
L4 端子间距离
L5 1个间距与端子长度L1的矩形中的对角线的长度
P1 粒子间距
P2 轴间距
θ 排列轴相对于膜宽度方向的角度(倾斜角)

Claims (10)

1.一种各向异性导电膜，其包含绝缘粘接剂层和配置于该绝缘粘接剂层的导电粒子，
预定的粒子间距的导电粒子的排列轴在各向异性导电膜的大致膜宽度方向上延伸，该排列轴在各向异性导电膜的长边方向上以预定的轴间距连续排列，
当由各向异性导电膜连接的电子部件的端子排列区域和各向异性导电膜按照各端子的长边方向与膜宽度方向匹配的方式重叠时，根据端子的外形确定排列轴中的粒子间距、排列轴的轴间距、以及排列轴与膜宽度方向所成的角度即排列轴的倾斜角，以使各端子上存在3个以上40个以下的导电粒子。
2.根据权利要求1所述的各向异性导电膜，当由各向异性导电膜连接的电子部件具有排列间距不同的多个端子排列区域时，根据所述多个端子排列区域所包含的端子中宽度或面积最小的端子的外形确定排列轴中的粒子间距、排列轴的轴间距、以及排列轴的倾斜角。
3.根据权利要求1或2所述的各向异性导电膜，排列轴具有可使一个端子存在3个以上导电粒子的粒子间距和倾斜角，各端子被三根以上的排列轴横穿。
4.根据权利要求1或2所述的各向异性导电膜，导电粒子排列区域对应于由各向异性导电膜连接的电子部件的端子排列区域的外形而在各向异性导电膜的长边方向上形成多列。
5.根据权利要求1或2所述的各向异性导电膜，与电子部件的对准标记的外形相对应的导电粒子排列区域在各向异性导电膜的长边方向上周期性地形成。
6.根据权利要求1或2所述的各向异性导电膜，作为导电粒子的排列轴，存在倾斜角不同的多种排列轴。
7.一种各向异性导电膜，其包含绝缘粘接剂层和配置于该绝缘粘接剂层的导电粒子，
在任意选择的长度为膜的长边方向上的5～400μm、宽度为膜宽度的区域内，存在3～3200个导电粒子，该区域中预定的粒子间距的导电粒子的排列轴与各向异性导电膜的膜宽度方向斜交，该排列轴在各向异性导电膜的长边方向上并排排列。
8.根据权利要求7所述的各向异性导电膜，作为导电粒子的排列轴，存在不同倾斜角的排列轴。
9.一种连接结构体，第一电子部件与第二电子部件通过权利要求1～8中任一项所述的各向异性导电膜而被各向异性导电连接。
10.一种连接结构体的制造方法，包括将第一电子部件与第二电子部件通过权利要求1～8中任一项所述的各向异性导电膜而各向异性导电连接的步骤。
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