CN103988289A - 带各向异性导电薄膜的半导体芯片、带各向异性导电薄膜的半导体晶片、以及半导体装置 - Google Patents
带各向异性导电薄膜的半导体芯片、带各向异性导电薄膜的半导体晶片、以及半导体装置 Download PDFInfo
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- CN103988289A CN103988289A CN201280061980.5A CN201280061980A CN103988289A CN 103988289 A CN103988289 A CN 103988289A CN 201280061980 A CN201280061980 A CN 201280061980A CN 103988289 A CN103988289 A CN 103988289A
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Abstract
本发明提供能够在连接前检查连接部的、能够预测对于连接有贡献的导电性颗粒数、且连接时对准标记的识别性优异的带各向异性导电薄膜的半导体芯片或晶片。一种带各向异性导电薄膜的半导体芯片或晶片,其特征在于,前述带各向异性导电薄膜的半导体芯片或晶片具有一面有多个电路电极的半导体芯片或晶片以及覆盖该电路电极的各向异性导电薄膜,该各向异性导电薄膜包含绝缘性树脂成分和导电性颗粒,并且该各向异性导电薄膜所含的导电性颗粒总数的60%以上存在于与该电路电极的平均高度相比为该各向异性导电薄膜的表面侧。
Description
技术领域
本发明涉及:半导体芯片上已具备各向异性导电薄膜的带各向异性导电薄膜的半导体芯片,所述各向异性导电薄膜用于将半导体芯片的电极与对应的电路基板上的电极彼此电连接;用于将对应的电路基板的电极电连接的半导体芯片制造用的、带各向异性导电薄膜的半导体晶片;以及半导体芯片的电极与对应的电路基板上的电极介由粘接剂彼此电连接的半导体装置。
背景技术
各向异性导电薄膜是绝缘性粘接剂中分散有导电性颗粒的薄膜,用于半导体芯片电极与对应的电路基板电极之间的连接。各向异性导电薄膜例如用于连接有机基板与半导体芯片、玻璃基板与半导体芯片,主要在平板显示器领域被广泛使用。
然而,随着半导体芯片的高集成化、高频化,除了以往的在有机基板上安装的方法以外,对于使用了能够缩短接线长度的各向异性导电薄膜的半导体芯片的层压化连接、与中介层(interposer)的连接的要求逐渐提高。
目前为止,有关用于连接半导体芯片电极这种微细电路的各向异性导电薄膜,公知有下述方法:为了防止短路,用电绝缘树脂覆盖导电性颗粒表面的方法(参照以下的专利文献1);将含导电性颗粒的层与不含导电性颗粒的层层压,防止相邻的电路间的短路的方法(参照以下的专利文献2、3)等。另外,还公知有单层地排列导电性颗粒以减少各向异性导电薄膜中的导电性颗粒、实现连接-绝缘的平衡化的方法(参照以下的专利文献4)。此外,还公知有下述方法:在半导体芯片的连接电极面以连接端子表面露出的方式形成绝缘性树脂层并与对应的电极压接的方法(参照以下的专利文献5~7);在半导体芯片的连接端子面以连接端子表面露出的方式形成绝缘性粘接层,并与大体贴有一层各向异性导电薄膜的电极压接的方法(参照以下的专利文献8);将半导体芯片层压在各向异性导电薄膜上,然后剥离而形成转印了各向异性导电薄膜的半导体芯片并进行压接的方法(参照以下的专利文献9、10)。另外,还提出了通过旋涂在半导体晶片上形成各向异性导电粘接剂层、接着将晶片切割而分割为单个芯片的方法(参照以下的专利文献11)。
现有技术文献
专利文献
专利文献1:日本特开平3-112011号公报
专利文献2:日本特开平6-60712号公报
专利文献3:日本特开平6-45024号公报
专利文献4:国际公开第2005/054388号小册子
专利文献5:日本特开2004-315688号公报
专利文献6:日本特开2008-133423号公报
专利文献7:日本特开2011-174010号公报
专利文献8:日本特开2009-147231号公报
专利文献9:日本特开2007-158367号公报
专利文献10:日本特开2006-287269号公报
专利文献11:日本特开平9-36143号公报
发明内容
发明要解决的问题
虽然存在前述的现有技术,但在使用各向异性导电薄膜的公知方法的情况下,难以在连接前检查连接部的导电性颗粒数、异常等。另外,由于连接时导电性颗粒发生移动,因而难以***对于连接有贡献的导电性颗粒数。对于连接有贡献的导电性颗粒数少时,存在连接时的电阻值增加、连接后的半导体装置的发热量变大的问题。
另外,半导体芯片上仅形成没有导电性颗粒的绝缘性粘接剂层的情况下,与对应的电极进行压接时,电极上容易残留绝缘性树脂,或者连接电阻受到电极高度不均的影响而变得不稳定、在连接可靠性方面也存在问题。
此外,关于在半导体芯片上贴附各向异性导电薄膜的方法,为了高连接可靠性地连接微小尺寸的电极,需要加大导电性颗粒的配合量,此时存在难以读取半导体芯片面的对准标记而无法定位的问题。
上述情况下,本发明所要解决的课题是提供能够在连接前检查连接部、能够够预测对于连接有贡献的导电性颗粒数、且连接时对准标记的识别性优异的带各向异性导电薄膜的半导体芯片。
另外,提供能够在切割前检查连接部的带各向异性导电薄膜的半导体晶片,提供通过切割该带各向异性导电薄膜的半导体晶片而能够预测对于连接有贡献的导电性颗粒数、且连接时对准标记的识别性优异的带各向异性导电薄膜的半导体芯片的制造方法。
用于解决问题的方案
本发明人等为了解决前述课题,进行了深入研究并反复实验,结果发现通过使用具有特定结构的带各向异性导电薄膜的半导体芯片或晶片能够解决上述课题,从而完成本发明。
即,本发明如下所述。
[1]一种带各向异性导电薄膜的半导体芯片,其特征在于,前述带各向异性导电薄膜的半导体芯片具有一面有多个电路电极的半导体芯片以及覆盖该电路电极的各向异性导电薄膜,该各向异性导电薄膜包含绝缘性树脂成分和导电性颗粒,并且该各向异性导电薄膜所含的导电性颗粒总数的60%以上存在于与该电路电极的平均高度相比为该各向异性导电薄膜的表面侧。
[2]根据前述[1]记载的带各向异性导电薄膜的半导体芯片,其中,前述各向异性导电薄膜的、位于与前述电路电极的平均高度相比为表面侧的绝缘性树脂成分的高度是前述导电性颗粒的平均直径的1.0倍~2.0倍。
[3]根据前述[1]或[2]记载的带各向异性导电薄膜的半导体芯片,其中,前述各向异性导电薄膜具有覆盖前述电路电极的绝缘性粘接剂层和导电性颗粒层,该导电性颗粒层是前述导电性颗粒在绝缘性树脂中大致平面状地分散排列1层而成的。
[4]根据前述[3]记载的带各向异性导电薄膜的半导体芯片,其中,20℃~100℃的温度范围内,前述绝缘性粘接剂层的树脂成分的粘度低于前述导电性颗粒层的绝缘性树脂的粘度。
[5]根据前述[3]或[4]记载的带各向异性导电薄膜的半导体芯片,其中,前述导电性颗粒层的绝缘性树脂的厚度是前述导电性颗粒的平均直径的0.4~2.0倍。
[6]根据前述[3]~[5]中任一项记载的带各向异性导电薄膜的半导体芯片,其中,前述导电性颗粒层中的导电性颗粒总数的90%以上独立存在,相邻的导电性颗粒间的平均颗粒间距是该导电性颗粒的平均直径的1.0~20倍。
[7]根据前述[1]~[6]中任一项记载的带各向异性导电薄膜的半导体芯片,其中,前述导电性颗粒总数的70%以上从前述各向异性导电薄膜的表面露出其一部分。
[8]根据前述[1]~[7]中任一项记载的带各向异性导电薄膜的半导体芯片,其中,前述导电性颗粒是平均直径2~50μm的大致球状的颗粒,并且选自由塑料制颗粒被金属包覆而成的颗粒、金属颗粒、合金颗粒、以及金属制颗粒或合金制颗粒被金属或合金包覆而成的颗粒组成的组中。
[9]根据前述[1]~[8]中任一项记载的带各向异性导电薄膜的半导体芯片,其中,从前述半导体芯片的外形溢出的前述各向异性导电薄膜的最大溢出长度为50μm以下。
[10]一种前述[1]记载的带各向异性导电薄膜的半导体芯片的制造方法,其包括以下的工序:
将一面有多个电路电极的半导体芯片的该电路电极面层压在如下的层压体上的工序,所述层压体是支撑体、和导电性颗粒在断面厚度方向偏在于支撑体侧的各向异性导电薄膜层按该顺序层压而成的;以及
将该经过层压的该半导体芯片连同该各向异性导电薄膜层从该支撑体剥离的工序。
[11]根据前述[10]记载的方法,其中,前述各向异性导电薄膜层具有绝缘性粘接剂层和导电性颗粒层,该导电性颗粒层是前述导电性颗粒在绝缘性树脂中大致平面状地分散排列1层而成的。
[12]一种前述[3]记载的带各向异性导电薄膜的半导体芯片的制造方法,其包括以下的工序:
向一面有多个电路电极的半导体芯片的电路电极面填充绝缘性粘接剂的工序;
在所得到的带绝缘性粘接剂层的半导体芯片上层压导电性颗粒层的工序,所述导电性颗粒层形成在支撑体上且是导电性颗粒在绝缘性树脂中大致平面状地分散排列1层而成的;
将前述带绝缘性粘接剂层的半导体芯片连同前述导电性颗粒层从前述支撑体剥离的工序。
[13]一种前述[3]记载的带各向异性导电薄膜的半导体芯片的制造方法,其包括以下的工序:
向一面有多个电路电极的半导体芯片的电路电极面填充绝缘性粘接剂的工序;
在所得到的带绝缘性粘接剂层的半导体芯片上层压导电性颗粒的工序,所述导电性颗粒是在层压于支撑体上的粘接剂层上分散排列而形成的;
将前述带绝缘性粘接剂层的半导体芯片连同前述导电性颗粒从层压于前述支撑体上的粘接剂层剥离的工序。
[14]根据前述[10]~[13]中任一项记载的方法,其中,前述层压的工序中,20℃~100℃下进行真空层压。
[15]一种半导体装置的制造方法,包括将前述[1]~[9]中任一项记载的带各向异性导电薄膜的半导体芯片的电路电极与具有对应的连接电极的电路基板对准位置来热压接的工序。
[16]根据前述[15]记载的方法,包括在前述热压接的工序之前目视检查前述电路电极上的导电性颗粒数的工序。
[17]一种由前述[15]或[16]记载的方法制造的半导体装置,其中,前述热压接后的前述连接电极上的每单位面积的导电性颗粒数为前述电路电极以外的部分的每单位面积的导电性颗粒数的65%以上。
[18]一种带各向异性导电薄膜的半导体晶片,其特征在于,前述带各向异性导电薄膜的半导体晶片具有一面有多个电路电极的半导体晶片以及覆盖该电路电极的各向异性导电薄膜,该各向异性导电薄膜包含绝缘性树脂成分和导电性颗粒,并且该各向异性导电薄膜所含的导电性颗粒总数的60%以上存在于与该电路电极的平均高度相比为该各向异性导电薄膜的表面侧。
[19]根据前述[18]记载的带各向异性导电薄膜的半导体晶片,其中,前述各向异性导电薄膜的、位于与前述电路电极的平均高度相比为表面侧的绝缘性树脂成分的高度是前述导电性颗粒的平均直径的1.0倍~2.0倍。
[20]根据前述[18]或[19]记载的带各向异性导电薄膜的半导体晶片,其中,前述各向异性导电薄膜具有覆盖前述电路电极的绝缘性粘接剂层和导电性颗粒层,该导电性颗粒层是前述导电性颗粒在绝缘性树脂中大致平面状地分散排列1层而成的。
[21]根据前述[20]记载的带各向异性导电薄膜的半导体晶片,其中,20℃~100℃的温度范围内,前述绝缘性粘接剂层的树脂成分的粘度低于前述导电性颗粒层的绝缘性树脂的粘度。
[22]根据前述[20]或[21]记载的带各向异性导电薄膜的半导体晶片,其中,前述导电性颗粒层的绝缘性树脂的厚度是前述导电性颗粒的平均直径的0.4~2.0倍。
[23]根据前述[20]~[22]中任一项记载的带各向异性导电薄膜的半导体晶片,其中,前述导电性颗粒层中的导电性颗粒总数的90%以上独立存在,相邻的导电性颗粒间的平均颗粒间距是该导电性颗粒的平均直径的1.0~20倍。
[24]根据前述[18]~[23]中任一项记载的带各向异性导电薄膜的半导体晶片,其中,前述导电性颗粒总数的70%以上从前述各向异性导电薄膜的表面露出其一部分。
[25]根据前述[18]~[24]中任一项记载的带各向异性导电薄膜的半导体晶片,其中,前述导电性颗粒是平均直径2~50μm的大致球状的颗粒,并且选自由塑料制颗粒被金属包覆而成的颗粒、金属颗粒、合金颗粒、以及金属制颗粒或合金制颗粒被金属或合金包覆而成的颗粒组成的组中。
[26]一种前述[18]记载的带各向异性导电薄膜的半导体晶片的制造方法,其包括以下的工序:
将一面有多个电路电极的半导体晶片的该电路电极面层压在如下的层压体上的工序,所述层压体是支撑体、和导电性颗粒在断面厚度方向偏在于支撑体侧的各向异性导电薄膜层按该顺序层压而成的;以及
将该经过层压的该半导体晶片连同该各向异性导电薄膜层从该支撑体剥离的工序。
[27]根据前述[26]记载的方法,其中,前述各向异性导电薄膜层具有绝缘性粘接剂层和导电性颗粒层,该导电性颗粒层是前述导电性颗粒在绝缘性树脂中大致平面状地分散排列1层而成的。
[28]一种前述[20]记载的带各向异性导电薄膜的半导体晶片的制造方法,其包括以下的工序:
向一面有多个电路电极的半导体晶片的电路电极面填充绝缘性粘接剂的工序;
在所得到的带绝缘性粘接剂层的半导体晶片上层压导电性颗粒层的工序,所述导电性颗粒层形成在支撑体上且是导电性颗粒在绝缘性树脂中大致平面状地分散排列1层而成的;
将前述带绝缘性粘接剂层的半导体晶片连同前述导电性颗粒层从前述支撑体剥离的工序。
[29]一种前述[20]记载的带各向异性导电薄膜的半导体晶片的制造方法,其包括以下的工序:
向一面有多个电路电极的半导体晶片的电路电极面填充绝缘性粘接剂的工序;
在所得到的带绝缘性粘接剂层的半导体晶片上层压导电性颗粒的工序,所述导电性颗粒是在层压于支撑体上的粘接剂层上分散排列而形成的;
将前述带绝缘性粘接剂层的半导体晶片连同前述导电性颗粒从层压于前述支撑体上的粘接剂层剥离的工序。
[30]根据前述[26]~[29]中任一项记载的方法,其中,前述层压的工序中,20℃~100℃下进行真空层压。
[31]一种带各向异性导电薄膜的半导体芯片的制造方法,包括切割前述[18]~[25]中任一项记载的带各向异性导电薄膜的半导体晶片的工序。
[32]根据前述[31]记载的方法,其中,包括在切割前述带各向异性导电薄膜的半导体晶片的工序之前目视检查前述电路电极上的导电性颗粒数的工序。
[33]一种半导体装置,该半导体装置包括一面有多个电路电极的半导体芯片、具有与该电路电极对应的连接电极的电路基板、以及粘接剂,该粘接剂包含绝缘性树脂和导电性颗粒、且被配置在该半导体芯片与该电路基板之间,该半导体芯片上的距离最短的电路电极间的沿厚度方向切断的断面中,距半导体芯片最近的导电性颗粒与距半导体芯片最远的导电性颗粒的厚度方向的颗粒间距是该导电性颗粒的平均直径的1倍以下。
[34]根据前述[33]记载的半导体装置,其中,前述导电性颗粒是平均直径2~50μm的大致球状的颗粒,并且选自由塑料制颗粒被金属包覆而成的颗粒、金属颗粒、合金颗粒、以及金属制颗粒或合金制颗粒被金属或合金包覆而成的颗粒组成的组中。
[35]根据前述[33]或[34]记载的半导体装置,其中,从前述半导体芯片的外形溢出的前述粘接剂的最大溢出长度为50μm以下。
[36]根据前述[33]~[35]中任一项记载的半导体装置,其中,前述热压接后的前述连接电极上的每单位面积的导电性颗粒数为前述电路电极以外的部分的每单位面积的导电性颗粒数的65%以上。
发明的效果
本发明的带各向异性导电薄膜的半导体芯片或晶片能够在连接前检查连接部、能够预测对于连接有贡献的导电性颗粒数、且连接时对准标记的识别性优异。
附图说明
图1所示为本实施方式的带各向异性导电薄膜的半导体芯片的一个例子的断面图。
图2所示为本实施方式的带各向异性导电薄膜的半导体芯片(包括导电性颗粒层/绝缘性粘接剂层的结构)的一个例子的断面图。
图3所示为本实施方式的带各向异性导电薄膜的半导体芯片的制造方法(方法1)的一个例子的示意图。(a)所示为将一面有多个电路电极的半导体芯片的该电路电极面层压在如下的层压体上的工序,所述层压体是支撑体、和导电性颗粒在断面厚度方向偏在于支撑体侧的各向异性导电薄膜层按照该顺序层压而成的。(b)所示为将该经过层压的该半导体芯片连同该各向异性导电薄膜层从该支撑体剥离的工序。
图4所示为本实施方式的带各向异性导电薄膜的半导体芯片的制造方法(方法2)的一个例子的示意图。(a)所示为向一面有多个电路电极的半导体芯片的电路电极面填充绝缘性粘接剂的工序。(b)所示为在所得到的带绝缘性粘接剂层的半导体芯片上层压导电性颗粒层的工序,所述导电性颗粒层形成在支撑体上且是导电性颗粒在绝缘性树脂中大致平面状地分散1层而成的。
图5所示为本实施方式的带各向异性导电薄膜的半导体芯片的制造方法(方法3)的一个例子的示意图。(a)所示为向一面有多个电路电极的半导体芯片的电路电极面填充绝缘性粘接剂的工序。(b)所示为在所得到的带绝缘性粘接剂层的半导体芯片上层压导电性颗粒的工序,所述导电性颗粒是在层压于支撑体上的粘接剂层上分散排列而形成的。
图6所示为本实施方式的带各向异性导电薄膜的半导体晶片的一个例子的断面图。
图7所示为本实施方式的带各向异性导电薄膜的半导体晶片(包括导电性颗粒层/绝缘性粘接剂层的结构)的一个例子的断面图。
图8所示为本实施方式的带各向异性导电薄膜的半导体晶片的制造方法(方法1)的一个例子的示意图。(a)所示为将一面有多个电路电极的半导体晶片的该电路电极面层压在如下的层压体上的工序,所述层压体是支撑体、和导电性颗粒在断面厚度方向偏在于支撑体侧的各向异性导电薄膜层按该顺序层压而成的。(b)所示为将该经过层压的该半导体晶片连同该各向异性导电薄膜层从该支撑体剥离的工序。
图9所示为本实施方式的带各向异性导电薄膜的半导体晶片的制造方法(方法2)的一个例子的示意图。(a)所示为向一面有多个电路电极的半导体晶片的电路电极面填充绝缘性粘接剂的工序。(b)所示为在所得到的带绝缘性粘接剂层的半导体晶片上层压导电性颗粒层的工序,所述导电性颗粒层形成在支撑体上且是导电性颗粒在绝缘性树脂中大致平面状的分散1层而成的。
图10所示为本实施方式的带各向异性导电薄膜的半导体晶片的制造方法(方法3)的一个例子的示意图。(a)所示为向一面有多个电路电极的半导体晶片的电路电极面填充绝缘性粘接剂的工序。(b)所示为在所得到的带绝缘性粘接剂层的半导体晶片上层压导电性颗粒的工序,所述导电性颗粒是在层压于支撑体上的粘接剂层上分散排列而形成的。
图11所示为本实施方式的半导体装置的一个例子的断面图。
具体实施方式
以下,对于用于实施本发明的方式(以下简称为“实施方式”)进行详细的说明。需要说明的是,本发明不限于以下的实施方式,可以在其要旨的范围内进行各种变形而实施。
本实施方式的带各向异性导电薄膜的半导体芯片具有一面(主表面的至少一侧)有多个电路电极的半导体芯片以及覆盖电路电极的各向异性导电薄膜(参照图1)。
本实施方式中,各向异性导电薄膜包含绝缘性树脂成分和导电性颗粒,该导电性颗粒在断面厚度方向不均匀分布。具体而言,导电性颗粒总数的60%以上、优选70%以上、更优选80%以上、进一步优选90%以上存在于与半导体芯片的电路电极的平均高度相比为该各向异性导电薄膜的表面侧。其中,电路电极的平均高度是指半导体芯片断面中以未配置电路电极的部分为基准的、各电路电极的高度的平均。各向异性导电薄膜的表面侧是指各向异性导电薄膜断面中与半导体芯片接触侧的相反侧。若导电性颗粒总数的60%以上存在于与半导体芯片的电路电极的平均高度相比为该各向异性导电薄膜的表面侧,从连接电阻稳定化的方面来看是优选的。
各向异性导电薄膜的绝缘性树脂成分还可以包含固化性树脂、固化剂。
作为导电性颗粒,可以使用金属颗粒、塑料制颗粒被金属薄膜包覆而成的颗粒。作为金属颗粒,例如可列举出:金、银、铜、镍、铝、锌、锡、铅、铟、钯等的单质;这些金属中的2种以上层状或倾斜状地组合而成的颗粒;或者2种以上组合得到的合金、焊剂等。使用熔点为150℃以上且500℃以下的合金颗粒、焊剂颗粒的情况下,优选先在颗粒表面包覆熔剂等。通过使用熔剂,可以去除表面的氧化物等。作为熔剂,可以使用松香酸等的脂肪酸。
作为塑料制颗粒被金属薄膜包覆而成的颗粒,可例示出选自环氧树脂、苯乙烯树脂、有机硅树脂、丙烯酸类树脂、聚烯烃树脂、三聚氰胺树脂、苯并胍胺树脂、聚氨酯树脂、酚醛树脂、聚酯树脂、二乙烯基苯树脂、NBR、SBR等聚合物中的1种或2种以上的组合通过镀敷等被金属包覆而成的颗粒。从连接稳定性和颗粒的聚集性的观点考虑,金属薄膜的厚度优选为0.005μm以上且1μm以下的范围。还可以使用将所述导电性颗粒的表面进一步绝缘包覆而成的颗粒、表面形成有微小突起的糖果型的颗粒。
作为导电性颗粒,优选使用球状的导电性颗粒,此情况下更优选近似圆球的导电性颗粒。短轴与长轴的比优选为0.5以上,更优选为0.7以上,进一步优选为0.9以上。短轴与长轴的比的最大值是1。
导电性颗粒的平均直径必须小于所要连接的相邻电极间的距离,同时还优选大于需要连接的电子部件的电极高度的偏差。因此,导电性颗粒的平均直径优选为2.0μm以上且50μm以下的范围、更优选为2.5μm以上且40μm以下、进一步优选为3.0μm以上且35μm以下、特别优选为4.0μm以上且30μm以下。另外,导电性颗粒的粒径分布的标准偏差优选为平均直径的50%以下。
另外,各向异性导电薄膜还可以进一步含有绝缘颗粒、填充剂、软化剂、固化促进剂、稳定剂、着色剂、阻燃剂、流动调节剂、偶联剂等。
配合绝缘性颗粒、填充剂等固形物时,它们的最大直径优选小于导电性颗粒的平均直径。作为偶联剂,从密合性的观点考虑,优选含有环氧基、酮亚胺基、乙烯基、丙烯酰基、氨基、异氰酸酯基等的硅烷偶联剂。
各向异性导电薄膜的、位于与电路电极平均高度相比为表面侧的绝缘性树脂成分的高度(厚度)优选是所含的导电性颗粒的平均直径的1.0~2.0倍、更优选是1.0~1.5倍、进一步优选是1.0~1.2倍。其中,导电性颗粒的平均直径是指导电性颗粒的长径的平均。从控制各向异性导电薄膜的粘性以及控制导电性颗粒保持性的观点考虑,该厚度优选是导电性颗粒的平均直径的1.0倍以上,而从抑制连接时导电性颗粒移动的观点考虑,优选是2.0倍以下。
另外,优选该厚度是电路电极的平均高度的1.05倍~1.5倍。从控制各向异性导电薄膜的粘性以及控制导电性颗粒保持性的观点考虑,该厚度优选是电路电极的平均高度的1.05倍以上,而从抑制连接时导电性颗粒移动的观点考虑,优选是1.5倍以下。
各向异性导电薄膜优选包含绝缘性粘接剂层、以及导电性颗粒在绝缘性树脂中大致平面状地分散排列1层而成的导电性颗粒层(参照图2)。
导电性颗粒层的绝缘性树脂的厚度优选是导电性颗粒的平均直径的0.4~2.0倍,更优选是0.5~1.8倍,进一步优选是0.7~1.0倍。从控制导电性颗粒层的粘性以及控制导电性颗粒保持性的观点考虑,该厚度优选是0.4倍以上,而从连接稳定性的观点考虑,优选是2.0倍以下。
本实施方式的带各向异性导电薄膜的半导体芯片中,指示各向异性导电薄膜从半导体芯片外形溢出的量的、最大溢出长度优选为-20~50μm,更优选为-10~30μm,进一步优选为0~20μm。从电连接性以及机械连接性的观点考虑,该溢出长度优选为-20μm以上,而从操作性以及连接时树脂溢出的观点来看优选为50μm以下。
本实施方式的各向异性导电薄膜中的导电性颗粒总数的70%以上优选从各向异性导电薄膜的表面露出其一部分。露出的颗粒数更优选为80%以上,进一步优选为90%以上。连接时,从与对应的电极的连接性的观点考虑,导电性颗粒优选从各向异性导电薄膜的表面露出。指示露出的每个颗粒的露出程度的露出高度优选小于该颗粒的平均直径的50%。该露出高度若小于50%,从不容易引起导电性颗粒欠缺的方面来看是优选的。
本实施方式所用的绝缘性粘接剂可以含有选自由热固化性树脂、热塑性树脂、光固化性树脂、电子束固化性树脂组成的组中的1种以上的树脂。这些树脂例如可列举出环氧树脂、氧杂环丁烷树脂、酚醛树脂、有机硅树脂、聚氨酯树脂、丙烯酸类树脂、聚酰亚胺树脂、苯氧树脂、聚乙烯醇缩丁醛树脂、SBR、SBS、NBR、聚对苯二甲酸乙二醇酯树脂、聚酰胺树脂、聚苯乙烯树脂、聚异丁烯树脂、烷基酚醛树脂、苯乙烯-丁二烯树脂、羧基改性腈树脂等或它们的改性树脂。从密合性的观点考虑,绝缘性粘接剂优选含有环氧树脂、氧杂环丁烷树脂。
作为其中所用的环氧树脂,例如有双酚A型环氧树脂、双酚F型环氧树脂、双酚S型环氧树脂、四亚甲基双酚A型环氧树脂、联苯型环氧树脂、萘型环氧树脂、间苯二酚型环氧树脂、芴型环氧树脂、苯酚酚醛清漆型环氧树脂、甲酚酚醛清漆型环氧树脂、双酚A型酚醛清漆型环氧树脂、脂肪族醚型环氧树脂等的缩水甘油基醚型环氧树脂、缩水甘油基醚酯型环氧树脂、缩水甘油基酯型环氧树脂、缩水甘油基胺型环氧树脂、脂环式环氧树脂等,这些环氧树脂可以被卤代或加氢,或者可以为聚氨酯改性、橡胶改性、有机硅改性等的改性环氧树脂。
另外,出于赋予薄膜形成性、粘接性、固化时的应力松弛的目的,优选在绝缘性粘接剂中配合热塑性树脂。热塑性树脂的分子量优选为5000~1000000,更优选为8000~80000,进一步优选为9000~60000。相对于各向异性导电薄膜中的所有树脂成分,热塑性树脂成分的含量优选为5~80质量份、更优选为10~70质量份、进一步优选为20~60质量份。若该含量为5质量份以上,从薄膜形成性的观点来看是优选的,而若为80质量份以下,从连接稳定性的观点来看是优选的。作为使用环氧树脂、氧杂环丁烷树脂时的固化剂,优选潜伏性固化剂。作为潜伏性固化剂,优选使用微胶囊型潜伏性固化剂、阳离子热固化剂等。
微胶囊型固化剂介由树脂覆膜等将固化剂的表面稳定化,树脂覆膜受到连接时的热或负荷而破坏,固化剂扩散到微胶囊外并与环氧树脂、氧杂环丁烷树脂反应。在微胶囊型潜伏性固化剂之中,将胺加合物、咪唑加合物等加合型固化剂微胶囊化的潜伏性固化剂从稳定性与固化性的平衡优异的方面来看是优选的。以相对于100质量份环氧树脂为2~100质量份的量地使用微胶囊型固化剂。
作为阳离子热固化剂,优选芳香族锍盐型固化剂。阳离子热固化剂能够均匀地配合在固化性树脂中、可以催化方式固化,因而低温、短时间内的固化成为可能,溶剂稳定性也是良好的,因而优选。作为芳香族锍盐型固化剂的阴离子,可以采用六氟锑酸根、六氟磷酸根、四氟硼酸根、四(五卤代苯基)硼酸根等,从能够减少杂质离子的方面来看,优选为四(五卤代苯基)硼酸根、特别优选为四(五氟苯基)硼酸根。
另外,绝缘性粘接剂层中,为了抗静电等,可以在不损害绝缘性的范围内添加导电性颗粒。
关于导电性颗粒的分散排列,邻近的导电性颗粒的平均颗粒间隔优选是导电性颗粒的平均直径的1.0倍以上且20倍以下、更优选是2倍以上且10倍以下。若为1.0倍以上,从不容易发生短路的方面来看是优选的,而若为20倍以下,从易于确保连接稳定性所需的导电性颗粒数的方面来看是优选的。
关于分布了导电性颗粒的平面中的分散排列状态,优选大致正三角形状地分散排列。大致正三角形状地分散排列的情况下,邻近的导电性颗粒的间隔近乎于等间隔,位于连接电极上的导电性颗粒数基本恒定,连接部的导电性颗粒数的偏差小,连接电阻稳定化,因而优选。
另外,导电性颗粒优选总数的90%以上独立存在、不发生相互聚集。即便发生聚集的情况下,也优选聚集颗粒不是4个以上的导电性颗粒聚集而成的。
导电性颗粒层包含导电性颗粒和绝缘性树脂,也可以含有固化性树脂、固化剂。导电性颗粒层的绝缘性树脂的100℃下的粘度优选处于3000Pa·s~500000Pa·s的范围,更优选为5000Pa·s~300000Pa·s,进一步优选为10000Pa·s~200000Pa·s。该粘度若为3000Pa·s以上,从容易抑制导电性颗粒的流动的方面来看是优选的。另一方面,若为500000Pa·s以下,从连接电阻值良好的方面来看是优选的。
导电性颗粒层的绝缘性树脂的100℃下的粘度、以及20℃~100℃下的粘度可分别使用流变仪来测定。优选的是,制作从导电性颗粒层中去除了导电性颗粒的物体的片,以60℃/分钟的升温条件进行测定。
绝缘性粘接剂层的100℃下的粘度优选为100Pa·s~10000Pa·s的范围,更优选为200Pa·s~5000Pa·s的范围,进一步优选处于300Pa·s~1000Pa·s的范围。绝缘性粘接剂层的100℃下的粘度从操作性的观点来看优选为100Pa·s,而从连接稳定性的观点来看优选为10000Pa·s以下。
绝缘性粘接剂层的树脂成分的100℃下的粘度、以及20℃~100℃下的粘度的测定方法分别可与导电性颗粒层的绝缘性树脂的粘度的测定为同样的方法。导电性颗粒层的绝缘性树脂的100℃下的粘度优选是绝缘性粘接剂层的树脂成分的100℃下的粘度的2倍~1000倍,更优选是5倍~500倍的范围,进一步优选是8倍~400倍的范围,特别优选为10倍~300倍的范围。该粘度比若为2倍以上,从能够在连接时抑制导电性颗粒流出的方面来看是优选的,而从连接电阻稳定化的观点来看为1000倍以下是优选的。
导电性颗粒层的绝缘性树脂成分可以与绝缘性粘接剂层的树脂成分相同,不同的情况下,20~100℃的温度范围内,优选的是,导电性颗粒层的绝缘性树脂成分的粘度高于绝缘性粘接剂层的树脂成分的粘度;更优选的是,该温度范围的各温度下的导电性颗粒层的绝缘性树脂成分的粘度与绝缘性粘接剂层的树脂成分的粘度之比为2~1000倍,该比更优选为10~500倍,该比特别优选为20~100倍。
从减少连接时的树脂从各向异性导电薄膜溢出的溢出量、以及抑制连接时导电性颗粒移动的观点考虑,导电性颗粒层的绝缘性树脂成分的粘度优选高于绝缘性粘接剂层的树脂成分的粘度。另外,从抑制灰尘附着在导电性颗粒层上、连接前的操作性的观点考虑,导电性颗粒层的绝缘性树脂成分的粘度也优选高于绝缘性粘接剂层的树脂成分的粘度。从连接稳定性的观点考虑,该粘度比优选为1000倍以下。
以下,对于本实施方式的带各向异性导电薄膜的半导体芯片的制造方法进行说明。作为本实施方式的带各向异性导电薄膜的芯片的制造方法,可以采用以下的方法。
方法1
方法1是包括以下工序的带各向异性导电薄膜的半导体芯片的制造方法(参照图3):
将一面有多个电路电极的半导体芯片的该电路电极面层压在如下的层压体上的工序,所述层压体是支撑体、和导电性颗粒在断面厚度方向偏在于支撑体侧的各向异性导电薄膜层按该顺序层压而成的;以及
将该经过层压的该半导体芯片连同该各向异性导电薄膜层从该支撑体剥离的工序。
前述各向异性导电薄膜层具有绝缘性粘接剂层、以及前述导电性颗粒大致平面状地分散排列1层而成的导电性颗粒层,从连接可靠性的观点来看是优选的。
作为在支撑体上形成导电性颗粒大致平面状地分散排列的导电性颗粒层的方法,优选采用以下的方法。
在能够双轴拉伸的支撑体(支撑薄膜)上形成粘合层,在粘合层上最密填充导电性颗粒,在导电性颗粒上涂布绝缘性树脂清漆,干燥而制作导电性颗粒填充树脂片。然后,通过将该导电性颗粒填充片双轴拉伸,得到在支撑体上形成的导电性颗粒层。将如此得到的导电性颗粒层与在剥离片上形成的绝缘性粘接剂层层压,除去剥离片,由此可以得到在支撑体上形成的各向异性导电薄膜。另外,制作导电性颗粒在支撑体上分散排列的导电性颗粒分散排列片,将如此得到的导电性颗粒分散排列片与另外在剥离薄膜上形成的绝缘性树脂片层压而形成导电性颗粒层,除去剥离薄膜,从而制作在支撑体上形成的导电性颗粒层,将如此得到的导电性颗粒层与另外在剥离片上形成的绝缘性粘接剂层层压,除去该剥离片,由此能够得到在支撑体上形成的各向异性导电薄膜。
作为上述导电性颗粒分散排列片的制造方法,可列举出下述方法:在能够双轴拉伸的支撑薄膜上形成粘合层,在粘合层上最密填充导电性颗粒,然后将该导电性颗粒填充片双轴拉伸;或者,按照规定的排列图案形成深度是导电性颗粒的平均直径的0.8~1.2倍的凹坑,制作该凹坑中填充了导电性颗粒的片,进而将支撑薄膜上形成有粘合层的粘合薄膜的粘合层面层压在该填充有导电性颗粒的片上,剥离前述填充有导电性颗粒的片,由此制作支撑薄膜上的粘合层中转印有导电性颗粒的薄膜。
方法2
方法2是包括以下工序的带各向异性导电薄膜的半导体芯片的制造方法(参照图4):
向一面有多个电路电极的半导体芯片的电路电极面填充绝缘性粘接剂的工序;
在所得到的带绝缘性粘接剂层的半导体芯片上层压导电性颗粒层的工序,所述导电性颗粒层形成在支撑体上且是导电性颗粒在绝缘性树脂中大致平面状地分散排列1层而成的;
将前述带绝缘性粘接剂层的半导体芯片连同前述导电性颗粒层从前述支撑体剥离的工序。
作为导电性颗粒层的形成方法,可以采用前述的方法。
方法3
方法3是包括以下工序的带各向异性导电薄膜的半导体芯片的制造方法(参照图5):
向一面有多个电路电极的半导体芯片的电路电极面填充绝缘性粘接剂的工序;
在所得到的带绝缘性粘接剂层的半导体芯片上层压导电性颗粒的工序,所述导电性颗粒是在层压于支撑体上的粘接剂层上分散排列而形成的;
将前述带绝缘性粘接剂层的半导体芯片连同前述导电性颗粒从层压于前述支撑体上的粘接剂层剥离的工序。
作为在层压于支撑体上的粘接剂层上分散排列而形成的导电性颗粒的制作方法,可以采用前述的导电性颗粒分散排列片的制作方法。
关于方法1~3的层压的工序,优选是20℃~100℃、更优选是30~80℃、进一步优选是40~70℃下的真空层压。从保存稳定性的观点考虑,该层压的工序的温度优选为100℃以下,而从层压性的观点来看优选为20℃以上。
将本实施方式的带各向异性导电薄膜的半导体芯片与具有对应的电极的电路基板压接来制造半导体装置的情况下,优选采用将电极彼此对准位置来热压接的方法。
作为本实施方式中使用的电路基板,可以使用有机基板、无机基板,而优选使用硅、铝、砷化镓、玻璃等的无机基板。另外,电路基板是半导体芯片,也优选采取半导体芯片层压的结构。将多个半导体芯片层压的情况下,优选在半导体芯片内设置贯通电路,在上表面侧设置连接电极、在下表面侧形成电路电极。另外,还可以在连接电极面另设线焊(wire bonding)用的电极,通过线焊形成与其他的电路基板的电连接。从因电路基板与半导体芯片连接而成的连接结构体的翘曲导致特性变化的观点考虑,电路基板的线膨胀系数优选处于2.5×10-6K-1~8×10-6K-1的范围。
半导体芯片的电路电极配置可列举出:整面配置,在芯片的下表面的几乎整面配置电极;***面配置,在除了芯片下表面的中心部以外的部分配置电极;两边配置或四边配置,在下表面端部的两边或四边配置电极;等。此外,还可以列举出在两边配置或四边配置中一部分或全部的电极配置成2列以上的交错配置等。
作为半导体芯片的形状,可以采用正方形或长方形的形状。长方形的情况下,长边与短边的比优选处于1~30的范围。
将本实施方式的带各向异性导电薄膜的半导体芯片与具有对应的电极的电路基板压接时的、指示各向异性导电薄膜从半导体芯片外周溢出的溢出量的、溢出长度优选处于连接电极高度的0.5~100倍的范围,更优选为1~80倍的范围,进一步优选为2倍~70倍的范围。从高密度安装的观点考虑,该溢出长度优选为100倍以下,从电连接、机械连接观点来看优选为0.5倍以上。压接时的溢出量可以通过调整电路电极高度、电极面积、各向异性导电薄膜厚度、各向异性导电薄膜的溢出量(长度)、各向异性导电薄膜的树脂粘度、连接温度等来控制。
半导体芯片的电路电极优选采用下述电极电路:在由选自铝、铜、镍、钨、钛、银中的1种或2种以上的金属形成的单层或多层的电极上,形成由金、焊剂或铜形成的凸电极。半导体芯片的凸电极以外的部分优选被氧化硅、氮化硅、氮氧化硅、聚酰亚胺等的绝缘膜覆盖。电路基板的连接电极优选是由选自铝、镍、铜、钨、钛、钽、钼、铟锡氧化物、铟锌氧化物中的1种或2种以上形成的单层或多层的电极。
电路基板的连接电极以外的部分优选被氧化硅、氮化硅、氮氧化硅、聚酰亚胺等的绝缘膜覆盖。
电路电极的凸电极的面积优选处于500μm2~10000μm2的范围,更优选处于1000μm2~5000μm2的范围。
本实施方式的带各向异性导电薄膜的半导体芯片优选在热压接前目视检查电路电极上的导电性颗粒数。通过目视检查,可以预先确认导电性颗粒的个数,并且还能够确认异物混入等的异常。
将本实施方式的带各向异性导电薄膜的半导体芯片与电路基板连接的情况下,连接后的电路电极上的每单位面积的导电性颗粒数优选为电路电极以外的部分的每单位面积的导电性颗粒数的65%以上、更优选为80%以上、进一步优选为90%以上。该导电性颗粒数若为65%以上,从不容易引发连接电极上的导电性颗粒的移动且容易取得连接性、绝缘性的平衡的方面来看是优选的。
本实施方式的带各向异性导电薄膜的半导体晶片具有一面(主表面的至少一侧)有多个电路电极的半导体晶片以及覆盖电路电极的各向异性导电薄膜(参照图6)。
本实施方式中,各向异性导电薄膜包含绝缘性树脂成分和导电性颗粒,该导电性颗粒在断面厚度方向不均匀分布。具体而言,导电性颗粒总数的60%以上、优选为70%以上、更优选为80%以上、进一步优选为90%以上存在于与半导体晶片的电路电极的平均高度相比为该各向异性导电薄膜的表面侧。其中,电路电极的平均高度是指半导体芯片断面中以未配置电路电极的部分为基准的、各电路电极的高度的平均。各向异性导电薄膜的表面侧是指各向异性导电薄膜断面中与半导体芯片接触侧的相反侧。若导电性颗粒总数的60%以上存在于与半导体晶片的电路电极的平均高度相比为该各向异性导电薄膜的表面侧,从连接电阻稳定化的方面来看是优选的。
各向异性导电薄膜的绝缘性树脂成分还可以包含固化性树脂、固化剂。
导电性颗粒可以与之前关于带各向异性导电薄膜的半导体芯片的描述中的相同。
另外,各向异性导电薄膜还可以进一步含有与之前关于带各向异性导电薄膜的半导体芯片的描述中的相同的绝缘颗粒、填充剂、软化剂、固化促进剂、稳定剂、着色剂、阻燃剂、流动调节剂、偶联剂等。
各向异性导电薄膜的、位于与电路电极平均高度相比为表面侧的绝缘性树脂成分的高度(厚度)可以与之前关于带各向异性导电薄膜的半导体芯片的描述中的相同。
如之前关于带各向异性导电薄膜的半导体芯片的描述,各向异性导电薄膜优选包含绝缘性粘接剂层、以及导电性颗粒在绝缘性树脂中大致平面状地分散排列1层而成的导电性颗粒层(参照图7)。
导电性颗粒层的绝缘性树脂的厚度可以与之前关于带各向异性导电薄膜的半导体芯片的描述中的相同。
本实施方式的各向异性导电薄膜中的导电性颗粒总数的比例也可以与之前关于带各向异性导电薄膜的半导体芯片的描述中的相同。另外,导电性颗粒优选从各向异性导电薄膜的表面露出,指示露出的每个颗粒的露出程度的露出高度也可以与之前关于带各向异性导电薄膜的半导体芯片的描述中的相同。
本实施方式所用的绝缘性粘接剂也可以与之前关于带各向异性导电薄膜的半导体芯片的描述中的相同。
另外,如之前关于带各向异性导电薄膜的半导体芯片的描述,出于赋予薄膜形成性、粘接性、固化时的应力松弛的目的,优选在绝缘性粘接剂中配合热塑性树脂,可使用的热塑性树脂固化剂等也可以与之前的描述相同。
导电性颗粒的分散排列也可以与之前关于带各向异性导电薄膜的半导体芯片的描述中的相同。
如之前关于带各向异性导电薄膜的半导体芯片的描述,导电性颗粒层包含导电性颗粒和绝缘性树脂,也可以含有固化性树脂、固化剂。
导电性颗粒层的绝缘性树脂成分的粘度也可以与之前关于带各向异性导电薄膜的半导体芯片的描述中的相同。
以下、本实施方式的带各向异性导电薄膜的半导体芯片可以通过在制造本实施方式的带各向异性导电薄膜的半导体晶片之后将其单片化(切出、切割)来制造,因而除去单片化工序,本实施方式的带各向异性导电薄膜的半导体晶片的制造方法可与之前关于带各向异性导电薄膜的半导体芯片的描述中的实质上相同。
本实施方式的带各向异性导电薄膜的半导体晶片优选在切割前目视检查电路电极上的导电性颗粒数。通过目视检查,可以预先确认导电性颗粒的个数,并且还能够确认异物混入等的异常。另外,通过特定异常部分,能够区分切割后的良品、不良品。此外,带各向异性导电薄膜的半导体晶片的不良位置多时,除去各向异性导电薄膜,再次贴附各向异性导电薄膜,由此能够减少半导体晶片的损耗。
本实施方式的半导体装置是包括一面有多个电路电极2的半导体芯片1、具有与该电路电极2对应的连接电极12的电路基板11、以及粘接剂10的半导体装置,该粘接剂10包含绝缘性树脂和导电性颗粒4、且被配置在该半导体芯片1与该电路基板11之间,该半导体芯片1上的距离最短的电路电极间的沿厚度方向切断的断面中,距半导体芯片最近的导电性颗粒与距半导体芯片最远的导电性颗粒的厚度方向的颗粒间距是该导电性颗粒的平均直径的1倍以下(参照图11)。
其中,距半导体芯片最近的导电性颗粒与距半导体芯片最远的导电性颗粒的厚度方向的颗粒间距是指自距半导体芯片最远的颗粒的中心起垂直于厚度方向所引的假想直线15与自距半导体芯片最近的颗粒的中心起垂直于厚度方向所引的假想直线16的距离(参照图11)。
本实施方式的半导体装置通过采取上述规定的导电性颗粒的配置,可靠性试验后的连接电阻、绝缘性优异。从该观点考虑,距半导体芯片最近的导电性颗粒与距半导体芯片最远的导电性颗粒的厚度方向的颗粒间距优选是该导电性颗粒的平均直径的0.9倍以下、更优选是0.8倍以下、进一步优选是0.5倍以下、特别优选为0.35倍以下。上述距离的最小值是0倍。
上述规定的半导体装置例如可以将一面有多个电路电极、且各向异性导电粘接薄膜中的导电性颗粒在断面厚度方向不均匀分布的带各向异性导电薄膜的半导体芯片与具有对应的连接电极的电路基板压接而得到。
电路电极可以与之前关于带各向异性导电薄膜的半导体芯片的描述中的相同。
导电性颗粒的平均直径必须小于所要连接的相邻电极间的距离,同时还优选大于需要连接的电子部件的电极高度的偏差。因此,导电性颗粒的平均直径优选为2.0μm以上且50μm以下的范围,更优选为2.5μm以上且40μm以下,进一步优选为3.0μm以上且35μm以下,特别优选为4.0μm以上且30μm以下。另外,导电性颗粒的粒径分布的标准偏差优选为平均直径的50%以下。
本实施方式的半导体装置中,指示粘接剂从半导体芯片外形溢出的量的、最大溢出长度优选为-20~50μm,更优选为-10~30μm,进一步优选为0~20μm。从电连接性以及机械连接性的观点考虑,该溢出长度优选为-20μm以上,而从操作性以及连接时的树脂溢出的观点来看优选为50μm以下。
本实施方式的半导体装置的、电路电极上的每单位面积的导电性颗粒数优选是电路电极以外的部分的每单位面积的导电性颗粒数的65%以上,更优选为80%以上,进一步优选为90%以上。该导电性颗粒数若为65%以上,从容易取得连接性、绝缘性的平衡的方面来看是优选的。
实施例
以下,通过实施例和比较例具体地说明本发明,但本发明不限于以下的实施例。
(半导体芯片的制作)
在横竖为1.6mm×15.1mm的硅片(厚度0.28mm)整面形成氧化膜,在距***部20μm的内侧沿每个长边侧以彼此间隔为2μm地形成480个横58μm、竖120μm的铝薄膜(厚度)。在这些铝薄膜上,为了以间隔为10μm地分别形成各2个横20μm、竖100μm的金凸块(厚度15μm),在距各个金凸块配置位置的外周部7μm的内侧留出横6μm、竖86μm的开口部,除此以外的部分形成包含氧化硅/氮化硅的厚度0.1μm的保护膜。然后,形成前述金凸块,制成半导体芯片。电路电极即金凸块的、以未配置电极的保护膜面为基准的平均高度为15.0μm。
(带各向异性导电薄膜的半导体芯片的检查评价)
检查性评价:使用显微镜由该带各向异性导电薄膜的晶片的各向异性导电薄膜表面计测金凸块上的导电性颗粒数。能够计测的评价为OK,不能计测的评价为NG。
检查结果评价:采用与上述同样的方法,对于50凸块份计测连接凸块上的导电性颗粒数,标准偏差/平均值小于0.3时评价为○、0.3以上时评价为×。
(捕获颗粒数评价)
对于压接后的金凸块上的导电性颗粒数与上述同样地测定50凸块份,算出它们的平均捕获颗粒数与连接前计测的连接凸块上的导电性颗粒数的比例。65%以上且小于90%时评价为○、90%以上时评价为◎、而小于65%时评价为×。
(连接电阻试验)
在厚度0.5mm的无碱玻璃上形成钽布线(0.8μm),使得能够以半导体芯片的铝薄膜上的金凸块与相邻的铝薄膜上的金凸块成对的位置关系进行连接,接着形成铟锡氧化物膜的连接焊盘(横42μm、竖120μm)。在每个能够连接20个金凸块的前述连接焊盘上形成铟锡氧化物薄膜的引线,引线上形成铝钛薄膜(钛1%、),制成连接评价基板。将该连接评价基板的连接焊盘与带各向异性导电薄膜的半导体芯片的金凸块对准位置、或者在将连接评价基板与各向异性导电薄膜预压接之后将连接评价基板的连接焊盘与半导体芯片的金凸块对准位置以190℃、10秒钟、40MPa的负荷进行压接,作成半导体装置。压接后,对于前述引线间(20个金凸块的串级链(daisychain))的电阻值使用四探针法的电阻表进行电阻测定,记作初始连接电阻值。85℃、85%RH的环境下将该连接电阻测定基板保持500小时,测定取出后25℃放置1小时后的连接电阻值,记作可靠性试验后连接电阻值。
(绝缘性试验评价)
在厚度0.5mm的无碱玻璃上,以能够分别连接半导体芯片的铝薄膜上的2个金凸块的位置关系形成钽布线(0.8μm),接着形成铟锡氧化物膜()的连接焊盘(横42μm、竖120μm)。以每个前述连接焊盘能够连接5个的方式形成铟锡氧化物薄膜的连接布线。在各个连接布线上形成铟锡氧化物薄膜的引线,在引线上形成铝钛薄膜(钛1%、)而制成绝缘性评价基板。将该绝缘电阻评价基板的连接焊盘与带各向异性导电薄膜的半导体芯片的金凸块对准位置、或者将连接评价基板与各向异性导电薄膜预压接之后将连接评价基板的连接焊盘与半导体芯片的金凸块对准位置以190℃、10秒钟、40MPa的负荷进行压接,制成绝缘电阻试验基板。边将该绝缘电阻试验基板保持为85℃、85%RH,边使用低电压低电流电源在成对的引线间施加30V的直流电压。每5分钟测定该布线间的绝缘电阻,测定直到绝缘电阻为10MΩ以下的时间,将该值记作绝缘下降时间。该绝缘下降时间小于500小时时评价为NG、500小时以上时评价为OK。
(位置对准性评价)
使用压接装置进行压接的过程中,出现对准标记读取错误时评价为NG、不出现错误时评价为OK。出现错误的情况下,反复进行操作,计测直到能够正常压接的次数。
(厚度方向的导电性颗粒间距的测定)
由上述连接电阻试验制作的半导体装置的电极之中,使用目标断面试样制作装置(LEICA制EM TXP)将电极间距离最窄、最靠近长边方向的中心的电极间沿厚度方向切断。用砂纸研磨至观察位置附近后,使用宽离子束(broad ion beam)装置(日立制作所制型号:E-3500)将所得到的断面平滑化。测定对象的切断面设定为在上述电极间包含5个以上的导电性颗粒的切断面。然后通过使用蒸镀装置(VACCUM DEVICE(真空デバイス)制型号:HPC-1s Osmium coat)在切断面蒸镀锇,进行导电化处理。断面观察采用扫描电子显微镜(日立制作所制型号:S-4700)。
测定电极间的、自距半导体芯片最远的颗粒的中心起垂直于厚度方向所引的假想直线与自距半导体芯片最近的颗粒的中心垂直于厚度方向所引的假想直线的距离,记作距半导体芯片最近的导电性颗粒与距半导体芯片最远的导电性颗粒的厚度方向的颗粒间距。距半导体芯片的距离视为该切断面中从导电性颗粒的中心落下至Si基板的垂线的长度。
[实施例1]
粘接层A
将苯氧树脂(玻璃化转变温度84℃、数均分子量9500)90g、双酚A型液态环氧树脂(环氧当量190、25℃粘度、14000mPa·s)10g、γ-(环氧丙氧基)丙基三乙氧基硅烷1.5g、以及乙酸乙酯250g混合,得到导电性颗粒层用绝缘性树脂清漆。将该导电性颗粒层用绝缘性树脂清漆涂布在厚度38μm的剥离处理了的聚对苯二甲酸乙二醇酯薄膜上,60℃下干燥15分钟,得到膜厚2.8μm的粘接层A。按照同样的方法制作粘度测定用的片,使用流变仪(60℃/分钟、升温)测定100℃粘度,结果为35000Pa·s。
绝缘性粘接剂层B
在乙酸乙酯-甲苯的混合溶剂(混合比1:1)中溶解苯氧树脂(玻璃化转变温度91℃、数均分子量11300)40g、双酚A型液态环氧树脂(环氧当量190、25℃粘度、14000mPa·s)10g、以及γ-(环氧丙氧基)丙基三乙氧基硅烷1.0g,制成固形分50%溶液。使含有微胶囊型潜伏性咪唑固化剂的液态环氧树脂(微胶囊的平均粒径5μm、活化温度123度、液态环氧树脂)50g(含有33.5g液态环氧树脂)混合分散在前述固形分50%溶液中。然后,将其涂布在厚度38μm的剥离处理了的聚对苯二甲酸乙二醇酯薄膜上,60℃鼓风干燥15分钟,得到厚度16μm的绝缘性粘接剂层B。按照同样的方法制作粘度测定用的片,使用流变仪(60℃/分钟、升温)测定100℃粘度,结果为450Pa·s。
导电性颗粒分散排列片C
在厚度100μm的未拉伸共聚聚丙烯薄膜上以4μm的厚度涂布丁腈胶乳-甲基丙烯酸甲酯的接枝共聚物粘接剂作为粘合层。在该带粘合层的聚丙烯薄膜上铺满平均直径3.8μm的镀金的塑料颗粒(丙烯酸类树脂、导电性颗粒),使得该粘接剂表面上导电性颗粒为多层,然后用软质橡胶形成的刮刀刮掉过剩的导电性颗粒,从而进行了基本无间隙的单层填充。填充率为80%。对于该薄膜使用双轴拉伸装置(东洋精机X6H-S、缩放仪方式的边角拉伸型的双轴拉伸装置)并用各10个夹具对横竖进行固定,125℃预热120秒,然后以10%/秒的速度进行2.4倍拉伸之后固定,得到导电性颗粒分散排列片C。使用显微镜测定导电性颗粒数,结果100μm×100μm的范围内的导电性颗粒数为134个。导电性颗粒的平均颗粒间隔为12.0μm,导电性颗粒大致正三角形地分散排列,聚集颗粒为0。
各向异性导电薄膜D
在上述导电性颗粒分散排列片C的导电性颗粒分散排列面上层压粘接层A,以80℃、0.4MPa的条件进行真空层压而制作导电性颗粒层,剥落聚对苯二甲酸乙二醇酯薄膜,在该剥离面上层压绝缘性粘接剂层B,以55℃、0.6MPa的条件进行真空层压,然后剥落聚对苯二甲酸乙二醇酯薄膜,得到各向异性导电薄膜D。
带各向异性导电薄膜的半导体芯片E
将上述半导体芯片的金凸块配置面侧真空层压(55℃、1.0MPa)于上述各向异性导电薄膜D的粘接层A侧,然后将各向异性导电薄膜连同半导体芯片从带粘合层的聚丙烯薄膜剥离,得到带各向异性导电薄膜的半导体芯片E。
对于带各向异性导电薄膜的半导体芯片E的各向异性导电薄膜的绝缘性树脂成分的厚度,使用激光显微镜进行测定,结果为18.8μm。另外,金凸块上的各向异性导电薄膜的绝缘性树脂成分的厚度为3.8μm。将该带各向异性导电薄膜的半导体芯片E冷冻切断,进行断面观察,对于50个导电性颗粒的位置状态进行确认。确认了50个之中50个位于与凸块的平均高度相比为表面侧。
[实施例2]
导电性颗粒层F
在厚度100μm的未拉伸共聚聚丙烯薄膜上以4μm的厚度涂布丁腈胶乳-甲基丙烯酸甲酯的接枝共聚物粘接剂作为粘合层。在该带粘合层的聚丙烯薄膜上铺满平均直径3.8μm的镀金的塑料颗粒(丙烯酸类树脂、导电性颗粒),使得该粘接剂表面上导电性颗粒为多层,然后用由软质橡胶形成的刮刀刮掉过剩的导电性颗粒,从而进行了基本无间隙的单层填充。填充率为80%。将苯氧树脂(玻璃化转变温度84℃、数均分子量9500)95g、双酚A型液态环氧树脂(环氧当量190、25℃粘度14000mPa·s)5g、以及γ-(环氧丙氧基)丙基三乙氧基硅烷1.2g、甲乙酮250g混合,得到导电性颗粒层用绝缘性树脂清漆。将该导电性颗粒层用绝缘性树脂清漆涂布在前述铺满了导电性颗粒的薄膜上,60℃干燥15分钟,得到厚度11μm的导电性颗粒填充薄膜。
对于前述导电性颗粒填充薄膜使用双轴拉伸装置(东洋精机X6H-S、缩放仪方式的边角拉伸型的双轴拉伸装置)并用各10个夹具对横竖进行固定,125℃预热120秒,然后以10%/秒的速度进行2.4倍拉伸之后固定,得到导电性颗粒层F。使用显微镜测定导电性颗粒数,结果100μm×100μm的范围内的导电性颗粒数为139个。导电性颗粒的平均颗粒间隔为12.0μm,导电性颗粒大致正三角形地分散排列,聚集颗粒为0。将该薄膜切断,使用电子显微镜测定导电性颗粒层F的绝缘性树脂的膜厚,结果为1.8μm。
带绝缘性粘接剂层的半导体芯片G
除了将膜厚设定为18μm以外,与实施例1同样地操作,制作绝缘性粘接剂层。
将该半导体芯片的金凸块配置面侧真空层压(55℃、1.0MPa)在该绝缘性粘接剂层上,然后将绝缘性粘接剂层连同半导体芯片从聚对苯二甲酸乙二醇酯薄膜剥离,去除多余的绝缘性粘接剂层,得到带绝缘性粘接剂层的半导体芯片G。
带各向异性导电薄膜的半导体芯片H
将带绝缘性粘接剂层的半导体芯片G的绝缘性粘接剂层面侧层压(55℃、1.0MPa)在导电性颗粒层F上,然后将导电性颗粒层连同带绝缘性粘接剂层的半导体芯片从带粘合层的聚丙烯薄膜剥离,得到带各向异性导电薄膜的半导体芯片H。
对于带各向异性导电薄膜的半导体芯片H的各向异性导电薄膜的绝缘性树脂成分的厚度,使用激光显微镜进行测定,结果为19.1μm。另外,金凸块上的各向异性导电薄膜的绝缘性树脂成分的厚度为4.1μm。将该带各向异性导电薄膜的半导体芯片H冷冻切断,进行断面观察,对于50个导电性颗粒的位置状态进行确认。确认了50个之中50个位于与凸块的平均高度相比为表面侧。
[实施例3]
除了将粘接层A的厚度设定为4.0μm以外,与实施例1同样地操作,得到带各向异性导电薄膜的半导体芯片I。
对于带各向异性导电薄膜的半导体芯片I的各向异性导电薄膜的绝缘性树脂成分的厚度,使用激光显微镜进行测定,结果为19.8μm。另外,金凸块上的各向异性导电薄膜的绝缘性树脂成分的厚度为4.8μm。将该带各向异性导电薄膜的半导体芯片I冷冻切断,进行断面观察,对于50个导电性颗粒的位置状态进行确认。确认了50个之中50个位于与凸块的平均高度相比为表面侧。
[实施例4]
带各向异性导电薄膜的半导体芯片J
除了将膜厚设定为19.5μm以外,与实施例2同样地操作,制作带绝缘性粘接剂层的半导体芯片,并真空层压(40℃、0.5MPa)在与实施例1同样地操作而制作的导电性颗粒分散排列片C上,然后将导电性颗粒连同带绝缘性粘接剂层的半导体芯片从带粘合层的聚丙烯薄膜剥离,得到带各向异性导电薄膜的半导体芯片J。
对于带各向异性导电薄膜的半导体芯片J的各向异性导电薄膜的绝缘性树脂成分的厚度,使用激光显微镜进行测定,结果为18.8μm。另外,金凸块上的各向异性导电薄膜的绝缘性树脂成分的厚度为3.8μm。使用显微镜由各向异性导电薄膜表面对于导电性颗粒从表面露出的露出量进行测定。测定50个导电性颗粒,结果它们全部露出,平均露出高度为0.3μm。
[比较例1]
除了将膜厚设定为19μm以外,将与实施例1同样地操作而制作的绝缘性粘接剂层层压(50℃、0.5MPa)在与实施例1同样地操作而制作的导电性颗粒分散排列片C上,得到各向异性导电薄膜K。将该各向异性导电薄膜K切开成1.6mm宽。以覆盖连接评价基板上的连接电极且导电性颗粒层被配置在基板侧的方式,将切开了的各向异性导电薄膜K以80℃、1秒、0.2MPa进行预压接。关于连接电阻试验、绝缘性试验评价,连接评价基板使用按照上述方法预压接而成的结构体、半导体芯片使用不带各向异性导电薄膜的半导体芯片,除此以外,采用与其他的实施例、比较例同样的条件、方法进行。
[比较例2]
在乙酸乙酯-甲苯的混合溶剂(混合比1:1)中溶解苯氧树脂(玻璃化转变温度91℃、数均分子量11300)40g、双酚A型液态环氧树脂(环氧当量190、25℃粘度、14000mPa·s)10g、以及γ-(环氧丙氧基)丙基三乙氧基硅烷1.0g,制成固形分50%溶液。使含有微胶囊型潜伏性咪唑固化剂的液态环氧树脂(微胶囊的平均粒径5μm、活化温度123度、液态环氧树脂)50g(含有33.5g液态环氧树脂)混合分散在前述固形分50%溶液中,得到各向异性导电薄膜用清漆。在该各向异性导电薄膜用清漆中以导电性颗粒密度为50000个/mm2的方式添加平均直径3.8μm的镀金的塑料颗粒(丙烯酸类树脂、导电性颗粒),涂布在厚度50μm的聚对苯二甲酸乙二醇酯薄膜上,60℃下干燥15分钟,得到膜厚20μm的各向异性导电薄膜L。
将该半导体芯片的金凸块配置面侧真空层压(55℃、1.0MPa)在该各向异性导电薄膜L上,然后将各向异性导电薄膜L连同半导体芯片从聚对苯二甲酸乙二醇酯薄膜剥离,去除多余的各向异性导电薄膜,得到带各向异性导电薄膜的半导体芯片M。
对于带各向异性导电薄膜的半导体芯片M的各向异性导电薄膜的绝缘性树脂成分的厚度,使用激光显微镜进行测定,结果为19.8μm。另外,金凸块上的各向异性导电薄膜的绝缘性树脂成分的厚度为4.8μm。将该半导体芯片M冷冻切断,进行断面观察。导电性颗粒在厚度方向基本上均匀分布。
[比较例3]
在各向异性导电薄膜用清漆中以导电性颗粒密度为10000个/mm2的方式添加平均直径3.8μm的镀金的塑料颗粒(丙烯酸类树脂、导电性颗粒),除此以外与比较例2同样地操作,得到各向异性导电薄膜N。将该半导体芯片的金凸块配置面侧真空层压(55℃、1.0MPa)在该各向异性导电薄膜N上,然后将各向异性导电薄膜N连同半导体芯片从聚对苯二甲酸乙二醇酯薄膜剥离,去除多余的各向异性导电薄膜,得到带各向异性导电薄膜的半导体芯片O。
对于带各向异性导电薄膜的半导体芯片O的各向异性导电薄膜的绝缘性树脂成分的厚度,使用激光显微镜进行测定,结果为19.7μm。另外,金凸块上的各向异性导电薄膜的绝缘性树脂成分的厚度为4.7μm。将该半导体芯片O冷冻切断,进行断面观察。导电性颗粒在厚度方向基本上均匀分布。
将各实施例、比较例的各项目的评价结果示于以下的表1。
[表1]
根据表1可知,关于各实施例所示的带各向异性导电薄膜的半导体芯片,半导体装置的厚度方向的导电性颗粒间距是导电性颗粒的平均直径的2倍以下,检查性、可靠性试验后的连接电阻、绝缘性试验评价结果、位置对准性均优异。
(半导体晶片的制作)
在直径6英寸、厚度0.28mm的硅片上整面地形成氧化膜,形成530个切出后的外形尺寸为横竖1.6mm×15.1mm的芯片。在各个芯片区域的距***部20μm的内侧沿每个长边侧以彼此间隔为2μm地形成480个横58μm、竖120μm的铝薄膜(厚度)。在这些铝薄膜上,为了以间隔为10μm地分别形成各2个横20μm、竖100μm的金凸块(厚度15μm),在距各个金凸块配置位置的外周部7μm的内侧留出横6μm、竖86μm的开口部,除此以外的部分形成包含氧化硅/氮化硅的厚度0.1μm的保护膜。然后,形成前述金凸块。然后,研磨至厚度0.28mm,在背面贴附切割薄膜(Lintec Corporation制、D-650),制成半导体晶片。电路电极即金凸块的、以未配置电极的保护膜面为基准的平均高度为15.0μm。
(切割性评价)
使用切割装置(DISCO公司制、DAD3350、刀具NBC ZH2060、30000rpm、切削速度50mm/s)以切出530个芯片(1.6mm×15.1mm)的方式对由各实施例制造的带各向异性导电薄膜的半导体晶片进行切割(切割薄膜中的进刀量、20μm)。将切割出的芯片作为评价用芯片。
外观评价:切出的芯片附着有切割屑的为5%以上时评价为×、5%以下时评价为○。
剥落评价:对切出的芯片的切割端面进行观察,各向异性导电薄膜从切割端面剥落的平均剥落量小于25μm时评价为○、25μm以上时评价为×。
(带各向异性导电薄膜的半导体晶片的检查评价)
检查性评价:使用显微镜由该带各向异性导电薄膜的晶片的各向异性导电薄膜表面计测金凸块上的导电性颗粒数。能够计测的评价为OK、不能计测的评价为NG。
检查结果评价:采用与上述同样的方法,对于50凸块份计测连接凸块上的导电性颗粒数,标准偏差/平均值小于0.3时评价为○、0.3以上时评价为×。
(捕获颗粒数评价)
对于压接后的金凸块上的导电性颗粒数与上述同样地测定50凸块份,算出它们的平均捕获颗粒数与连接前计测的连接凸块上的导电性颗粒数的比例。65%以上且小于90%时评价为○、90%以上时评价为◎、而小于65%时评价为×。
(连接电阻试验)
在厚度0.5mm的无碱玻璃上形成钽布线(0.8μm),使得能够以评价用芯片的铝薄膜上的金凸块与相邻的铝薄膜上的金凸块成对的位置关系进行连接,接着形成铟锡氧化物膜的连接焊盘(横42μm、竖120μm)。在每个能够连接20个金凸块的前述连接焊盘上形成铟锡氧化物薄膜的引线,引线上形成铝钛薄膜(钛1%、),制成连接评价基板。将该连接评价基板的连接焊盘与带各向异性导电薄膜的半导体芯片的金凸块对准位置以190℃、10秒钟、40MPa的负荷进行压接。压接后,对于前述引线间(20个金凸块的串级链)的电阻值使用四探针法的电阻表进行电阻测定,记作初始连接电阻值。85℃、85%RH的环境下将该连接电阻测定基板保持500小时,测定取出后25℃放置1小时后的连接电阻值,记作可靠性试验后电阻值。
(绝缘性试验评价)
在厚度0.5mm的无碱玻璃上,以能够分别连接评价用芯片的铝薄膜上的2个金凸块的位置关系形成钽布线(0.8μm),接着形成铟锡氧化物膜的连接焊盘(横42μm、竖120μm)。以每个前述连接焊盘能够连接5个的方式形成铟锡氧化物薄膜的连接布线。在各个连接布线上形成铟锡氧化物薄膜的引线,在引线上形成铝钛薄膜(钛1%、)而制成绝缘性评价基板。将该绝缘电阻评价基板的连接焊盘与带各向异性导电薄膜的半导体芯片的金凸块对准位置以190℃、10秒钟、40MPa的负荷进行压接,制成绝缘电阻试验基板。边将该绝缘电阻试验基板保持为85℃、85%RH,边使用低电压低电流电源在成对的引线间施加30V的直流电压。每5分钟测定该布线间的绝缘电阻,测定直到绝缘电阻为10MΩ以下的时间,将该值记作绝缘下降时间。该绝缘下降时间小于500小时时评价为NG、500小时以上时评价为OK。
(位置对准性评价)
使用压接装置进行压接的过程中,出现对准标记读取错误评价为NG、不出现错误时评价为OK。出现错误的情况下,反复进行操作,计测直到能够正常压接的次数。
[实施例5]
粘接层A
将苯氧树脂(玻璃化转变温度84℃、数均分子量9500)90g、双酚A型液态环氧树脂(环氧当量190、25℃粘度、14000mPa·s)10g、γ-(环氧丙氧基)丙基三乙氧基硅烷1.5g、以及乙酸乙酯250g混合,得到导电性颗粒层用绝缘性树脂清漆。将该导电性颗粒层用绝缘性树脂清漆涂布在厚度38μm的剥离处理了的聚对苯二甲酸乙二醇酯薄膜上,60℃下干燥15分钟,得到膜厚2.8μm的粘接层A。按照同样的方法制作粘度测定用的片,使用流变仪(60℃/分钟、升温)测定100℃粘度,结果为35000Pa·s。
绝缘性粘接剂层B
在乙酸乙酯-甲苯的混合溶剂(混合比1:1)中溶解苯氧树脂(玻璃化转变温度91℃、数均分子量11300)40g、双酚A型液态环氧树脂(环氧当量190、25℃粘度、14000mPa·s)10g、以及γ-(环氧丙氧基)丙基三乙氧基硅烷1.0g,制成固形分50%溶液。使含有微胶囊型潜伏性咪唑固化剂的液态环氧树脂(微胶囊的平均粒径5μm、活化温度123度、液态环氧树脂)50g(含有33.5g液态环氧树脂)混合分散在前述固形分50%溶液中。然后,将其涂布在厚度38μm的剥离处理了的聚对苯二甲酸乙二醇酯薄膜上,60℃鼓风干燥15分钟,得到厚度16μm的绝缘性粘接剂层B。按照同样的方法制作粘度测定用的片,使用流变仪(60℃/分钟、升温)测定100℃粘度,结果为450Pa·s。
导电性颗粒分散排列片C
在厚度100μm的未拉伸共聚聚丙烯薄膜上以4μm的厚度涂布丁腈胶乳-甲基丙烯酸甲酯的接枝共聚物粘接剂作为粘合层。在该带粘合层的聚丙烯薄膜上铺满平均直径3.8μm的镀金的塑料颗粒(丙烯酸类树脂、导电性颗粒),使得该粘接剂表面上导电性颗粒为多层,然后用软质橡胶形成的刮刀刮掉过剩的导电性颗粒,从而进行了基本无间隙的单层填充。填充率为80%。对于该薄膜使用双轴拉伸装置(东洋精机X6H-S、缩放仪方式的边角拉伸型的双轴拉伸装置)并用各10个夹具对横竖进行固定,125℃预热120秒,然后以10%/秒的速度进行2.4倍拉伸之后固定,得到导电性颗粒分散排列片C。使用显微镜测定导电性颗粒数,结果100μm×100μm的范围内的导电性颗粒数为134个。导电性颗粒的平均颗粒间隔为12.0μm,导电性颗粒大致正三角形地分散排列,聚集颗粒为0。
各向异性导电薄膜D
在上述导电性颗粒分散排列片C的导电性颗粒分散排列面上层压粘接层A,以80℃、0.4MPa的条件进行真空层压而制作导电性颗粒层,剥落聚对苯二甲酸乙二醇酯薄膜,在该剥离面上层压绝缘性粘接剂层B,以55℃、0.6MPa的条件进行真空层压,然后剥落聚对苯二甲酸乙二醇酯薄膜,得到各向异性导电薄膜D。
带各向异性导电薄膜的半导体晶片E
将上述半导体晶片的金凸块配置面侧真空层压(55℃、1.0MPa)在上述各向异性导电薄膜D上,然后将各向异性导电薄膜连同半导体晶片从带粘合层的聚丙烯薄膜剥离,得到带各向异性导电薄膜的半导体晶片E。
对于带各向异性导电薄膜的半导体晶片E的各向异性导电薄膜的绝缘性树脂成分的厚度,使用激光显微镜进行测定,结果为18.8μm。另外,金凸块上的各向异性导电薄膜的绝缘性树脂成分的厚度为3.8μm。将该带各向异性导电薄膜的半导体晶片E冷冻切断,进行断面观察,对于50个导电性颗粒的位置状态进行确认。确认了50个之中50个位于与凸块的平均高度相比为表面侧。
[实施例6]
导电性颗粒层F
在厚度100μm的未拉伸共聚聚丙烯薄膜上以4μm的厚度涂布丁腈胶乳-甲基丙烯酸甲酯的接枝共聚物粘接剂作为粘合层。在该带粘合层的聚丙烯薄膜上铺满平均直径3.8μm的镀金的塑料颗粒(丙烯酸类树脂、导电性颗粒),使得该粘接剂表面上导电性颗粒为多层,然后用由软质橡胶形成的刮刀刮掉过剩的导电性颗粒,从而进行了基本无间隙的单层填充。填充率为80%。将苯氧树脂(玻璃化转变温度84℃、数均分子量9500)95g、双酚A型液态环氧树脂(环氧当量190、25℃粘度14000mPa·s)5g、以及γ-(环氧丙氧基)丙基三乙氧基硅烷1.2g、甲乙酮250g混合,得到导电性颗粒层用绝缘性树脂清漆。将该导电性颗粒层用绝缘性树脂清漆涂布在前述铺满了导电性颗粒的薄膜上,60℃干燥15分钟,得到厚度11μm的导电性颗粒填充薄膜。
对于前述导电性颗粒填充薄膜使用双轴拉伸装置(东洋精机X6H-S、缩放仪方式的边角拉伸型的双轴拉伸装置)并用10个夹具对横竖进行固定,125℃预热120秒,然后以10%/秒的速度进行2.4倍拉伸之后固定,得到导电性颗粒层F。使用显微镜测定导电性颗粒数,结果100μm×100μm的范围内的导电性颗粒数为139个。导电性颗粒的平均颗粒间隔为12.0μm,导电性颗粒大致正三角形地分散排列,聚集颗粒为0。将该薄膜切断,使用电子显微镜测定导电性颗粒层F的绝缘性树脂的膜厚,结果为1.8μm。
带绝缘性粘接剂层的半导体晶片G
除了将膜厚设定为18μm以外,与实施例1同样地操作,制作绝缘性粘接剂层。
将该半导体晶片的金凸块配置面侧真空层压(55℃、1.0MPa)在该绝缘性粘接剂层上,然后将绝缘性粘接剂层连同半导体晶片从聚对苯二甲酸乙二醇酯薄膜剥离,去除多余的绝缘性粘接剂层,得到带绝缘性粘接剂层的半导体晶片G。
带各向异性导电薄膜的半导体晶片H
将带绝缘性粘接剂层的半导体晶片G的绝缘性粘接剂层面侧层压(55℃、1.0MPa)在导电性颗粒层F上,然后将导电性颗粒层连同带绝缘性粘接剂层的半导体晶片从带粘合层的聚丙烯薄膜剥离,得到带各向异性导电薄膜的半导体晶片H。
对于带各向异性导电薄膜的半导体晶片H的各向异性导电薄膜的绝缘性树脂成分的厚度,使用激光显微镜进行测定,结果为19.0μm。另外,金凸块上的各向异性导电薄膜的绝缘性树脂成分的厚度为4.0μm。将该带各向异性导电薄膜的半导体晶片H冷冻切断,进行断面观察,对于50个导电性颗粒的位置状态进行确认。确认了50个之中50个位于与凸块的平均高度相比为表面侧。
[实施例7]
除了将粘接层A的厚度设定为4.0μm以外,与实施例1同样地操作,得到带各向异性导电薄膜的半导体晶片I。
对于带各向异性导电薄膜的半导体晶片I的各向异性导电薄膜的绝缘性树脂成分的厚度,使用激光显微镜进行测定,结果为19.8μm。另外,金凸块上的各向异性导电薄膜的绝缘性树脂成分的厚度为4.8μm。将该带各向异性导电薄膜的半导体晶片I冷冻切断,进行断面观察,对于50个导电性颗粒的位置状态进行确认。确认了50个之中50个位于与凸块的平均高度相比为表面侧。
[实施例8]
带各向异性导电薄膜的半导体晶片J
除了将膜厚设定为19.5μm以外,与实施例2同样地操作,制作带绝缘性粘接剂层的半导体晶片,并真空层压(40℃、0.5MPa)在与实施例1同样地操作而制作的导电性颗粒分散排列片C上,然后将导电性颗粒连同带绝缘性粘接剂层的半导体晶片从带粘合层的聚丙烯薄膜剥离,得到带各向异性导电薄膜的半导体晶片J。
对于带各向异性导电薄膜的半导体晶片J的各向异性导电薄膜的绝缘性树脂成分的厚度,使用激光显微镜进行测定,结果为18.7μm。另外,金凸块上的各向异性导电薄膜的绝缘性树脂成分的厚度为3.7μm。使用显微镜由各向异性导电薄膜表面对于导电性颗粒从表面露出的露出量进行测定。测定50个导电性颗粒,结果它们全部露出,平均露出高度为0.25μm。
[比较例4]
在乙酸乙酯-甲苯的混合溶剂(混合比1:1)中溶解苯氧树脂(玻璃化转变温度91℃、数均分子量11300)40g、双酚A型液态环氧树脂(环氧当量190、25℃粘度、14000mPa·s)10g、以及γ-(环氧丙氧基)丙基三乙氧基硅烷1.0g,制成固形分50%溶液。使含有微胶囊型潜伏性咪唑固化剂的液态环氧树脂(微胶囊的平均粒径5μm、活化温度123度、液态环氧树脂)50g(含有33.5g液态环氧树脂)混合分散在前述固形分50%溶液中,得到各向异性导电薄膜用清漆。在该各向异性导电薄膜用清漆中以导电性颗粒密度为50000个/mm2的方式添加平均直径3.8μm的镀金的塑料颗粒(丙烯酸类树脂、导电性颗粒),涂布在厚度50μm的聚对苯二甲酸乙二醇酯薄膜上,60℃下干燥15分钟,得到膜厚20μm的各向异性导电薄膜K。
将该半导体晶片的金凸块配置面侧真空层压(55℃、1.0MPa)在该各向异性导电薄膜K上,然后将各向异性导电薄膜K连同半导体晶片从聚对苯二甲酸乙二醇酯薄膜剥离,去除多余的各向异性导电薄膜,得到带各向异性导电薄膜的半导体晶片L。
对于带各向异性导电薄膜的半导体晶片L的各向异性导电薄膜的绝缘性树脂成分的厚度,使用激光显微镜进行测定,结果为19.7μm。另外,金凸块上的各向异性导电薄膜的绝缘性树脂成分的厚度为4.7μm。将该半导体晶片L冷冻切断,进行断面观察。导电性颗粒在厚度方向基本上均匀分布而非不均匀分布。
[比较例5]
在各向异性导电薄膜用清漆中以导电性颗粒密度为10000个/mm2的方式添加平均直径3.8μm的镀金的塑料颗粒(丙烯酸类树脂、导电性颗粒),除此以外与比较例1同样地操作,得到各向异性导电薄膜M。将该半导体芯片的金凸块配置面侧真空层压(55℃、1.0MPa)在该各向异性导电薄膜M上,然后将各向异性导电薄膜M连同半导体晶片从聚对苯二甲酸乙二醇酯薄膜剥离,去除多余的各向异性导电薄膜,得到带各向异性导电薄膜的半导体晶片N。
对于带各向异性导电薄膜的半导体晶片N的各向异性导电薄膜的绝缘性树脂成分的厚度,使用激光显微镜进行测定,结果为19.8μm。另外,金凸块上的各向异性导电薄膜的绝缘性树脂成分的厚度为4.8μm。将该半导体晶片N冷冻切断,进行断面观察。导电性颗粒在厚度方向基本上均匀分布而非不均匀分布。
将各实施例、比较例的各项目的评价结果示于以下的表2。
[表2]
根据表2可知,关于各实施例所示的带各向异性导电薄膜的半导体晶片,检查性、切割性、可靠性试验后的连接电阻、绝缘性试验评价结果、位置对准性均优异。
产业上的可利用性
本发明可适合用于半导体芯片层压化连接、半导体芯片与中介层的连接等。
附图标记说明
1 半导体芯片
2 电路电极
3 各向异性导电薄膜
4 导电性颗粒
5 绝缘性粘接剂层
6 导电性颗粒层
7 支撑体
8 粘接剂层
9 半导体晶片
10 粘接剂
11 电路基板
12 连接电极
13 半导体元件部
14 Si基板
15 自距半导体芯片最远的颗粒的中心起垂直于厚度方向所引的假想直线
16 自距半导体芯片最近的颗粒的中心起垂直于厚度方向所引的假想直线
Claims (36)
1.一种带各向异性导电薄膜的半导体芯片,其特征在于,所述带各向异性导电薄膜的半导体芯片具有一面有多个电路电极的半导体芯片以及覆盖该电路电极的各向异性导电薄膜,该各向异性导电薄膜包含绝缘性树脂成分和导电性颗粒,并且该各向异性导电薄膜所含的导电性颗粒总数的60%以上存在于与该电路电极的平均高度相比为该各向异性导电薄膜的表面侧。
2.根据权利要求1所述的带各向异性导电薄膜的半导体芯片,其中,所述各向异性导电薄膜的、位于与所述电路电极的平均高度相比为表面侧的绝缘性树脂成分的高度是所述导电性颗粒的平均直径的1.0倍~2.0倍。
3.根据权利要求1或2所述的带各向异性导电薄膜的半导体芯片,其中,所述各向异性导电薄膜具有覆盖所述电路电极的绝缘性粘接剂层和导电性颗粒层,该导电性颗粒层是所述导电性颗粒在绝缘性树脂中大致平面状地分散排列1层而成的。
4.根据权利要求3所述的带各向异性导电薄膜的半导体芯片,其中,20℃~100℃的温度范围内,所述绝缘性粘接剂层的树脂成分的粘度低于所述导电性颗粒层的绝缘性树脂的粘度。
5.根据权利要求3或4所述的带各向异性导电薄膜的半导体芯片,其中,所述导电性颗粒层的绝缘性树脂的厚度是所述导电性颗粒的平均直径的0.4~2.0倍。
6.根据权利要求3~5中任一项所述的带各向异性导电薄膜的半导体芯片,其中,所述导电性颗粒层中的导电性颗粒总数的90%以上独立存在,相邻的导电性颗粒间的平均颗粒间距是该导电性颗粒的平均直径的1.0~20倍。
7.根据权利要求1~6中任一项所述的带各向异性导电薄膜的半导体芯片,其中,所述导电性颗粒总数的70%以上从所述各向异性导电薄膜的表面露出其一部分。
8.根据权利要求1~7中任一项所述的带各向异性导电薄膜的半导体芯片,其中,所述导电性颗粒是平均直径2~50μm的大致球状的颗粒,并且选自由塑料制颗粒被金属包覆而成的颗粒、金属颗粒、合金颗粒、以及金属制颗粒或合金制颗粒被金属或合金包覆而成的颗粒组成的组中。
9.根据权利要求1~8中任一项所述的带各向异性导电薄膜的半导体芯片,其中,从所述半导体芯片的外形溢出的所述各向异性导电薄膜的最大溢出长度为50μm以下。
10.一种权利要求1所述的带各向异性导电薄膜的半导体芯片的制造方法,其包括以下的工序:
将一面有多个电路电极的半导体芯片的该电路电极面层压在如下的层压体上的工序,所述层压体是支撑体、和导电性颗粒在断面厚度方向偏在于支撑体侧的各向异性导电薄膜层按该顺序层压而成的;以及
将该经过层压的该半导体芯片连同该各向异性导电薄膜层从该支撑体剥离的工序。
11.根据权利要求10所述的方法,其中,所述各向异性导电薄膜层具有绝缘性粘接剂层和导电性颗粒层,该导电性颗粒层是所述导电性颗粒在绝缘性树脂中大致平面状地分散排列1层而成的。
12.一种权利要求3所述的带各向异性导电薄膜的半导体芯片的制造方法,其包括以下的工序:
向一面有多个电路电极的半导体芯片的电路电极面填充绝缘性粘接剂的工序;
在所得到的带绝缘性粘接剂层的半导体芯片上层压导电性颗粒层的工序,所述导电性颗粒层形成在支撑体上且是导电性颗粒在绝缘性树脂中大致平面状地分散排列1层而成的;
将所述带绝缘性粘接剂层的半导体芯片连同所述导电性颗粒层从所述支撑体剥离的工序。
13.一种权利要求3所述的带各向异性导电薄膜的半导体芯片的制造方法,其包括以下的工序:
向一面有多个电路电极的半导体芯片的电路电极面填充绝缘性粘接剂的工序;
在所得到的带绝缘性粘接剂层的半导体芯片上层压导电性颗粒的工序,所述导电性颗粒是在层压于支撑体上的粘接剂层上分散排列而形成的;
将所述带绝缘性粘接剂层的半导体芯片连同所述导电性颗粒从层压于所述支撑体上的粘接剂层剥离的工序。
14.根据权利要求10~13中任一项所述的方法,其中,所述层压的工序中,20℃~100℃下进行真空层压。
15.一种半导体装置的制造方法,包括将权利要求1~9中任一项所述的带各向异性导电薄膜的半导体芯片的电路电极与具有对应的连接电极的电路基板对准位置来热压接的工序。
16.根据权利要求15所述的方法,包括在所述热压接的工序之前目视检查所述电路电极上的导电性颗粒数的工序。
17.一种由权利要求15或16所述的方法制造的半导体装置,其中,所述热压接后的所述连接电极上的每单位面积的导电性颗粒数为所述电路电极以外的部分的每单位面积的导电性颗粒数的65%以上。
18.一种带各向异性导电薄膜的半导体晶片,其特征在于,所述带各向异性导电薄膜的半导体晶片具有一面有多个电路电极的半导体晶片以及覆盖该电路电极的各向异性导电薄膜,该各向异性导电薄膜包含绝缘性树脂成分和导电性颗粒,并且该各向异性导电薄膜所含的导电性颗粒总数的60%以上存在于与该电路电极的平均高度相比为该各向异性导电薄膜的表面侧。
19.根据权利要求18所述的带各向异性导电薄膜的半导体晶片,其中,所述各向异性导电薄膜的、位于与所述电路电极的平均高度相比为表面侧的绝缘性树脂成分的高度是所述导电性颗粒的平均直径的1.0倍~2.0倍。
20.根据权利要求18或19所述的带各向异性导电薄膜的半导体晶片,其中,所述各向异性导电薄膜具有覆盖所述电路电极的绝缘性粘接剂层和导电性颗粒层,该导电性颗粒层是所述导电性颗粒在绝缘性树脂中大致平面状地分散排列1层而成的。
21.根据权利要求20所述的带各向异性导电薄膜的半导体晶片,其中,20℃~100℃的温度范围内,所述绝缘性粘接剂层的树脂成分的粘度低于所述导电性颗粒层的绝缘性树脂的粘度。
22.根据权利要求20或21所述的带各向异性导电薄膜的半导体晶片,其中,所述导电性颗粒层的绝缘性树脂的厚度是所述导电性颗粒的平均直径的0.4~2.0倍。
23.根据权利要求20~22中任一项所述的带各向异性导电薄膜的半导体晶片,其中,所述导电性颗粒层中的导电性颗粒总数的90%以上独立存在,相邻的导电性颗粒间的平均颗粒间距是该导电性颗粒的平均直径的1.0~20倍。
24.根据权利要求18~23中任一项所述的带各向异性导电薄膜的半导体晶片,其中,所述导电性颗粒总数的70%以上从所述各向异性导电薄膜的表面露出其一部分。
25.根据权利要求18~24中任一项所述的带各向异性导电薄膜的半导体晶片,其中,所述导电性颗粒是平均直径2~50μm的大致球状的颗粒,并且选自由塑料制颗粒被金属包覆而成的颗粒、金属颗粒、合金颗粒、以及金属制颗粒或合金制颗粒被金属或合金包覆而成的颗粒组成的组中。
26.一种权利要求18所述的带各向异性导电薄膜的半导体晶片的制造方法,其包括以下的工序:
将一面有多个电路电极的半导体晶片的该电路电极面层压在如下的层压体上的工序,所述层压体是支撑体、和导电性颗粒在断面厚度方向偏在于支撑体侧的各向异性导电薄膜层按该顺序层压而成的;以及
将该经过层压的该半导体晶片连同该各向异性导电薄膜层从该支撑体剥离的工序。
27.根据权利要求26所述的方法,其中,所述各向异性导电薄膜层具有绝缘性粘接剂层和导电性颗粒层,该导电性颗粒层是所述导电性颗粒在绝缘性树脂中大致平面状地分散排列1层而成的。
28.一种权利要求20所述的带各向异性导电薄膜的半导体晶片的制造方法,其包括以下的工序:
向一面有多个电路电极的半导体晶片的电路电极面填充绝缘性粘接剂的工序;
在所得到的带绝缘性粘接剂层的半导体晶片上层压导电性颗粒层的工序,所述导电性颗粒层形成在支撑体上且是导电性颗粒在绝缘性树脂中大致平面状地分散排列1层而成的;
将所述带绝缘性粘接剂层的半导体晶片连同所述导电性颗粒层从所述支撑体剥离的工序。
29.一种权利要求20所述的带各向异性导电薄膜的半导体晶片的制造方法,其包括以下的工序:
向一面有多个电路电极的半导体晶片的电路电极面填充绝缘性粘接剂的工序;
在所得到的带绝缘性粘接剂层的半导体晶片上层压导电性颗粒的工序,所述导电性颗粒是在层压于支撑体上的粘接剂层上分散排列而形成的;
将所述带绝缘性粘接剂层的半导体晶片连同所述导电性颗粒从层压于所述支撑体上的粘接剂层剥离的工序。
30.根据权利要求26~29中任一项所述的方法,其中,所述层压的工序中,20℃~100℃下进行真空层压。
31.一种带各向异性导电薄膜的半导体芯片的制造方法,包括切割权利要求18~25中任一项所述的带各向异性导电薄膜的半导体晶片的工序。
32.根据权利要求31所述的方法,其中,包括在切割所述带各向异性导电薄膜的半导体晶片的工序之前目视检查所述电路电极上的导电性颗粒数的工序。
33.一种半导体装置,该半导体装置包括一面有多个电路电极的半导体芯片、具有与该电路电极对应的连接电极的电路基板、以及粘接剂,该粘接剂包含绝缘性树脂和导电性颗粒、且被配置在该半导体芯片与该电路基板之间,该半导体芯片上的距离最短的电路电极间的沿着厚度方向切断的断面中,距半导体芯片最近的导电性颗粒与距半导体芯片最远的导电性颗粒的厚度方向的颗粒间距是该导电性颗粒的平均直径的1倍以下。
34.根据权利要求33所述的半导体装置,其中,所述导电性颗粒是平均直径2~50μm的大致球状的颗粒,且选自由塑料制颗粒被金属包覆而成的颗粒、金属颗粒、合金颗粒、以及金属制颗粒或合金制颗粒被金属或合金包覆而成的颗粒组成的组中。
35.根据权利要求33或34所述的半导体装置,其中,从所述半导体芯片的外形溢出的所述粘接剂的最大溢出长度为50μm以下。
36.根据权利要求33~35中任一项所述的半导体装置,其中,所述热压接后的所述连接电极上的每单位面积的导电性颗粒数为所述电路电极以外的部分的每单位面积的导电性颗粒数的65%以上。
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Cited By (4)
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CN107221770A (zh) * | 2017-05-10 | 2017-09-29 | 武汉华星光电技术有限公司 | 连接器、连接器的制作方法、连接组件及面板组件 |
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1132931A (zh) * | 1994-12-30 | 1996-10-09 | 卡西欧计算机公司 | 连接一个电子元件的端子到另一个电子元件的端子的方法 |
CN1185859A (zh) * | 1995-05-22 | 1998-06-24 | 日立化成工业株式会社 | 具有与布线基板电连接的半导体芯片的半导体器件 |
CN1289453A (zh) * | 1998-12-02 | 2001-03-28 | 精工爱普生株式会社 | 各向异性导电膜和半导体芯片的安装方法以及半导体装置 |
US20070295943A1 (en) * | 2005-02-22 | 2007-12-27 | Cheil Industries Inc. | Polymer Particles and Conductive Particles Having Enhanced Conducting Properties, and Anisotropic Conductive Packaging Materials Containing the Same |
CN101601171A (zh) * | 2007-07-03 | 2009-12-09 | 索尼化学&信息部件株式会社 | 各向异性导电膜和其制造方法以及接合体 |
US20110121243A1 (en) * | 2006-09-26 | 2011-05-26 | Hitachi Chemical Company, Ltd. | Anisotropic conductive adhesive composition, anisotropic conductive film, circuit member connecting structure and method for manufacturing coated particles |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4574631B2 (ja) * | 1996-08-06 | 2010-11-04 | 日立化成工業株式会社 | マルチチップ実装法 |
JPH10125725A (ja) * | 1996-10-18 | 1998-05-15 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP3684886B2 (ja) * | 1998-12-17 | 2005-08-17 | セイコーエプソン株式会社 | 半導体チップの実装構造、液晶装置及び電子機器 |
JP2007217503A (ja) * | 2006-02-15 | 2007-08-30 | Asahi Kasei Electronics Co Ltd | 異方導電性接着フィルム |
KR100838647B1 (ko) * | 2007-07-23 | 2008-06-16 | 한국과학기술원 | Acf/ncf 이중층을 이용한 웨이퍼 레벨 플립칩패키지의 제조방법 |
JP5192194B2 (ja) * | 2007-07-26 | 2013-05-08 | デクセリアルズ株式会社 | 接着フィルム |
JP2009147231A (ja) * | 2007-12-17 | 2009-07-02 | Hitachi Chem Co Ltd | 実装方法、半導体チップ、及び半導体ウエハ |
-
2012
- 2012-12-13 CN CN201280061980.5A patent/CN103988289A/zh active Pending
- 2012-12-13 WO PCT/JP2012/082413 patent/WO2013089199A1/ja active Application Filing
- 2012-12-13 KR KR1020147015696A patent/KR20140100511A/ko not_active Application Discontinuation
- 2012-12-13 JP JP2013549317A patent/JPWO2013089199A1/ja active Pending
- 2012-12-14 TW TW101147680A patent/TWI541958B/zh active
-
2015
- 2015-05-15 JP JP2015100484A patent/JP2015159333A/ja active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1132931A (zh) * | 1994-12-30 | 1996-10-09 | 卡西欧计算机公司 | 连接一个电子元件的端子到另一个电子元件的端子的方法 |
CN1185859A (zh) * | 1995-05-22 | 1998-06-24 | 日立化成工业株式会社 | 具有与布线基板电连接的半导体芯片的半导体器件 |
CN1289453A (zh) * | 1998-12-02 | 2001-03-28 | 精工爱普生株式会社 | 各向异性导电膜和半导体芯片的安装方法以及半导体装置 |
US20070295943A1 (en) * | 2005-02-22 | 2007-12-27 | Cheil Industries Inc. | Polymer Particles and Conductive Particles Having Enhanced Conducting Properties, and Anisotropic Conductive Packaging Materials Containing the Same |
US20110121243A1 (en) * | 2006-09-26 | 2011-05-26 | Hitachi Chemical Company, Ltd. | Anisotropic conductive adhesive composition, anisotropic conductive film, circuit member connecting structure and method for manufacturing coated particles |
CN101601171A (zh) * | 2007-07-03 | 2009-12-09 | 索尼化学&信息部件株式会社 | 各向异性导电膜和其制造方法以及接合体 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106170852A (zh) * | 2014-02-27 | 2016-11-30 | 迪睿合株式会社 | 连接体、连接体的制造方法及检查方法 |
CN109155259A (zh) * | 2016-05-27 | 2019-01-04 | 富士胶片株式会社 | 各向异性导电材料、电子元件、包含半导体元件的结构体及电子元件的制造方法 |
CN109155259B (zh) * | 2016-05-27 | 2023-02-28 | 富士胶片株式会社 | 电子元件、包含半导体元件的结构体及电子元件的制造方法 |
CN107221770A (zh) * | 2017-05-10 | 2017-09-29 | 武汉华星光电技术有限公司 | 连接器、连接器的制作方法、连接组件及面板组件 |
CN115388786A (zh) * | 2022-08-08 | 2022-11-25 | 安徽承禹半导体材料科技有限公司 | 一种碲锌镉晶片损伤层厚度的检测方法 |
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