CN102130057A - Method for making complementary metal oxide semiconductor device, and structure of complementary metal oxide semiconductor device - Google Patents
Method for making complementary metal oxide semiconductor device, and structure of complementary metal oxide semiconductor device Download PDFInfo
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Abstract
The invention discloses a method for making a complementary metal oxide semiconductor device. The method can be used for making a complementary metal oxide semiconductor device provided with a double lining layer and a bimetal front dielectric layer, and optimizes the overall performance of the semiconductor device. The invention also discloses a complementary metal oxide semiconductor device which is provided with a double lining layer and a bimetal front dielectric layer. The complementary metal oxide semiconductor device has an obvious effect on improving the carrier mobility.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly have the method and structure of CMOS (complementary metal oxide semiconductors (CMOS)) device of two backing layers and bimetallic front medium layer (PMD).
Background technology
Hot carrier is the charge carrier with high-energy, high drift velocity, the important effect that it showed, that is and, hot carrier's effect mainly contains two aspects.The nonlinear speed of the first-electric field relation: the charge carrier among the Si presents the drift velocity saturated phenomenon when high electric field, and Here it is because the result of hot carrier transmitting optics wave sound (about 0.05eV); Electronics among the GaAs promptly transits to time energy valley from main energy valley when by electric field " heating " (Te is so-called hot carrier temperature) when energy kTe reaches 0.21eV, thereby produces negative resistance phenomenon.It two is ionization by collision effects: hot electron and lattice collisions are also broken valence link, a kind of effect that promptly valence electron is energized into conduction band and produces electron-hole pair, ionization by collision need satisfy the energy and the conservation of momentum, energy needed Ei ≈ 2 Eg/2, the degree of ionization by collision can represent that α and electric field E have exponential relationship with so-called ionization rate α: and α=A exp (Ei/kTe)=A exp is (B/E).
Hot carrier's effect in mos field effect transistor (MOSFET) device is caused by the high electric field of locating near the raceway groove end of source/leakage diffusion region.That is, through the High-Field zone time, require the electronics of macro-energy, can produce electron hole pair, thereby cause high electric leakage of the grid and early stage gate oxide to puncture by injecting hot carrier to gate material layers via gate oxide by for example ionization by collision.As further result, in gate medium, also exist clean negative charge density.Captive electric charge is accumulated in time, causes the positive threshold drift in the nmos pass transistor, or the drift of the negative threshold value in the PMOS transistor.
Because hot electron is than the easier migration of hot hole, so hot carrier's effect causes bigger threshold value to tilt in nmos pass transistor than in the PMOS transistor.Even so, if the transistorized length of effective channel of PMOS less than for example 0.8 micron, the PMOS transistor will experience negative threshold value and tilt.Present Standard Thin gate oxide (for example greater than 1.5 nanometers) more is subject to the hot carrier degradation influence, because hot carrier trends towards accumulating in oxide in time.Thereby some application for being exclusively used in such as the integrated circuit of input/output circuitry can have some devices to be formed with thicker gate oxide (for example logic OR analog circuit transistor) with respect to other device on this chip on the single chip.
The method of known minimizing Hot-carrier Degradation Effects comprises the impurity that adds such as nitrogen, fluorine and chlorine in gate oxide.Yet because impurity (as nitrogen) trends towards the surperficial localization at film, it is more not obvious to thicker gate oxide effect to add impurity.And, also may be accompanied by undesirable effect to the direct nitriding of gate oxide, as the degeneration of electron mobility.
The disclosed another kind of technology that is used to improve the device lifetime that is caused by hot carrier's effect is to use deuterium annealing.By by the hydrogen in the deuterium exchange standard interface passivation anneal step, the life-span of nmos device can be improved about 10～100 times.Yet, must could effectively carry out deuterium annealing at sufficiently high temperature (for example more than 500 degrees centigrade), this may cause the dopant deexcitation that causes device degradation.
Recently, introduced two lining technologies, so that the stress different with respect to nmos device to be provided, thereby improved the hot carrier's effect in the cmos device in P MOS device.For example, above the PMOS of COMS device, form the first nitrogen oxide lining, and above the NMOS of cmos device, form the second nitrogen oxide lining.More specifically, have been found that the application improvement carrier mobility wherein of the compression in the PMOS raceway groove, and the charge carrier that the application of the tensile stress in the NMOS raceway groove improves wherein moves mobility.Thereby first nitride liner of PMOS device top forms according to the mode that realizes compression, and second nitride liner of nmos device top forms according to the mode that realizes tensile stress.U.S. Pat 7,288,451 B2 disclose structure and the method that a kind of making is used for two stressed liner of cmos device.
The method of traditional making cmos device is shown in Figure 1A to 1H.
Shown in Figure 1A, provide a substrate 101, a pair of exemplary cmos device that this substrate 101 has formation thereon and separated each other by shallow trench 102, i.e. PMOS device 103 and the nmos device 104 common cmos devices that constitute.The gate oxide 105A of PMOS device 103 and the gate oxide 105B of nmos device 104 are formed in the substrate 101, high k material layer 106A and 106B are formed at respectively on gate oxide 105A and the gate oxide 105B, gate material layers 107A and 107B are formed at respectively on high k material layer 106A and the 106B, and gate material layers can be but be not limited to polysilicon.Carry out after the shallow injection technology, form clearance wall insulating barrier 109A, 109A ', 109B, 109B ' and clearance wall 110A, 110A ', 110B, 110B ' respectively at gate material layers 107A and 107B sidewall.Then carry out ion implantation technology, form source/drain electrode 111A, the 111A ' of PMOS device 103 and source/drain electrode 111B, the 111B ' of nmos device 104 respectively, and source/drain electrode 111A, the 111A ' of PMOS device 103 carried out correspondingly silicification technics.
Shown in Figure 1B, above total, form tensile stress nitride layer 113, described tensile stress nitride for example adopts the Si of BTBAS (two tertiary butyl aminopropyl silane) precursor deposition
3N
4, thickness can be 500～1000 dusts.
Shown in Fig. 1 C, above tensile stress nitride layer 113, form thick oxide layers 114, thickness is at least 1000 dusts, is preferably 5000 dusts.Coating one deck photoresist layer 115 is to cover nmos device 104 districts (promptly exposing PMOS device 103 districts) on thick oxide layers 114.
Shown in Fig. 1 D, be etching barrier layer with thick oxide layers 114, can adopt reactive ion etching (RIE), remove a part of thick oxide layers 114 and the tensile stress nitride layer 113 that expose top, PMOS device 103 districts.
Shown in Fig. 1 E, remove photoresist layer 115, above total, form compression nitride layer 116 then, can be by depositing or plasma enhanced chemical vapor deposition (PECVD), with for example SiH at about 200～500 degrees centigrade of following high-density plasmas (HDP)
4, NH
2, N
2Mist form compression nitride layer 116 as source gas.
Shown in Fig. 1 F, above total, form oxide skin(coating) 117, its thickness can be 50～100 dusts.
Shown in Fig. 1 G, coating one deck photoresist layer 118 above oxide skin(coating) 117 is to cover PMOS device 103 districts.Then, remove the oxide skin(coating) 117 that covers top, nmos device 104 districts by reactive ion etching method earlier, adopting isotropically etching then, is that etching stop layer is removed the compression nitride layer 116 that covers above nmos device 104 districts with thick oxide layers 114.
Shown in Fig. 1 H, remove photoresist layer 118 in the ashing mode, then adopt the reactive ion etching method to remove remaining oxide skin(coating) 117 and remaining thick oxide layers 114.Next carry out follow-up CMOS technology.
Can see by above-mentioned processing step, deposit tensile stress nitride layer and compression nitride layer as backing layer in the zones of different of cmos device.For the cmos device of the two backing layers of this employing, conventional method is to adopt independently two kinds of different nitride of lithographic patterning step formation.That is, for example above PMOS and nmos device, form the nitride liner layer of the first kind, tensile stress nitride layer for example, the part of the nitride liner layer of the first kind above the PMOS device is patterned and removes subsequently.After optionally oxide skin(coating) forms, above two zones, form second nitride liner, for example the compression nitride layer uses second patterning step to remove the second nitride liner part of nmos device top subsequently.Generally speaking, will deposit layer of oxide layer between two kinds of different nitride layers, and during to this layer oxide layer etching, what use usually is reactive ion etching, and reactive ion etching technology can increase the cost of making.And, in follow-up technology, can on total, deposit interlayer dielectric layer, for example before-metal medium layer (PMD) usually.Because what total adopted is the interlayer dielectric layer with uniform pressure, this can weaken the effectiveness of the nitride layer with stress.That is,, can weaken the effect of the compression nitride layer of PMOS device region if the total employing is the tensile stress interlayer dielectric layer; If what total adopted is the compression interlayer dielectric layer, can weaken the effect of the tensile stress nitride layer in nmos device district.Such result can cause improving the DeGrain of carrier mobility.
In addition, above-mentioned technology also can be brought another problem.When making semiconductor device, can deposit different retes by the different parts on the device of total usually.For example, need be at A position deposition S
1, S
2, S
2... S
nThe tunic structure, and need deposit T at the B position
1, T
2, T
2... T
nDuring layer structure, the simplest way is to cover the position that does not need depositional coating with photoresist, deposit successively at the position that needs depositional coating then, but this is restricted on actual process.This is because in actual process, and depositing of thin film generally occurs under 400 degrees centigrade the condition, and photoresist can not bear this temperature for a long time.Promptly, if will not need the figuratum photoresist of apparatus to cover the position that does not need depositional coating, deposit successively at the position that needs depositional coating then, if this moment, the rete of deposition was too much, overlong time, the photoresist with pattern can deform, and this may make the place deposition that does not need depositional coating go up rete, and the place that needs depositional coating does not have rete, and this has just reduced the yields of semiconductor device.In addition, the rete that covers above the photoresist film is not easy to remove very much, and this can increase production cost.
Therefore, need a kind of method, can have the interlayer dielectric layer of required stress, reduce cost of manufacture, improve the yields of device at different area depositions.
Summary of the invention
Introduced the notion of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The problem that occurs when solving existing making complementary mos device the invention provides a kind of method of making complementary mos device, and described wind is sent out and comprised the following steps:
A: provide first device and with the second opposite device of the described first device polarity type, described first device has the first grid material layer, described second device has the second grid material layer, and described first grid material layer is concordant with the top of described second grid material layer;
B: on described first device and described second device, form first stressor layers;
C: on described first stressor layers, form first before-metal medium layer;
D: remove described first stressor layers of part and described first before-metal medium layer of part, till exposing described first grid material layer and described second grid material layer, make the top of remaining described first stressor layers and remaining described first before-metal medium layer concordant with the top of described second grid material layer with described first grid material layer;
E: patterning is also removed described first stressor layers of part of described second device top and described first before-metal medium layer of part of described second device top;
F: above described remaining described first before-metal medium layer, described first stressor layers, described first grid material layer and described second device, form second stressor layers;
G: on described second stressor layers, form second before-metal medium layer;
H: patterning is also removed described second stressor layers of part of described first device top and described second before-metal medium layer of part of described first device top, remove described second before-metal medium layer of part and described second stressor layers of part of described second device top, till exposing described first grid material layer and described second grid material layer, make the top of remaining described second before-metal medium layer and remaining described second stressor layers concordant with the top of described second grid material layer.
Preferably, also comprise the following steps,
I: remove described first grid material layer and described second grid material layer;
J: on second device of first device of removing described first grid material layer and the described second grid material layer of removal, form the first metal layer;
K: patterning is also removed the described the first metal layer of part above first device of the described first grid material layer of described removal;
L: formation second metal level on first device of remaining described the first metal layer and the described first grid material layer of described removal;
M: on described second metal level, form metal electrode layer;
N: described second metal level of part and the described remaining described the first metal layer of part of described second metal level of part of first device top of the described metal electrode layer of removal part, the described first grid material layer of described removal, second device top of the described second grid material layer of described removal make the top of the top of the top of remaining described metal electrode layer, described remaining described the first metal layer, described remaining second metal level all concordant with described remaining described second before-metal medium layer with described remaining described first before-metal medium layer.
Preferably, described first before-metal medium layer and second before-metal medium layer are selected from tensile stress before-metal medium layer or compression before-metal medium layer.
Preferably, described first stressor layers and second stressor layers are selected from tensile stress nitride layer or compression nitride layer, for example silicon nitride.
Preferably, described first device and second device are selected from nmos device or PMOS device.
Preferably, the described the first metal layer and second metal level are selected from work function and are applicable to the metal of NMOS or the metal that work function is applicable to PMOS.
Preferably, the material of described metal electrode layer is chosen as aluminum or aluminum alloy.
Another aspect of the present invention provides a kind of complementary mos device, comprises,
First device and with the second opposite device of the described first device polarity type, described first device has the first grid material layer, described second device has the second grid material layer, and described first grid material layer is concordant with the top of described second grid material layer; Form be set forth on first device and first stressor layers that the top is concordant with the top of described first grid material layer; Be formed at first before-metal medium layer on described first stressor layers, the top of described first before-metal medium layer is concordant with the top of described first grid material layer; Form be set forth on second device and second stressor layers that the top is concordant with the top of described second grid material layer; Be formed at second before-metal medium layer on described second stressor layers, the top of described second before-metal medium layer is concordant with the top of described second grid material layer.
Preferably, also comprise,
The first metal layer that on the position of having removed described second grid material layer, forms, the top of described the first metal layer is concordant with the top of described second before-metal medium layer;
Second metal level that on described the first metal layer, forms, the top of described second metal level is concordant with the top of the first metal layer;
First metal electrode layer that on described second metal level, forms, the top of described first metal electrode layer is concordant with the top of second metal level;
Described second metal level that on the position of having removed described first grid material layer, forms, the top of described second metal level is concordant with the top of described first before-metal medium layer;
Described second metal electrode layer that forms on described second metal level, described two metal electrode layers are concordant with the top of first before-metal medium layer.
Preferably, described first before-metal medium layer and described second before-metal medium layer are selected from tensile stress before-metal medium layer or compression before-metal medium layer.
Preferably, described first stressor layers and described second stressor layers are selected from tensile stress nitride layer or compression nitride layer, for example silicon nitride.
Preferably, described first device and described second device are selected from nmos device or PMOS device.
Preferably, described the first metal layer and described second metal level are selected from work function and are applicable to the metal of NMOS or the metal that work function is applicable to PMOS.
Preferably, the material of described first metal electrode layer and described second metal electrode layer is chosen as aluminum or aluminum alloy.
Description of drawings
Following accompanying drawing of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A to Fig. 1 H is the generalized section that traditional fabrication has the cmos device of two backing layers;
Fig. 2 A to 2K has the cross-sectional view of the cmos device of two backing layers and bimetallic front medium layer according to making of the present invention;
Fig. 3 A to 3C makes according to the cross-section structure process chart with cmos device of two backing layers and bimetallic front medium layer of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example,, be not described for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that how explanation the present invention makes the cmos device with two backing layers and bimetallic front medium layer.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
Cmos device comprises first stressor layers and first before-metal medium layer that first device top forms, with second stressor layers that above second device, forms and second before-metal medium layer, first stressor layers and second stressor layers have constituted two backing layers, and first before-metal medium layer and second before-metal medium layer have constituted the bimetallic front medium layer.With reference to Fig. 2 A to Fig. 2 K, show the cross-sectional view that has the cmos device 200 of two backing layers and bimetallic front medium layer according to making of the present invention.
Shown in Fig. 2 A, provide a substrate 201, a pair of cmos device 200 that constitutes jointly by PMOS device 203 and nmos device 204 that this substrate 201 has formation thereon and separated each other by shallow trench 202.Form one deck gate dielectric layer 205 with the CVD method in substrate 201, material can be selected but be not limited to contain silicon oxynitride, SiON for example, and thickness is 4～8 dusts.Then, form a floor height k material layer 206 in the CVD mode on gate dielectric layer 205, material can be chosen as but be not limited to HfO
x, HfSiO
x, HfSiNO
x, HfZrO
x, thickness is greater than being 5～25 dusts.Then, deposit the thin metal nitride layer 207 of one deck in the CVD mode on high k material layer 206, material can be selected but be not limited to TiN, and thickness is approximately 5～50 dusts.Thin metal nitride layer 207 can reduce the problem of the gate depletion that takes place in the use of high k material layer 206 and the stacked structure of the gate material layers 208 that next will deposit.Then, deposit one deck gate material layers 208 in the CVD mode on thin metal nitride layer 207, thickness is approximately 400～1000 dusts.
Shown in Fig. 2 B, coating one deck photoresist (not shown) on gate material layers 208, by forming photoresist (not shown) after the means such as exposure imaging with pattern, adopt reactive ion etching or wet etching method that gate dielectric layer 205, high k material layer 206, thin metal nitride layer 207 and gate material layers 208 are carried out etching, form the first grid 280A in PMOS device 203 zones and the second grid 280B in nmos device 204 zones.First grid 280A comprises first grid dielectric layer 205A, the first high k material layer 206A, first thin metal nitride layer 207A and the first grid material layer 208A; Equally, second grid 280B comprises the second gate dielectric layer 205B, the second high k material layer 206B, second thin metal nitride layer 207B and the second grid material layer 208B.First grid material layer 208A is concordant with the top of second grid material layer 208B.
Shown in Fig. 2 C, on the sidewall of first grid 280A, form first clearance wall insulating barrier 209A and the 209A ', on the sidewall of second grid 280B, form second clearance wall insulating barrier 209B and the 209B '.Then, on the sidewall of the first clearance wall insulating barrier 209A and 209A ', form first gap parietal layer 210A and the 210A ' respectively, on the sidewall of the second clearance wall insulating barrier 209B and 209B ', form second gap parietal layer 210B and the 210B ' respectively in the CVD mode.Then carry out ion implantation technology, form source/drain electrode 211A, the 211A ' of PMOS device 203 and source/drain electrode 211B, the 211B ' of nmos device 204 respectively, and technology such as the activation of annealing.Alternatively, the epitaxial growth selectively of silicon germanium material (not shown) can be advanced the source/drain electrode 211A and the 211A ' in PMOS device 203 zones, and keep the source/drain electrode 211B and the 211B ' in nmos device 204 zones not to contain SiGe.Alternatively, can also carry out the technology (not shown) such as formation of metal silicide, for example the formation of NiSi.
Shown in Fig. 2 D, then deposit one deck tensile stress nitride layer 212, for example the Si of silicon nitride or the two tertiary butyl aminopropyl silane precursor depositions of employing BTBAS in the PECVD mode
3N
4, thickness can be 300～1000 dusts.Then, with CVD mode plated metal front medium layer (PMD) 213, material is chosen as the tensile stress before-metal medium layer on tensile stress nitride layer 212, and thickness is approximately 500～8000 dusts.Select for use high density plasma CVD (HDPCVD) or subatmospheric chemical vapour deposition (CVD) (SACVD) mode to form the tensile stress before-metal medium layer, used tensile stress before-metal medium layer material includes but not limited to phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).
Shown in Fig. 2 E, remove unnecessary before-metal medium layer 213 and tensile stress nitride layer 212 until exposing first grid 280A and second grid 280B in the CMP mode, form the first tensile stress before-metal medium layer 213 ', make the top of the first tensile stress before-metal medium layer 213 ', tensile stress nitride layer 212 concordant, and expose first grid material layer 208A and second grid material layer 208B with the top of first grid 280A, second grid 280B.
Shown in Fig. 2 F, at the first tensile stress before-metal medium layer, 213 ' top coating photoresist layer 214, and expose and technology such as development so that photoresist layer 214 covers nmos devices 204 districts, expose PMOS device 203 districts.Carry out reactive ion etching, remove the first tensile stress before-metal medium layer 213 ' and tensile stress nitride layer 212 above PMOS device 203 districts.
Shown in Fig. 2 G, remove photoresist layer 214.Deposit compression nitride layer 215 in the PECVD mode on total, material can be but be not limited to silicon nitride that thickness is approximately 250～600 dusts.Deposition compression before-metal medium layer 216 on compression nitride layer 215, thickness is approximately 250～6000 dusts.Select for use HDPCVD and SACVD method to form the compression before-metal medium layer, used compression before-metal medium layer material includes but not limited to PSG and BPSG.
Shown in Fig. 2 H, carry out CMP technology, remove compression before-metal medium layer 216 and compression nitride layer 215 floor above nmos device 204 districts, make the top of 215 layers of compression before-metal medium layers 216, compression nitride layer concordant with the top of first grid material layer 208A, form the second compression before-metal medium layer 216 ', expose first grid material layer 208A and second grid material layer 208B.
Shown in Fig. 2 I, remove first grid material layer 208A and second grid material layer 208B.Deposition one deck the first metal layer 217 on total, material is chosen as the metal level that work function is applicable to PMOS.Can be used for forming the material that work function is applicable to the metal level of PMOS and comprise ruthenium, titanium, palladium, platinum, cobalt, nickel and conducting metal oxide, also comprise for example TiN.The thickness of the first metal layer 217 is approximately 25～300 dusts.The generation type of the first metal layer 217 can be known PVD or CVD mode.On the first metal layer 217 coating one deck photoresist layer (not shown) and expose and technology such as development so that the photoresist layer (not shown) covers the PMOS device.Remove the top the first metal layer 217 in nmos device 204 districts with the method for reactive ion etching.
Shown in Fig. 2 J, deposition second metal level 218 on total, material is chosen as the metal level that work function is applicable to NMOS.Work function is applicable to that the material of the metal level of NMOS can include but not limited to: hafnium, zirconium, titanium, tantalum, aluminium and alloy thereof, the metal carbides that for example comprise these elements, be hafnium carbide, zirconium carbide, titanium carbide, ramet and aluminium carbide, can also comprise it for example being TiAlN and TaC.Second metal level 218 can form with known PVD (physical vapour deposition (PVD)) or CVD method.Then deposit layer of metal electrode layer 219 with CVD or PVD mode on second metal level 218, material can be but be not limited to aluminum or aluminum alloy.
Shown in Fig. 2 K, carry out CMP technology, remove unnecessary metal electrode layer 219, second metal level 218 and the first metal layer 217, make the top of the first metal electrode layer 219A and the first metal layer 217 concordant with the top of the second compression before-metal medium layer 216 ', make the top of the second metal electrode layer 219B and second metal level 218 concordant, finish the making of whole C MOS device architecture with the top of the first tensile stress before-metal medium layer 213 '.
The cmos device of making according to the present invention combines two backing layers, high k material and " grid are last " technology, and has the before-metal medium layer of different stress.The PMD that the method for traditional making CMOS is deposited on NMOS and PMOS is the PMD of same type, promptly only has the PMD of tensile stress or compression.And the CMOS that the method according to this invention is made, has the tensile stress before-metal medium layer at nmos area, has the compression before-metal medium layer in the PMOS district, cooperate corresponding separately tensile stress nitride layer and compression nitride layer, can improve carrier mobility better, optimize whole structure, strengthened the effect of each position stress.
The flow chart of Fig. 3 shows making according to the cross-section structure technological process with cmos device of two backing layers (tensile stress nitride layer and compression nitride layer) and bimetallic front medium layer (the first tensile stress before-metal medium layer and the second compression before-metal medium layer) of the present invention.In step 301, provide a substrate, a pair of cmos device that constitutes jointly by PMOS device and nmos device that this substrate has formation thereon and separated each other by shallow trench.In step 302, in substrate, form one deck gate dielectric layer, on gate dielectric layer, form a floor height k material layer, on high k material layer, form the thin metal nitride layer of one deck, on thin metal nitride layer, form one deck gate material layers.In step 303, coating one deck photoresist on gate material layers, by forming photoresist after the means such as exposure imaging with pattern, gate dielectric layer, high k material layer, thin metal nitride layer and gate material layers are carried out etching, form the first grid of PMOS device area and the second grid in nmos device zone.In step 304, on the sidewall of first grid, form the first clearance wall insulating barrier, on the sidewall of second grid, form the second clearance wall insulating barrier.In step 305, on the sidewall of the first clearance wall insulating barrier, form first clearance wall, on the sidewall of the second clearance wall insulating barrier, form second clearance wall.Then carry out ion implantation technology, form the source/drain electrode of PMOS device and the source/drain electrode of nmos device respectively.In step 306, silicon germanium material selectively is filled into the source/drain electrode of PMOS device area, and keeps the source/drain electrode in nmos device zone not contain SiGe.Deposition one deck tensile stress nitride layer, deposition tensile stress before-metal medium layer on the tensile stress nitride layer then on total.In step 307, remove unnecessary before-metal medium layer and tensile stress nitride layer, form the first tensile stress before-metal medium layer, make its top concordant, and expose first grid material layer and second grid material layer with the top of first grid and second grid.In step 308, at first tensile stress before-metal medium layer top coating photoresist layer, promptly cover the nmos device district, expose the PMOS device region, remove the first tensile stress before-metal medium layer and tensile stress nitride layer above the PMOS device region.In step 309, remove photoresist layer.Deposition compression nitride layer on total, deposition compression metal level on the compression nitride layer.In step 310, form the second compression before-metal medium layer, expose first grid material layer and second grid material layer.In step 311, remove first grid material layer and second grid material layer.In step 312, on total, deposit the first metal layer, coating one deck photoresist layer and remove the first metal layer above the nmos device district on the first metal layer on the PMOS device region.In step 313, deposition one deck second metal level on total, and on second metal level, deposit the layer of metal electrode layer.In step 314, remove unnecessary metal electrode layer, second metal level and the first metal layer, make the top of first metal electrode layer, second metal level, the first metal layer and the second compression before-metal medium layer concordant, make second metal electrode layer, second metal level, the first tensile stress before-metal medium layer three's top concordant, finish the making of whole C MOS device architecture.
Semiconductor device according to the cmos device with two backing layers and bimetallic front medium layer of aforesaid embodiment manufacturing can be applicable in the multiple integrated circuit (IC).According to IC of the present invention for example is logical device, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM) or other circuit devcies arbitrarily.According to IC of the present invention can also be memory circuitry, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.IC chip according to the present invention can be used for for example consumer electronic products, in various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated by the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (16)
1. a method of making complementary mos device comprises the following steps:
A: provide first device and with the second opposite device of the described first device polarity type, described first device has the first grid material layer, described second device has the second grid material layer, and described first grid material layer is concordant with the top of described second grid material layer;
B: on described first device and described second device, form first stressor layers;
C: on described first stressor layers, form first before-metal medium layer;
D: remove described first stressor layers of part and described first before-metal medium layer of part, till exposing described first grid material layer and described second grid material layer, make the top of remaining described first stressor layers and remaining described first before-metal medium layer concordant with the top of described second grid material layer with described first grid material layer;
E: patterning is also removed described first stressor layers of part of described second device top and described first before-metal medium layer of part of described second device top;
F: above described remaining described first before-metal medium layer, described first stressor layers, described first grid material layer and described second device, form second stressor layers;
G: on described second stressor layers, form second before-metal medium layer;
H: patterning is also removed described second stressor layers of part of described first device top and described second before-metal medium layer of part of described first device top, remove described second before-metal medium layer of part and described second stressor layers of part of described second device top, till exposing described first grid material layer and described second grid material layer, make the top of remaining described second before-metal medium layer and remaining described second stressor layers concordant with the top of described second grid material layer.
2. the method for claim 1 also comprises the following steps,
I: remove described first grid material layer and described second grid material layer;
J: on second device of first device of removing described first grid material layer and the described second grid material layer of removal, form the first metal layer;
K: patterning is also removed the described the first metal layer of part above first device of the described first grid material layer of described removal;
L: formation second metal level on first device of remaining described the first metal layer and the described first grid material layer of described removal;
M: on described second metal level, form metal electrode layer;
N: described second metal level of part and the described remaining described the first metal layer of part of described second metal level of part of first device top of the described metal electrode layer of removal part, the described first grid material layer of described removal, second device top of the described second grid material layer of described removal make the top of the top of the top of remaining described metal electrode layer, described remaining described the first metal layer, described remaining second metal level all concordant with described remaining described second before-metal medium layer with described remaining described first before-metal medium layer.
3. method according to claim 1 and 2 is characterized in that, described first before-metal medium layer and second before-metal medium layer are selected from tensile stress before-metal medium layer or compression before-metal medium layer.
4. method according to claim 1 and 2 is characterized in that, described first stressor layers and second stressor layers are selected from tensile stress nitride layer or compression nitride layer.
5. method according to claim 1 and 2 is characterized in that, described first device and second device are selected from nmos device or PMOS device.
6. method according to claim 2 is characterized in that, the described the first metal layer and second metal level are selected from work function and are applicable to the metal of NMOS or the metal that work function is applicable to PMOS.
7. method according to claim 2 is characterized in that the material of described metal electrode layer is chosen as aluminum or aluminum alloy.
8. a complementary mos device comprises,
First device and with the second opposite device of the described first device polarity type, described first device has the first grid material layer, described second device has the second grid material layer, and described first grid material layer is concordant with the top of described second grid material layer; Form be set forth on first device and first stressor layers that the top is concordant with the top of described first grid material layer; Be formed at first before-metal medium layer on described first stressor layers, the top of described first before-metal medium layer is concordant with the top of described first grid material layer; Form be set forth on second device and second stressor layers that the top is concordant with the top of described second grid material layer; Be formed at second before-metal medium layer on described second stressor layers, the top of described second before-metal medium layer is concordant with the top of described second grid material layer.
9. device as claimed in claim 8 also comprises,
The first metal layer that on the position of having removed described second grid material layer, forms, the top of described the first metal layer is concordant with the top of described second before-metal medium layer;
Second metal level that on described the first metal layer, forms, the top of described second metal level is concordant with the top of the first metal layer;
First metal electrode layer that on described second metal level, forms, the top of described first metal electrode layer is concordant with the top of second metal level;
Described second metal level that on the position of having removed described first grid material layer, forms, the top of described second metal level is concordant with the top of described first before-metal medium layer;
Described second metal electrode layer that forms on described second metal level, described two metal electrode layers are concordant with the top of first before-metal medium layer.
10. according to Claim 8 or 9 described devices, it is characterized in that described first before-metal medium layer and described second before-metal medium layer are selected from tensile stress before-metal medium layer or compression before-metal medium layer.
11. according to Claim 8 or 9 described devices, it is characterized in that described first stressor layers and described second stressor layers are selected from tensile stress nitride layer or compression nitride layer.
12. according to Claim 8 or 9 described devices, it is characterized in that described first device and described second device are selected from nmos device or PMOS device.
13. device according to claim 9 is characterized in that, described the first metal layer and described second metal level are selected from work function and are applicable to the metal of NMOS or the metal that work function is applicable to PMOS.
14. device according to claim 9 is characterized in that, the material of described first metal electrode layer and described second metal electrode layer is chosen as aluminum or aluminum alloy.
15. an integrated circuit that comprises the semiconductor device of the method for claim 1 manufacturing, described integrated circuit is selected from random access memory, dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC) and buried type DRAM, radio-frequency devices.
16. an electronic equipment that comprises the semiconductor device of the method for claim 1 manufacturing, wherein said electronic equipment is selected from personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103871890A (en) * | 2012-12-18 | 2014-06-18 | 中芯国际集成电路制造(上海)有限公司 | MOS (metal oxide semiconductor) transistor and forming method thereof |
| CN107275404A (en) * | 2011-09-30 | 2017-10-20 | 英特尔公司 | Tungsten grid for non-planar transistors |
| US9947772B2 (en) | 2014-03-31 | 2018-04-17 | Stmicroelectronics, Inc. | SOI FinFET transistor with strained channel |
| CN107919323A (en) * | 2016-10-10 | 2018-04-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US10438856B2 (en) | 2013-04-03 | 2019-10-08 | Stmicroelectronics, Inc. | Methods and devices for enhancing mobility of charge carriers |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040256700A1 (en) * | 2003-06-17 | 2004-12-23 | International Business Machines Corporation | High-performance CMOS devices on hybrid crystal oriented substrates |
| US20060033977A1 (en) * | 2003-02-12 | 2006-02-16 | Patel Satyadev R | Micromirror device |
| US20060071285A1 (en) * | 2004-09-29 | 2006-04-06 | Suman Datta | Inducing strain in the channels of metal gate transistors |
| CN1812101A (en) * | 2004-11-08 | 2006-08-02 | 国际商业机器公司 | Compensated metal oxide semiconductor and forming method thereof |
| CN101064310A (en) * | 2006-04-28 | 2007-10-31 | 国际商业机器公司 | CMOS structures and methods using self-aligned dual stressed layers |
| CN101388399A (en) * | 2007-09-14 | 2009-03-18 | 国际商业机器公司 | Metal oxide semiconductor junction using hybrid orientation and method for manufacturing same |
-
2010
- 2010-01-14 CN CN 201010022890 patent/CN102130057B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060033977A1 (en) * | 2003-02-12 | 2006-02-16 | Patel Satyadev R | Micromirror device |
| US20040256700A1 (en) * | 2003-06-17 | 2004-12-23 | International Business Machines Corporation | High-performance CMOS devices on hybrid crystal oriented substrates |
| US20060071285A1 (en) * | 2004-09-29 | 2006-04-06 | Suman Datta | Inducing strain in the channels of metal gate transistors |
| CN1812101A (en) * | 2004-11-08 | 2006-08-02 | 国际商业机器公司 | Compensated metal oxide semiconductor and forming method thereof |
| CN101064310A (en) * | 2006-04-28 | 2007-10-31 | 国际商业机器公司 | CMOS structures and methods using self-aligned dual stressed layers |
| CN101388399A (en) * | 2007-09-14 | 2009-03-18 | 国际商业机器公司 | Metal oxide semiconductor junction using hybrid orientation and method for manufacturing same |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107275404A (en) * | 2011-09-30 | 2017-10-20 | 英特尔公司 | Tungsten grid for non-planar transistors |
| CN103871890A (en) * | 2012-12-18 | 2014-06-18 | 中芯国际集成电路制造(上海)有限公司 | MOS (metal oxide semiconductor) transistor and forming method thereof |
| CN103871890B (en) * | 2012-12-18 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Mos transistor and forming method thereof |
| US10438856B2 (en) | 2013-04-03 | 2019-10-08 | Stmicroelectronics, Inc. | Methods and devices for enhancing mobility of charge carriers |
| US10546789B2 (en) | 2013-04-03 | 2020-01-28 | Stmicroelectronics, Inc. | Methods of forming metal-gate semiconductor devices with enhanced mobility of charge carriers |
| US10553497B2 (en) | 2013-04-03 | 2020-02-04 | Stmicroelectronics, Inc. | Methods and devices for enhancing mobility of charge carriers |
| US9947772B2 (en) | 2014-03-31 | 2018-04-17 | Stmicroelectronics, Inc. | SOI FinFET transistor with strained channel |
| US10804377B2 (en) | 2014-03-31 | 2020-10-13 | Stmicroelectronics, Inc. | SOI FinFET transistor with strained channel |
| US11495676B2 (en) | 2014-03-31 | 2022-11-08 | Stmicroelectronics, Inc. | SOI FinFET transistor with strained channel |
| CN107919323A (en) * | 2016-10-10 | 2018-04-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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|---|---|
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