CN107910325B - 一种外部pmos触发scr-ldmos结构的esd防护器件 - Google Patents
一种外部pmos触发scr-ldmos结构的esd防护器件 Download PDFInfo
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- CN107910325B CN107910325B CN201710975122.6A CN201710975122A CN107910325B CN 107910325 B CN107910325 B CN 107910325B CN 201710975122 A CN201710975122 A CN 201710975122A CN 107910325 B CN107910325 B CN 107910325B
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- 230000001681 protective effect Effects 0.000 title description 2
- 238000002347 injection Methods 0.000 claims description 170
- 239000007924 injection Substances 0.000 claims description 170
- 239000002184 metal Substances 0.000 claims description 134
- 238000002955 isolation Methods 0.000 claims description 73
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 49
- 229920005591 polysilicon Polymers 0.000 claims description 49
- 210000000746 body region Anatomy 0.000 claims description 20
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 230000009024 positive feedback mechanism Effects 0.000 abstract description 5
- 230000008901 benefit Effects 0.000 abstract description 3
- 230000007246 mechanism Effects 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 abstract 1
- 238000002513 implantation Methods 0.000 description 35
- 239000007943 implant Substances 0.000 description 7
- 238000012423 maintenance Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710975122.6A CN107910325B (zh) | 2017-10-19 | 2017-10-19 | 一种外部pmos触发scr-ldmos结构的esd防护器件 |
Applications Claiming Priority (1)
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CN201710975122.6A CN107910325B (zh) | 2017-10-19 | 2017-10-19 | 一种外部pmos触发scr-ldmos结构的esd防护器件 |
Publications (2)
Publication Number | Publication Date |
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CN107910325A CN107910325A (zh) | 2018-04-13 |
CN107910325B true CN107910325B (zh) | 2020-07-24 |
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CN201710975122.6A Active CN107910325B (zh) | 2017-10-19 | 2017-10-19 | 一种外部pmos触发scr-ldmos结构的esd防护器件 |
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Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN111312710B (zh) * | 2020-04-03 | 2024-04-26 | 欧跃半导体(西安)有限公司 | 一种低残压低容值的esd器件及制备方法 |
CN111968970B (zh) * | 2020-08-28 | 2022-04-08 | 电子科技大学 | 一种esd保护器件 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105489603A (zh) * | 2016-01-06 | 2016-04-13 | 江南大学 | 一种pmos触发ldmos-scr结构的高维持电压esd保护器件 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6764892B2 (en) * | 2001-09-05 | 2004-07-20 | Texas Instruments Incorporated | Device and method of low voltage SCR protection for high voltage failsafe ESD applications |
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2017
- 2017-10-19 CN CN201710975122.6A patent/CN107910325B/zh active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105489603A (zh) * | 2016-01-06 | 2016-04-13 | 江南大学 | 一种pmos触发ldmos-scr结构的高维持电压esd保护器件 |
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Application publication date: 20180413 Assignee: NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS INSTITUTE AT NANTONG Co.,Ltd. Assignor: NANJING University OF POSTS AND TELECOMMUNICATIONS Contract record no.: X2020980006914 Denomination of invention: An ESD protection device with scr-ldmos structure triggered by external PMOS Granted publication date: 20200724 License type: Common License Record date: 20201021 |
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EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20180413 Assignee: NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS NANTONG INSTITUTE Co.,Ltd. Assignor: NANJING University OF POSTS AND TELECOMMUNICATIONS Contract record no.: X2021980011448 Denomination of invention: An ESD protection device with scr-ldmos structure triggered by external PMOS Granted publication date: 20200724 License type: Common License Record date: 20211027 |