CN107887328B - Array substrate, manufacturing method thereof and OLED structure - Google Patents

Array substrate, manufacturing method thereof and OLED structure Download PDF

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CN107887328B
CN107887328B CN201610865955.2A CN201610865955A CN107887328B CN 107887328 B CN107887328 B CN 107887328B CN 201610865955 A CN201610865955 A CN 201610865955A CN 107887328 B CN107887328 B CN 107887328B
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CN107887328A (en
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孟哲宇
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Kunshan Govisionox Optoelectronics Co Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Abstract

The invention discloses an array substrate, a manufacturing method thereof and an OLED structure. In the array substrate, the manufacturing method thereof and the OLED structure provided by the invention, the first electrode layer and the second electrode layer of the capacitor structure are made of porous graphene materials, so that the capacitor density is increased, the area of a capacitor area is reduced, the wiring space is conveniently increased, and high PPI can be better realized; the second electrode layer and the grid metal layer form a double-grid structure, so that leakage current is reduced, and the quality of the array substrate is improved.

Description

Array substrate, manufacturing method thereof and OLED structure
Technical Field
The invention relates to the field of display, in particular to an array substrate, a manufacturing method thereof and an OLED structure.
Background
With the development of the information society, the demand of people for display devices is increasing. Flexible displays are becoming more and more popular with people due to their features of being light and thin, bendable or even curled, and good mechanical properties. At present, flexible displays are increasingly used in life. The flexible display includes a flexible Liquid Crystal Display (LCD) and a flexible organic light emitting diode display (OLED). Flexible displays are usually fabricated on flexible carriers, which have many special user experiences due to their inherent flexible characteristics, and also present significant challenges to their design and fabrication.
At present, flexible displays with high PPI have been a necessary trend for development, which requires the size of each pixel to be smaller and smaller, and the wiring space of the pixel circuit to be smaller, however, the capacitance occupies the largest space in the pixel circuit, which is not favorable for obtaining high PPI. Therefore, how to reduce the space occupied by the capacitor (i.e., reduce the area of the capacitor region) while ensuring the capacitance value becomes an important research direction.
Disclosure of Invention
The invention aims to provide an array substrate, a manufacturing method thereof and an OLED structure, which can reduce the area of a capacitance area and realize high PPI flexible display.
Another object of the present invention is to reduce leakage current while achieving high PPI flexible display.
It is yet another object of the present invention to reduce voltage drop by using full-faced power supply voltage traces.
In order to solve the above technical problem, the present invention provides a method for manufacturing an array substrate, including:
providing a substrate;
sequentially forming a first electrode layer, a first dielectric layer and a second electrode layer on the substrate to obtain a capacitor structure, wherein the first electrode layer and the second electrode layer are both made of porous graphene; and
and sequentially forming a second dielectric layer, a polycrystalline silicon layer, a third dielectric layer and a grid metal layer on the second electrode layer.
Optionally, for the manufacturing method of the array substrate, the step of obtaining the capacitor structure includes:
forming a first graphene material layer by adopting a chemical vapor deposition process;
photoetching and etching the first graphene material layer, and irradiating by adopting laser to form the first electrode layer;
forming a second insulating layer around the first electrode layer, wherein the second insulating layer is flush with the upper surface of the first electrode layer;
forming a first dielectric layer by adopting a chemical vapor deposition process;
forming a second graphene material layer on the first medium layer by adopting a chemical vapor deposition process;
and photoetching and etching the first graphene material layer, and irradiating by adopting laser to form the second electrode layer.
Optionally, in the manufacturing method of the array substrate, the first dielectric layer is made of polyimide and has a thickness of 5 μm to 10 μm.
Optionally, for the manufacturing method of the array substrate, after providing a substrate and before obtaining the capacitor structure, the method further includes:
forming a layer of whole first metal layer on the substrate as a power supply voltage wire;
a first insulating layer is formed on the first metal layer.
Optionally, in the manufacturing method of the array substrate, the first metal layer is made of molybdenum and has a thickness of molybdenum
Figure BDA0001124512630000021
Optionally, in the manufacturing method of the array substrate, an opening is formed in the insulating layer, and the first electrode layer fills the opening and is connected to the first metal layer.
Optionally, for the manufacturing method of the array substrate, the step of sequentially forming a second dielectric layer, a polysilicon layer, a third dielectric layer and a gate metal layer on the second electrode layer includes:
forming a second dielectric layer by adopting a chemical vapor deposition process, and covering the first dielectric layer and the second electrode layer;
removing part of the second dielectric layer on one side of the second electrode layer by a photoetching process;
forming an opening, wherein the opening is formed at one side of the second dielectric layer, penetrates through the first dielectric layer, the second insulating layer and the first insulating layer and exposes the first metal layer;
forming a polycrystalline silicon layer by adopting a chemical vapor deposition process, wherein the polycrystalline silicon layer fills the opening, is connected with the first metal layer, and is positioned on the first dielectric layer on one side of the opening and part of the second dielectric layer above the capacitor structure;
forming a third dielectric layer by adopting a chemical vapor deposition process, wherein the third dielectric layer covers the polycrystalline silicon layer and is combined with the second dielectric layer above the capacitor structure to seal the polycrystalline silicon layer;
and forming a grid metal layer by adopting a physical vapor deposition process, wherein the grid metal layer is formed on the third dielectric layer above the capacitor structure.
Optionally, for the manufacturing method of the array substrate, after a second dielectric layer, a polysilicon layer, a third dielectric layer, and a gate metal layer are sequentially formed on the second electrode layer, the method further includes:
forming a fourth dielectric layer to cover the third dielectric layer, the gate metal layer and the second dielectric layer;
forming a covering layer to cover the fourth dielectric layer;
and forming a second metal layer, wherein the second metal layer penetrates through the covering layer, the fourth dielectric layer, the third dielectric layer and the second dielectric layer to be connected with the second electrode layer.
The present invention also provides an array substrate formed by the method as described above, the array substrate including:
a substrate;
the capacitor structure comprises a first electrode layer, a second electrode layer and a first dielectric layer positioned between the first electrode layer and the second electrode layer, wherein the first electrode layer and the second electrode layer are made of porous graphene materials;
and forming a second dielectric layer, a polysilicon layer, a third dielectric layer and a gate metal layer which are partially laminated on the second electrode layer in sequence.
The present invention also provides an OLED structure comprising:
the array substrate as described above;
an anode and a pixel defining layer formed on the array substrate;
an OLED device formed on the anode between the pixel defining layers;
a cathode formed on the OLED device; and
an encapsulation layer covering the cathode and the pixel defining layer.
In the array substrate, the manufacturing method thereof and the OLED structure provided by the invention, the first electrode layer and the second electrode layer of the capacitor structure are made of porous graphene materials, so that the capacitor density is increased, the area of a capacitor area can be effectively reduced, the wiring space is conveniently increased, and high PPI can be better realized; the second electrode layer and the grid metal layer form a double-grid structure, so that leakage current is effectively reduced, and the quality of the array substrate is improved; furthermore, voltage drop can be reduced by adopting a whole power supply voltage wiring.
Drawings
FIG. 1 is a flow chart of a method for fabricating an array substrate according to an embodiment of the invention;
fig. 2-8 are schematic structural views illustrating an array substrate in a manufacturing process according to an embodiment of the invention;
fig. 9 is a schematic structural diagram of an OLED structure according to an embodiment of the invention.
Detailed Description
The array substrate, the method of fabricating the same, and the OLED structure of the present invention will be described in more detail with reference to the schematic drawings, in which preferred embodiments of the present invention are shown, it being understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The core idea of the present invention is to provide a method for manufacturing an array substrate, including:
step S11, providing a substrate;
step S12, sequentially forming a first electrode layer, a first dielectric layer and a second electrode layer on the substrate to obtain a capacitor structure, wherein the first electrode layer and the second electrode layer are both made of porous graphene; and
step S13, a second dielectric layer, a polysilicon layer, a third dielectric layer and a gate metal layer are sequentially formed on the second electrode layer.
The following examples of the array substrate, the method for manufacturing the same, and the OLED structure are given to clearly illustrate the present invention, and it should be understood that the present invention is not limited to the following examples, and other modifications by conventional techniques of those skilled in the art are within the scope of the present invention.
The array substrate, the manufacturing method thereof, and the OLED structure of the present invention are described in detail with reference to fig. 1 and fig. 2-9, wherein fig. 1 is a flow chart of the manufacturing method of the array substrate of the present invention, fig. 2-8 are schematic structural diagrams of the array substrate of the present invention during the manufacturing process, and fig. 9 is a schematic structural diagram of the OLED structure of the present invention.
The manufacturing method of the array substrate comprises the following steps:
first, step S11 is executed, please refer to fig. 2, a substrate 10 is provided. The substrate 10 may be selected from materials in the prior art, such as a polyimide substrate, and the substrate of the present invention is not limited to the polyimide substrate, and may be made of other materials.
Next, a first additional step S111 is executed, please refer to fig. 3, a layer of a whole first metal layer 11 is formed on the substrate 10 as a power voltage (Vdd) trace. Specifically, the first metal layer 11 may be formed by a physical vapor deposition process or a sputtering process, for example, the material of the first metal layer 11 may be molybdenum, and the thickness thereof may be
Figure BDA0001124512630000051
In the method, the power supply voltage wire is a layer of metal on the whole surface, so that the voltage drop can be reduced, and the quality of the formed array substrate is improved.
Next, a second additional step S112 is performed, please continue with fig. 3, and a first insulating layer 12 is formed on the first metal layer 11. Specifically, the material of the first insulating layer 12 may be selected from silicon nitride, silicon oxide, silicon oxynitride, and the like, and may be formed by a chemical vapor deposition process. After the first insulating layer 12 is formed, an opening 121 is formed by an etching process to expose the first metal layer 11.
Then, step S12 is executed, please refer to fig. 4 and 5, a first electrode layer 13, a first dielectric layer 15, and a second electrode layer 16 are sequentially formed on the substrate 10, so as to obtain a capacitor structure, where the first electrode layer 13 and the second electrode layer 16 are both made of porous graphene. Specifically, the method comprises the following steps:
a first substep S121 of forming a first graphene material layer by a chemical vapor deposition process; for example, graphene may be obtained via reaction of silicon, silane, and the like in embodiments of the present invention. Wherein the deposited first graphene material layer fills the opening 121.
A second substep S122, performing photolithography and etching on the first graphene material layer, and performing laser irradiation to form the first electrode layer 13; after etching, the first graphene material layer to be formed into the capacitor structure remains, including the portion located in the opening 121. After laser irradiation, the first graphene material layer is converted into a porous graphene material, and the required first electrode layer 13 is obtained.
A third substep S123 of forming a second insulating layer 14 around the first electrode layer 13, the second insulating layer 14 being flush with the upper surface of the first electrode layer 13; for example, the second insulating layer 14 may be silicon nitride, silicon oxide, silicon oxynitride, or the like.
A fourth substep S124, forming a first dielectric layer 15 by using a chemical vapor deposition process; in the embodiment of the present invention, the first dielectric layer 15 is made of polyimide and has a thickness of 5 μm to 10 μm, but the thickness of the first dielectric layer 15 is not limited thereto, and may be flexibly changed according to the requirement for the capacitor and the process capability in the actual production.
A fifth substep S125, forming a second graphene material layer on the first dielectric layer 15 by using a chemical vapor deposition process; this step S125 may be the same as the first substep S121, i.e. graphene may be obtained via reaction of silicon, silane, etc., for example.
In the sixth substep S126, the second graphene material layer is etched by photolithography, and is irradiated with laser light to form the second electrode layer 16. After laser irradiation, the second graphene material layer is converted into a porous graphene material, and the required second electrode layer 16 is obtained.
Here, the laser irradiation in the second substep S122 may be adjusted to be performed in the sixth substep S126, and the film layer on which the laser acts may be controlled by adjusting the energy, wavelength, and the like of the laser, thereby forming the first electrode layer 13 and the second electrode layer 16, respectively.
Therefore, the capacitor structure in the invention can greatly reduce the area of the capacitor area, for example, the 5.5HD capacitor density in the prior art is 0.5 x 10-3f/m2The area is as high as 420 μm2Above, and in the present invention such a junctionThe capacitance density of the structure is more than or equal to 50f/m2E.g. 70f/m2、90f/m2And the like, thereby being capable of well reducing the area of the capacitor, being more beneficial to wiring and being beneficial to realizing high PPI.
Then, step S13 is executed, referring to fig. 6 to 8, a second dielectric layer 17, a polysilicon layer 19, a third dielectric layer 20 and a gate metal layer 21 are sequentially formed on the second electrode layer 16. Specifically, the method comprises the following steps:
in the first sub-step S131, a second dielectric layer 17 is formed by using a chemical vapor deposition process to cover the first dielectric layer 15 and the second electrode layer 16, and then a portion of the second dielectric layer on one side of the second electrode layer 16 is removed by using a photolithography and etching process to form the structure shown in fig. 6.
In the second substep S132, an opening 18 is formed, wherein the opening 18 is formed at one side of the second dielectric layer removed in step S131, and penetrates through the first dielectric layer 15, the second insulating layer 14 and the first insulating layer 12 to expose the first metal layer 11.
In the third substep S133, a polysilicon layer 19 is formed by using a chemical vapor deposition process, wherein the polysilicon layer 19 fills the opening 18, is connected to the first metal layer 11, and is located on the first dielectric layer 15 on one side of the opening 18 and on a portion of the second dielectric layer 17 on the capacitor structure. The polysilicon layer 19 is isolated from the second electrode layer 16 by the second dielectric layer 17.
In the fourth substep S134, a third dielectric layer 20 is formed by using a chemical vapor deposition process, and the third dielectric layer 20 covers the polysilicon layer 19 and is combined with the second dielectric layer 17 above the capacitor structure to seal the polysilicon layer 19.
In the fifth substep S135, a physical vapor deposition process is used to form a gate metal layer 21, specifically, the gate metal layer 21 is formed on the third dielectric layer 20 on the capacitor structure. In the embodiment of the present invention, the gate metal layer 21 is made of metal, and a common metal gate material may be used.
Thus, the second electrode layer 16 and the gate metal layer 21 form a dual-gate structure (i.e., a bottom gate and a top gate, respectively, with respect to the polysilicon layer 19) through this step, and thus the leakage current can be effectively reduced.
Thereafter, please continue to refer to fig. 8, which further includes: in step S14, a fourth dielectric layer 22 is formed to cover the third dielectric layer 20, the gate metal layer 21 and the second dielectric layer 17.
Step S15, forming a covering layer 23 covering the fourth dielectric layer 22.
Step S16, forming a second metal layer 24, where the second metal layer 24 penetrates through the cover layer 23, the fourth dielectric layer 22, the third dielectric layer 20, and the second dielectric layer 17 to be connected to the second electrode layer 16.
Thus, the array substrate of the present invention is manufactured, and with continued reference to fig. 8, the array substrate 100 includes:
a substrate 10;
a first metal layer 11 formed on the substrate 10, wherein the first metal layer 11 is a whole surface and is used as a power voltage trace;
a first insulating layer 12 formed on the first metal layer 11;
the capacitor structure is formed on the substrate 10, and comprises a first electrode layer 13, a first dielectric layer 14 and a second electrode layer 16, wherein the first electrode layer 13 and the second electrode layer 16 are made of porous graphene, the first electrode layer 13 penetrates through the first insulating layer 12 to be connected with the first metal layer 11, and second insulating layers 14 are formed on two sides of the first electrode layer 13;
a second dielectric layer 17, a polysilicon layer 19, a third dielectric layer 20 and a gate metal layer 21 which are partially laminated in sequence are formed on the second electrode layer 16, and the polysilicon layer 19 penetrates through the first dielectric layer 15, the second insulating layer 14 and the first insulating layer 12 to be connected with the first metal layer 11;
a fourth dielectric layer 22 formed on the third dielectric layer 20, the gate metal layer 21 and the second dielectric layer 17;
a capping layer 23 formed on the fourth dielectric layer 22;
and the second metal layer 24 penetrates through the covering layer 23, the fourth dielectric layer 22, the third dielectric layer 20 and the second dielectric layer 17 to be connected with the second electrode layer 16.
Further, the present invention provides an OLED structure, please refer to fig. 9, which includes:
the array substrate 100 as shown in fig. 8;
an anode 101 and a pixel defining layer 102 formed on the array substrate 100;
an OLED device 103 formed on the anode 101 between the pixel defining layers 102;
a cathode 104 formed on the OLED device 103; and
an encapsulation layer 105 covering the cathode 104 and the pixel defining layer 102.
In summary, in the array substrate, the manufacturing method thereof and the OLED structure provided by the invention, the first electrode layer and the second electrode layer of the capacitor structure are made of the porous graphene material, so that the capacitor density is increased, the area of the capacitor region can be effectively reduced, the wiring space is conveniently increased, and the high PPI can be better realized; the second electrode layer and the grid metal layer form a double-grid structure, so that leakage current is effectively reduced, and the quality of the array substrate is improved; furthermore, voltage drop can be reduced by adopting a whole power supply voltage wiring.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A manufacturing method of an array substrate includes:
providing a substrate;
sequentially forming a first electrode layer, a first dielectric layer and a second electrode layer on the substrate to obtain a capacitor structure, wherein the first electrode layer and the second electrode layer are both made of porous graphene; and
sequentially forming a second dielectric layer, a polycrystalline silicon layer, a third dielectric layer and a grid metal layer on the second electrode layer; the second electrode layer is used as a bottom gate of the polycrystalline silicon layer, and the grid metal layer is used as a top gate of the polycrystalline silicon layer to form a double-gate structure;
before obtaining the capacitor structure, the method further comprises: and forming a whole first metal layer on the substrate as a power supply voltage wire.
2. The method of claim 1, wherein the step of obtaining the capacitor structure comprises:
forming a first graphene material layer by adopting a chemical vapor deposition process;
photoetching and etching the first graphene material layer, and irradiating by adopting laser to form the first electrode layer;
forming a second insulating layer around the first electrode layer, wherein the second insulating layer is flush with the upper surface of the first electrode layer;
forming a first dielectric layer by adopting a chemical vapor deposition process;
forming a second graphene material layer on the first medium layer by adopting a chemical vapor deposition process;
and photoetching and etching the first graphene material layer, and irradiating by adopting laser to form the second electrode layer.
3. The method for manufacturing the array substrate according to claim 2, wherein the first dielectric layer is made of polyimide and has a thickness of 5 μm to 10 μm.
4. The method of claim 2, further comprising, after providing a substrate and before obtaining the capacitor structure:
a first insulating layer is formed on the first metal layer.
5. The method of claim 4, wherein the first metal layer is made of Mo and has a thickness of Mo
Figure FDA0002504076870000021
6. The method of claim 4, wherein an opening is formed in the insulating layer, and the first electrode layer fills the opening and is connected to the first metal layer.
7. The method of claim 4, wherein the step of sequentially forming a second dielectric layer, a polysilicon layer, a third dielectric layer and a gate metal layer on the second electrode layer comprises:
forming a second dielectric layer by adopting a chemical vapor deposition process, and covering the first dielectric layer and the second electrode layer;
removing part of the second dielectric layer on one side of the second electrode layer by a photoetching process;
forming an opening, wherein the opening is formed at one side of the second dielectric layer, penetrates through the first dielectric layer, the second insulating layer and the first insulating layer and exposes the first metal layer;
forming a polycrystalline silicon layer by adopting a chemical vapor deposition process, wherein the polycrystalline silicon layer fills the opening, is connected with the first metal layer, and is positioned on the first dielectric layer on one side of the opening and part of the second dielectric layer above the capacitor structure;
forming a third dielectric layer by adopting a chemical vapor deposition process, wherein the third dielectric layer covers the polycrystalline silicon layer and is combined with the second dielectric layer above the capacitor structure to seal the polycrystalline silicon layer;
and forming a grid metal layer by adopting a physical vapor deposition process, wherein the grid metal layer is formed on the third dielectric layer above the capacitor structure.
8. The method of claim 1, wherein after sequentially forming a second dielectric layer, a polysilicon layer, a third dielectric layer and a gate metal layer on the second electrode layer, the method further comprises:
forming a fourth dielectric layer to cover the third dielectric layer, the gate metal layer and the second dielectric layer;
forming a covering layer to cover the fourth dielectric layer;
and forming a second metal layer, wherein the second metal layer penetrates through the covering layer, the fourth dielectric layer, the third dielectric layer and the second dielectric layer to be connected with the second electrode layer.
9. An array substrate formed using the method of any one of claims 1 to 8, the array substrate comprising:
a substrate;
the capacitor structure comprises a first electrode layer, a second electrode layer and a first dielectric layer positioned between the first electrode layer and the second electrode layer, wherein the first metal layer and the capacitor structure are sequentially formed on the substrate and used as power supply voltage wiring;
and forming a second dielectric layer, a polysilicon layer, a third dielectric layer and a gate metal layer which are partially laminated on the second electrode layer in sequence, wherein the second electrode layer is used as a bottom gate of the polysilicon layer, and the gate metal layer is used as a top gate of the polysilicon layer to form a double-gate structure.
10. An OLED structure comprising:
the array substrate of claim 9;
an anode and a pixel defining layer formed on the array substrate;
an OLED device formed on the anode between the pixel defining layers;
a cathode formed on the OLED device; and
an encapsulation layer covering the cathode and the pixel defining layer.
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