CN107887328A - Array base palte and its manufacture method, OLED structure - Google Patents
Array base palte and its manufacture method, OLED structure Download PDFInfo
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- CN107887328A CN107887328A CN201610865955.2A CN201610865955A CN107887328A CN 107887328 A CN107887328 A CN 107887328A CN 201610865955 A CN201610865955 A CN 201610865955A CN 107887328 A CN107887328 A CN 107887328A
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
Abstract
Present invention is disclosed a kind of array base palte and its manufacture method, OLED structure.In array base palte provided by the invention and its manufacture method, OLED structure, it is porous graphene material by the first electrode layer and the second electrode lay of capacitance structure, increases capacitance density, reduces capacitive region area, it is easy to increase wiring space, high PPI can be better achieved；Double-gate structure is formed by the second electrode lay and gate metal layer, reduces leakage current, is advantageous to improve the quality of array base palte.
Description
Technical field
The present invention relates to display field, more particularly to a kind of array base palte and its manufacture method, OLED structure.
Background technology
With the development of information-intensive society, people are growing to the demand of display device.Flexible display is so that its is frivolous, can
The characteristics of bending even crimps, good mechanical property is increasingly favored by people.At present, flexible display answering in life
With more and more extensive.Flexible display includes flexible liquid crystal display (LCD) and flexible organic light emitting diode display
(OLED).Flexible display is typically fabricated on flexible carrier, due to itself distinctive flexible feature of flexible display,
Determine that it has many special Consumer's Experiences, also bring very big challenge to its design and making.
At present, high PPI flexible display has become the inexorable trend of development, and this requires that the size of each pixel is more next
Smaller, the wiring space of image element circuit is also smaller, but electric capacity takes up space maximum in image element circuit, is unfavorable for obtaining high
PPI.Therefore, how in the case where ensuring capacitance, reduce electric capacity and take up space (namely reducing i.e. capacitive region area), turn into
One important research direction.
The content of the invention
It is an object of the present invention to provide a kind of array base palte and its manufacture method, OLED structure, reduces capacitive region face
Product, realizes high PPI Flexible Displays.
Another object of the present invention is to while realizing high PPI Flexible Displays, reduce leakage current.
A further object of the present invention is, by using the supply voltage cabling in whole face, reduces pressure drop.
In order to solve the above technical problems, the present invention provides a kind of manufacture method of array base palte, including：
One substrate is provided；
First electrode layer, first medium layer and the second electrode lay are sequentially formed on the substrate, obtain capacitance structure, institute
State first electrode layer and the second electrode lay is made by porous graphene；And
Second dielectric layer, polysilicon layer, the 3rd dielectric layer and gate metal layer are sequentially formed on the second electrode lay.
Optionally, for the manufacture method of described array base palte, the step of obtaining capacitance structure, includes：
First grapheme material layer is formed using chemical vapor deposition method；
First grapheme material layer described in chemical wet etching, and irradiated using laser, form the first electrode layer；
The second insulating barrier, second insulating barrier and the first electrode layer upper table are formed around the first electrode layer
Face flushes；
First medium layer is formed using chemical vapor deposition method；
Second grapheme material layer is formed on the first medium layer using chemical vapor deposition method；
First grapheme material layer described in chemical wet etching, and irradiated using laser, form the second electrode lay.
Optionally, for the manufacture method of described array base palte, the material of the first medium layer is polyimides, thick
Spend for 5 μm~10 μm.
Optionally, for the manufacture method of described array base palte, after a substrate is provided, obtain capacitance structure it
Before, in addition to：
The first metal layer in one layer of whole face is formed on the substrate as supply voltage cabling；
The first insulating barrier is formed on the first metal layer.
Optionally, for the manufacture method of described array base palte, the material of the first metal layer is molybdenum, and thickness is
Optionally, for the manufacture method of described array base palte, formed with opening, first electricity in the insulating barrier
Pole layer filling is described to be open and is connected with the first metal layer.
Optionally, for the manufacture method of described array base palte, second Jie is sequentially formed on the second electrode lay
The step of matter layer, polysilicon layer, the 3rd dielectric layer and gate metal layer, includes：
Second dielectric layer is formed using chemical vapor deposition method, covers first medium layer and the second electrode lay；
The part second dielectric layer of the second electrode lay side is removed by lithographic etch process；
Opening is formed, the opening is formed at the side that has been removed second dielectric layer, through the first medium layer, the
Two insulating barriers and the first insulating barrier, expose the first metal layer；
Polysilicon layer is formed using chemical vapor deposition method, the full opening of polysilicon layer filling, with described the
One metal level is connected, and the part second dielectric layer on the first medium layer of the opening side and above capacitance structure
On；
3rd dielectric layer is formed using chemical vapor deposition method, the 3rd dielectric layer covers the polysilicon layer, and
It is combined above capacitance structure with the second dielectric layer, realizes the sealing to polysilicon layer；
Gate metal layer is formed using physical gas-phase deposition, the gate metal layer is formed on the capacitance structure
On 3rd dielectric layer of side.
Optionally, for the manufacture method of described array base palte, second Jie is sequentially formed on the second electrode lay
After matter layer, polysilicon layer, the 3rd dielectric layer and gate metal layer, in addition to：
Form the 4th dielectric layer and cover the 3rd dielectric layer, gate metal layer and the second dielectric layer；
Form coating and cover the 4th dielectric layer；
Second metal layer is formed, the second metal layer penetrates the coating, the 4th dielectric layer, the 3rd dielectric layer and the
Second medium layer is connected with the second electrode lay.
The present invention also provides a kind of array base palte, is formed using method as described above, the array base palte includes：
One substrate；
Capacitance structure on the substrate is formed, the capacitance structure includes first electrode layer, the second electrode lay and position
First medium layer between the first electrode layer and the second electrode lay, the first electrode layer and the second electrode lay are porous
Graphene material；
Formed on the second electrode lay successively part stacking second dielectric layer, polysilicon layer, the 3rd dielectric layer and
Gate metal layer.
The present invention also provides a kind of OLED structure, including：
Array base palte as described above；
Form anode and pixel confining layers on the array base palte；
Form the OLED on the anode between the pixel confining layers；
Form the negative electrode in the OLED；And
Cover the negative electrode and the encapsulated layer of pixel confining layers.
In array base palte provided by the invention and its manufacture method, OLED structure, pass through the first of capacitance structure
Electrode layer and the second electrode lay are porous graphene material, capacitance density are increased, so as to effectively reduce capacitive region face
Product, it is easy to increase wiring space, high PPI can be better achieved；It is made up of the second electrode lay and gate metal layer double
Grid structure, effectively reduces leakage current, is advantageous to improve the quality of array base palte；Further, by using the electricity in whole face
Source voltage cabling, can reduce pressure drop.
Brief description of the drawings
The flow chart of the manufacture method of array base palte in Fig. 1 one embodiment of the invention；
Fig. 2-Fig. 8 is the structural representation of array base palte in the fabrication process in one embodiment of the invention；
Fig. 9 is the structural representation of OLED structure in one embodiment of the invention.
Embodiment
The array base palte and its manufacture method, OLED structure of the present invention are retouched in more detail below in conjunction with schematic diagram
State, which show the preferred embodiments of the present invention, it should be appreciated that those skilled in the art can change described here hair
It is bright, and still realize the advantageous effects of the present invention.Therefore, description below is appreciated that for the wide of those skilled in the art
It is general to know, and it is not intended as limitation of the present invention.
More specifically description is of the invention by way of example referring to the drawings in the following passage.Will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing is using very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
The core concept of the present invention is to provide a kind of manufacture method of array base palte, including：
Step S11 a, there is provided substrate；
Step S12, first electrode layer, first medium layer and the second electrode lay are sequentially formed on the substrate, obtain electricity
Hold structure, the first electrode layer and the second electrode lay are made by porous graphene；And
Step S13, second dielectric layer, polysilicon layer, the 3rd dielectric layer and grid are sequentially formed on the second electrode lay
Pole metal level.
The array base palte and its manufacture method, the preferred embodiment of OLED structure are exemplified below, clearly to illustrate this
The content of invention, it is understood that, present disclosure is not restricted to following examples, and other pass through the common skill in this area
The improvement of the conventional technical means of art personnel is also within the thought range of the present invention.
Array base palte and its manufacture method of the invention, OLED structure are carried out specifically with reference to Fig. 1, Fig. 2-Fig. 9
It is bright, wherein, the flow chart of the manufacture method of array base palte in Fig. 1 present invention, Fig. 2-Fig. 8 is manufacturing for array base palte in the present invention
During structural representation, Fig. 9 be the present invention in OLED structure structural representation.
The manufacture method of the array base palte of the present invention, including：
First, step S11 is performed, refer to Fig. 2, there is provided a substrate 10.The substrate 10 can be selected as prior art
In material, such as polyimide substrate, substrate of the present invention be not limited to polyimides material, also can be by other materials
It is made.
Then, the first additional step S111 is performed, refer to Fig. 3, the first of one layer of whole face is formed in the substrate 10
Metal level 11 is used as supply voltage (Vdd) cabling.Specifically, the first metal layer 11 can use physical gas-phase deposition shape
Into can also be formed with sputtering technology, for example, the material of the first metal layer 11 can be molybdenum, its thickness can beThis way in the present invention, because supply voltage cabling is the metal in one layer of whole face, therefore it can reduce
Pressure drop, be advantageous to improve the quality of the array base palte formed.
Then, the second additional step S112 is performed, please continue to refer to Fig. 3, first is formed on the first metal layer 11
Insulating barrier 12., can be with specifically, the material of first insulating barrier 12 can be selected as silicon nitride, silica, silicon oxynitride etc.
Formed using chemical vapor deposition method.After first insulating barrier 12 formation, opening 121 is formed by etching technics, cruelly
Expose the first metal layer 11.
Then, step S12 is performed, refer to Fig. 4 and Fig. 5, first electrode layer 13, the are sequentially formed in the substrate 10
One dielectric layer 15 and the second electrode lay 16, capacitance structure is obtained, the first electrode layer 13 and the second electrode lay 16 are by porous
Graphene is made.Specifically, this step includes：
First sub-step S121, the first grapheme material layer is formed using chemical vapor deposition method；For example, in the present invention
Can be via the reacted acquisition graphene such as silicon, silane in embodiment.Wherein, the full institute of the first grapheme material layer filling of deposition
State opening 121.
Second sub-step S122, the first grapheme material layer described in chemical wet etching, and irradiated using laser, form described the
One electrode layer 13；Retaining after etching needs to form the first grapheme material layer of capacitance structure, including positioned at the opening
Part in 121.After being irradiated by laser so that the first grapheme material layer is changed into porous graphene material, needed for acquisition
The first electrode layer 13 wanted.
3rd sub-step S123, the second insulating barrier 14, second insulating barrier are formed around the first electrode layer 13
14 with the upper surface flush of first electrode layer 13；For example, second insulating barrier 14 can be silicon nitride, silica, nitrogen oxygen
SiClx etc..
4th sub-step S124, first medium layer 15 is formed using chemical vapor deposition method；In embodiments of the present invention,
The material of the first medium layer 15 is polyimides, and thickness is 5 μm~10 μm, certainly, the thickness of the first medium layer 15
This is not limited to, the demand and technological ability of electric capacity can flexibly be changed according in actual production.
5th sub-step S125, the second graphene is formed on the first medium layer 15 using chemical vapor deposition method
Material layer；This step S125 can be identical with the first sub-step S121, i.e., such as can via silicon, silane reacted acquisition stone
Black alkene.
6th sub-step S126, the second grapheme material layer described in chemical wet etching, and irradiated using laser, form described the
Two electrode layers 16.After being irradiated by laser so that the second grapheme material layer is changed into porous graphene material, required for acquisition
The second electrode lay 16.
Wherein, the laser irradiation in the second sub-step S122 can be adjusted to perform in the 6th sub-step S126, can be with
Energy, wavelength by adjusting laser etc. control the film layer of laser action, so as to form the electricity of first electrode layer 13 and second respectively
Pole layer 16.
Thus, the capacitance structure in the present invention is formed, and the capacitance structure in the present invention can greatly reduce capacitive region area,
For example, 5.5HD capacitance densities are 0.5*10 in the prior art-3f/m2, then up to 420 μm of area2More than, and it is this in the present invention
The capacitance density of structure is more than or equal to 50f/m2, such as 70f/m2、90f/m2Deng, so as to reduce capacity area well,
It is more beneficial for connecting up, is advantageously implemented high PPI.
Afterwards, step S13 is performed, Fig. 6-Fig. 8 is refer to, second dielectric layer is sequentially formed on the second electrode lay 16
17th, polysilicon layer 19, the 3rd dielectric layer 20 and gate metal layer 21.Specifically, this step includes：
First sub-step S131, second dielectric layer 17, covering first medium layer 15 are formed using chemical vapor deposition method
With the second electrode lay 16, the part second dielectric layer of the side of the second electrode lay 16 is then removed by lithographic etch process, is formed
Structure as shown in Figure 6.
Second sub-step S132, opening 18 is formed, the opening 18, which is formed in step S131, removes second dielectric layer
Side, through the first medium layer 15, the second insulating barrier 14 and the first insulating barrier 12, expose the first metal layer 11.
3rd sub-step S133, polysilicon layer 19 is formed using chemical vapor deposition method, the polysilicon layer 19 is filled
The full opening 18, is connected with the first metal layer 11, and on the first medium layer 15 of 18 sides of the opening and
In part second dielectric layer 17 on capacitance structure.The polysilicon layer 19 is situated between with the second electrode lay 16 by described second
Matter layer 17 is isolated.
4th sub-step S134, the 3rd dielectric layer 20, the 3rd dielectric layer 20 are formed using chemical vapor deposition method
The polysilicon layer 19 is covered, and is combined above capacitance structure with the second dielectric layer 17, is realized to polysilicon layer 19
Sealing.
5th sub-step S135, gate metal layer 21 is formed using physical gas-phase deposition, specifically, the grid is golden
Category layer 21 is formed on the 3rd dielectric layer 20 on the capacitance structure.In embodiments of the present invention, the gate metal layer 21
Material be metal, can use common metal gates material.
Thus, the second electrode lay 16 and gate metal layer 21 is caused to form double-gate structure (i.e. relative to more by this step
Crystal silicon layer 19 is respectively bottom gate and top-gated), by this structure, leakage current can be effectively reduced.
Afterwards, please continue to refer to Fig. 8, in addition to：Step S14, form the 4th dielectric layer 22 and cover the 3rd dielectric layer
20th, gate metal layer 21 and second dielectric layer 17.
Step S15, form coating 23 and cover the 4th dielectric layer 22.
Step S16, forms second metal layer 24, and the second metal layer 24 penetrates the coating 23, the 4th dielectric layer
22nd, the 3rd dielectric layer 20 and second dielectric layer 17 are connected with the second electrode lay 16.
Thus, array base palte of the invention manufacture is completed, and please continue to refer to Fig. 8, the array base palte 100 includes：
One substrate 10；
The first metal layer 11 in the substrate 10 is formed, the first metal layer 11 is a whole face, as power supply electricity
Press cabling；
Form the first insulating barrier 12 on the first metal layer 11；
The capacitance structure in the substrate 10 is formed, the capacitance structure includes first electrode layer 13, first medium layer
14 and the second electrode lay 16, the first electrode layer 13 and the second electrode lay 16 are porous graphene material, the first electrode
Layer 13 is connected through first insulating barrier 12 with the first metal layer 11, and the both sides of first electrode layer 13 are formed with the
Two insulating barriers 14；
Part is laminated successively on the second electrode lay 16 second dielectric layer 17, polysilicon layer the 19, the 3rd is formed to be situated between
Matter layer 20 and gate metal layer 21, the polysilicon layer 19 are exhausted through the first medium layer 15, the second insulating barrier 14 and first
Edge layer 12 is connected with the first metal layer 11；
Form the 4th dielectric layer 22 in the 3rd dielectric layer 20, gate metal layer 21 and second dielectric layer 17；
Form the coating 23 on the 4th dielectric layer 22；
Second metal layer 24, the second metal layer 24 penetrate the coating 23, the 4th dielectric layer 22, the 3rd dielectric layer
20 and second dielectric layer 17 be connected with the second electrode lay 16.
Further, the present invention also provides a kind of OLED structure, refer to Fig. 9, including：
Array base palte 100 as described in Figure 8；
Form anode 101 and pixel confining layers 102 on the array base palte 100；
Form the OLED 103 on the anode 101 between pixel confining layers 102；
Form the negative electrode 104 in the OLED 103；And
Cover the negative electrode 104 and the encapsulated layer 105 of pixel confining layers 102.
In summary, in array base palte provided by the invention and its manufacture method, OLED structure, capacitive junctions are passed through
The first electrode layer and the second electrode lay of structure are porous graphene material, capacitance density are increased, so as to effectively reduce
Capacitive region area, it is easy to increase wiring space, high PPI can be better achieved；Pass through the second electrode lay and gate metal
Layer forms double-gate structure, effectively reduces leakage current, is advantageous to improve the quality of array base palte；Further, by using
The supply voltage cabling in whole face, can reduce pressure drop.
Obviously, those skilled in the art can carry out the essence of various changes and modification without departing from the present invention to the present invention
God and scope.So, if these modifications and variations of the present invention belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these changes and modification.
Claims (10)
1. a kind of manufacture method of array base palte, including：
One substrate is provided；
Sequentially form first electrode layer, first medium layer and the second electrode lay on the substrate, obtain capacitance structure, described the
One electrode layer and the second electrode lay are made by porous graphene；And
Second dielectric layer, polysilicon layer, the 3rd dielectric layer and gate metal layer are sequentially formed on the second electrode lay.
2. the manufacture method of array base palte as claimed in claim 1, it is characterised in that the step of obtaining capacitance structure includes：
First grapheme material layer is formed using chemical vapor deposition method；
First grapheme material layer described in chemical wet etching, and irradiated using laser, form the first electrode layer；
The second insulating barrier is formed around the first electrode layer, second insulating barrier and the first electrode layer upper surface are neat
It is flat；
First medium layer is formed using chemical vapor deposition method；
Second grapheme material layer is formed on the first medium layer using chemical vapor deposition method；
First grapheme material layer described in chemical wet etching, and irradiated using laser, form the second electrode lay.
3. the manufacture method of array base palte as claimed in claim 2, it is characterised in that the material of the first medium layer is poly-
Acid imide, thickness are 5 μm~10 μm.
4. the manufacture method of array base palte as claimed in claim 2, it is characterised in that after a substrate is provided, obtain electricity
Before holding structure, in addition to：
The first metal layer in one layer of whole face is formed on the substrate as supply voltage cabling；
The first insulating barrier is formed on the first metal layer.
5. the manufacture method of array base palte as claimed in claim 4, it is characterised in that the material of the first metal layer is
Molybdenum, thickness are
6. the manufacture method of array base palte as claimed in claim 4, it is characterised in that formed with opening in the insulating barrier,
The first electrode layer filling is described to be open and is connected with the first metal layer.
7. the manufacture method of array base palte as claimed in claim 4, it is characterised in that the shape successively on the second electrode lay
Include into the step of second dielectric layer, polysilicon layer, the 3rd dielectric layer and gate metal layer：
Second dielectric layer is formed using chemical vapor deposition method, covers first medium layer and the second electrode lay；
The part second dielectric layer of the second electrode lay side is removed by lithographic etch process；
Opening is formed, the opening is formed at the side that has been removed second dielectric layer, through the first medium layer, second exhausted
Edge layer and the first insulating barrier, expose the first metal layer；
Polysilicon layer, the full opening of polysilicon layer filling, with first gold medal are formed using chemical vapor deposition method
Category layer is connected, and in the part second dielectric layer on the first medium layer of the opening side and above capacitance structure；
3rd dielectric layer is formed using chemical vapor deposition method, the 3rd dielectric layer covers the polysilicon layer, and in electricity
Hold superstructure to be combined with the second dielectric layer, realize the sealing to polysilicon layer；
Gate metal layer is formed using physical gas-phase deposition, the gate metal layer is formed above the capacitance structure
On 3rd dielectric layer.
8. the manufacture method of array base palte as claimed in claim 1, it is characterised in that the shape successively on the second electrode lay
Into after second dielectric layer, polysilicon layer, the 3rd dielectric layer and gate metal layer, in addition to：
Form the 4th dielectric layer and cover the 3rd dielectric layer, gate metal layer and the second dielectric layer；
Form coating and cover the 4th dielectric layer；
Second metal layer is formed, the second metal layer penetrates the coating, the 4th dielectric layer, the 3rd dielectric layer and second and is situated between
Matter layer is connected with the second electrode lay.
9. a kind of array base palte, being formed using the method as any one of claim 1 to 8, the array base palte includes：
One substrate；
Capacitance structure on the substrate is formed, the capacitance structure includes first electrode layer, the second electrode lay and positioned at institute
The first medium layer between first electrode layer and the second electrode lay is stated, the first electrode layer and the second electrode lay are porous graphite
Alkene material；
Form second dielectric layer, polysilicon layer, the 3rd dielectric layer and the grid that part is laminated successively on the second electrode lay
Metal level.
10. a kind of OLED structure, including：
Array base palte as claimed in claim 9；
Form anode and pixel confining layers on the array base palte；
Form the OLED on the anode between the pixel confining layers；
Form the negative electrode in the OLED；And
Cover the negative electrode and the encapsulated layer of pixel confining layers.
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| CN109786425A (en) * | 2019-01-08 | 2019-05-21 | 昆山国显光电有限公司 | Array substrate and preparation method thereof, display device |
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