CN107863325A - High-power MOS FET's is fanned out to shape encapsulating structure and its manufacturing process - Google Patents
High-power MOS FET's is fanned out to shape encapsulating structure and its manufacturing process Download PDFInfo
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- CN107863325A CN107863325A CN201710106233.3A CN201710106233A CN107863325A CN 107863325 A CN107863325 A CN 107863325A CN 201710106233 A CN201710106233 A CN 201710106233A CN 107863325 A CN107863325 A CN 107863325A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 67
- 239000000919 ceramic Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 235000012431 wafers Nutrition 0.000 claims abstract description 27
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052737 gold Inorganic materials 0.000 claims abstract description 21
- 239000010931 gold Substances 0.000 claims abstract description 21
- 229910052718 tin Inorganic materials 0.000 claims description 57
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 24
- 229910052802 copper Inorganic materials 0.000 claims description 24
- 239000010949 copper Substances 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 9
- 239000012774 insulation material Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 238000012545 processing Methods 0.000 claims description 5
- 238000012360 testing method Methods 0.000 claims description 4
- 238000003854 Surface Print Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 3
- 238000013461 design Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 229910052573 porcelain Inorganic materials 0.000 claims 1
- 239000006185 dispersion Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000011990 functional testing Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229940095676 wafer product Drugs 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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Abstract
Shape encapsulating structure is fanned out to the invention discloses a kind of high-power MOS FET, including the ceramic double-sided copper-clad substrate set gradually from down to up, Gold plated Layer, the single MOSFET chip that high-power MOS FET wafers are formed after scribing, tin ball, the lower caulking groove for built-in single MOSFET chip is provided with ceramic double-sided copper-clad substrate, grid is provided with single MOSFET chip, source electrode and drain electrode, tin ball includes the first tin ball, second tin ball, 3rd tin ball, 4th tin ball, first tin ball is located at the outer both sides of lower caulking groove and the drain electrode for drawing finished product is contacted with Gold plated Layer, second tin ball, which is located at, is used for the grid for drawing finished product on grid, 3rd tin ball, 4th tin ball is located at the upper source electrode for being used to draw finished product on source electrode；Also disclose a kind of high-power MOS FET manufacturing process for being fanned out to shape encapsulating structure, the lower internal resistances of MOSFET, smaller stray parameter, more preferable heat dispersion and bigger power density ratio can be realized by the present invention, while are more suitable for large-scale mass production and reduce production cost.
Description
Technical field
The invention belongs to field of semiconductor manufacture, and in particular to high-power MOS FET's is fanned out to shape encapsulating structure and its manufacture
Technique.
Background technology
The technical parameter and performance of metal oxide semiconductor field effect tube (MOSFET), depending on the performance of chip in itself
In terms of later stage encapsulation two, after wafer output, its parameter is it has been determined that still pass through the encapsulation in later stage, to univers parameter
It can change, this is mainly reflected in the introducing of DC parameter, alternating-current parameter, hot property and stray inductance and stray capacitance.One
The packing forms planted, cost rationally, be adapted to batch production on the premise of, will make every effort to strengthen its hot property and moisture resistance humidity etc.
Level, for the purpose of not deteriorating its DC parameter, alternating-current parameter, stray parameter.
The encapsulation of INVENTIONConventional metal-oxide semiconductor field (MOSFET), it is that MOSFET chips are bonded to lead frame
On frame (Lead Frame), then again through processes such as bonding wire, plastic packaging, plating, rib cutting, test, packagings, the mistake of finished product is produced
Journey.Its packing forms mainly has the series such as SOT, SOP, TO, DFN.At present, these serial encapsulation are the masters of MOSFET products
Power, as electronic product is to miniaturization, the development in more power density ratio direction, it is desirable to which electronic component is real in smaller volume
It is now more multi-functional.The key element that power MOSFET is transmitted and changed as energy, correspondingly need to realize lower internal resistance, higher
Switching frequency, more preferable heat dispersion and smaller volume requirement.Conventional package is in order to realize that it is many excellent that these demands have been done
Change, but be constrained to the limitation of structure and material, the limit has been basically reached, it is difficult to there is the space being substantially improved again.
The content of the invention
In view of this, it is a primary object of the present invention to provide a kind of high-power MOS FET be fanned out to shape encapsulating structure and its
Manufacturing process.
To reach above-mentioned purpose, the technical proposal of the invention is realized in this way：
A kind of high-power MOS FET's of offer of the embodiment of the present invention is fanned out to shape encapsulating structure, including sets gradually from down to up
Ceramic double-sided copper-clad substrate, Gold plated Layer, high-power MOS FET the wafers single MOSFET chip, the tin ball that are formed after scribing,
The lower caulking groove for built-in single MOSFET chip, the single MOSFET chip are provided with the ceramic double-sided copper-clad substrate
On be provided with grid, source electrode and drain electrode, the tin ball includes the first tin ball, the second tin ball, the 3rd tin ball, the 4th tin ball, described
First tin ball is located at the outer both sides of lower caulking groove and the drain electrode for drawing finished product is contacted with Gold plated Layer, and the second tin ball is located at grid
The extremely upper grid for being used to draw finished product, the 3rd tin ball, the 4th tin ball are located at the upper source electrode for being used to draw finished product on source electrode.
In such scheme, the ceramic double-sided copper-clad substrate includes back side thin copper layer, the ceramics set gradually from down to up
Layer, thick copper layer, the lower caulking groove for built-in single MOSFET chip is provided with the thick copper layer.
In such scheme, region is provided between the second tin ball, the 3rd tin ball, the 4th tin ball and grid or source electrode
Metal level.
In such scheme, the bottom of the ceramic double-sided copper-clad substrate is provided with Gold plated Layer, and both sides are provided with thick copper layer.
In such scheme, between the gap of the single MOSFET chip and single MOSFET chips side wall and lower caulking groove
Gap is provided with insulation material layer.
In such scheme, the surface of the single MOSFET chip is provided with passivation layer except other regions of tin ball bottom.
The embodiment of the present invention also provides a kind of high-power MOS FET manufacturing process for being fanned out to shape encapsulating structure, and the technique is led to
Cross following steps realization：
Step 1：Ceramic double-sided copper-clad substrate cut into wafer size, using precise etching method in ceramic double-sided copper-clad
The thick copper face of substrate corrodes the surface circumferential side frame groove of the lower caulking groove for be put into single MOSFET chip 200, product, thin
Copper face corrodes the back side circumferential side frame groove for product, and corrosion depth is exposes ceramic layer, the ceramic double-sided copper-clad that will be etched
The metal part of substrate does Gold plated Layer, lower caulking groove bottom tin coating；
Step 2：Into the thin slice of 100um thickness, wafer frontside grid and source electrode expose full wafer MOSFET grinding wafers
Part Gold plated Layer processing, wafer rear drain electrode do metal layer, single MOSFET chip are diced into by design size；
Step 3：The single MOSFET chip pulled is transferred to the lower caulking groove of ceramic double-sided copper-clad substrate, full wafer ceramics are double
Chip and substrate are bonded to together by face copper-clad base plate heating；
Step 4：The surface printing insulation material layer of the single MOSFET chip；
Step 5：Three electrodes of the single MOSFET chip plant multiple tin balls；
Step 6：Whole plate test, it is diced into single finished product.
Compared with prior art, beneficial effects of the present invention：
The present invention can realize the lower internal resistances of MOSFET, smaller stray parameter, more preferable heat dispersion and bigger work(
Rate density ratio, while be more suitable for large-scale mass production and reduce production cost.
Brief description of the drawings
Fig. 1 provides a kind of high-power MOS FET structural representation for being fanned out to shape encapsulating structure for the embodiment of the present invention；
Fig. 2 is schematic diagram of the high-power MOS FET wafers after pre-treatment；
Fig. 3 is the former chip architecture figure of ceramic double-sided copper-clad substrate；
Fig. 4 is ceramic double-sided copper-clad substrate through precise etching manuscript；
Fig. 5 is the ceramic gold-plated schematic diagram of double-sided copper-clad substrate；
Fig. 6 is the lower tin plating schematic diagram in caulking groove bottom of ceramic double-sided copper-clad substrate；
Fig. 7 is the structure chart that single MOSFET chip is put into after lower caulking groove and bonding；
Fig. 8 is that surface coats the disk after insulating materials；
Fig. 9 is that electrode plants the schematic diagram after ball；
Figure 10 is finished product schematic diagram.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
A kind of high-power MOS FET's of offer of the embodiment of the present invention is fanned out to shape encapsulating structure, as shown in figure 1, including being arrived by down
On formed after scribing single of the ceramic double-sided copper-clad substrate, Gold plated Layer 300, the high-power MOS FET wafers that set gradually
MOSFET chips 200, tin ball, it is provided with built-in single MOSFET chip 200 on the ceramic double-sided copper-clad substrate
Caulking groove, grid 202, source electrode 204 and drain electrode 201 are provided with the single MOSFET chip 200, the tin ball includes the first tin
Ball 400, the second tin ball 401, the 3rd tin ball 402, the 4th tin ball 404, the first tin ball 400 be located at the outer both sides of lower caulking groove and
The drain electrode for drawing finished product is contacted with Gold plated Layer 300, the second tin ball 401, which is located on grid 202, to be used to draw finished product
Grid, the 3rd tin ball 402, the 4th tin ball 40 are located at the upper source electrode for being used to draw finished product on source electrode 204.
Certainly, when source electrode and drain electrode have high current to flow through, size that can be according to single MOSFET chip 200, electric current
Size, arrange multiple tin balls.
The ceramic double-sided copper-clad substrate includes the back side thin copper layer 101, ceramic layer 100, thickness set gradually from down to up
Layers of copper 102, the lower caulking groove for built-in single MOSFET chip 200 is provided with the thick copper layer 102.The conduct of ceramic layer 100
Insulation and heat-conducting layer, back side thin copper layer 101 play a part of balancing internal stress, the second tin ball 401, the 3rd tin ball 402, the
Be provided with regional metal layer 700 between four tin balls 404 and grid 202 or source electrode 204, primarily to increase chip electrode with
The adhesion of tin ball.
The bottom of the ceramic double-sided copper-clad substrate is provided with Gold plated Layer 600, and both sides are provided with thick copper layer 601.Gold plated Layer
600 be to prevent the oxidation of copper.
The gap of the single MOSFET chip 200 and the single side wall of MOSFET chips 200 and the gap of lower caulking groove are equal
It is provided with insulation material layer 500.Left-hand seat insulation material layer 500 rises while the insulating properties of product are improved to its lower metal
Anti-oxidation effect is arrived.
The surface of the single MOSFET chip 200 is provided with passivation layer 203 except other regions of tin ball bottom, its composition
It is SiO2, it plays a part of insulating and protected to chip surface.
The lower caulking groove is processed using the method for precise etching, and its depth is 100 ± 10um.Single MOSFET chip 200
It is to be bound together its drain metal and the Gold plated Layer 300 of thick copper by tin layers, realizes that electrical property connects, the thickness of tin layers is small
In 20um.Single MOSFET chip 200 is by heat diffusion to back and to realize insulation by ceramic layer 100.Ceramic layer 100
Material can be Al2O3 or AlN, this depends primarily on product power consumption and cost needs.Product is prolonged by lower caulking groove down payment category
Reach surface and form fan-out structure, avoid chip perforation, connecting line is rebuild or beaten to conductive layer.
The embodiment of the present invention also provides a kind of high-power MOS FET manufacturing process for being fanned out to shape encapsulating structure, such as Fig. 2-10
Shown, the technique is realized by following steps：
Step 1：Ceramic double-sided copper-clad substrate cut into wafer size, using precise etching method in ceramic double-sided copper-clad
The thick copper face of substrate corrodes the surface circumferential side frame groove of the lower caulking groove for be put into single MOSFET chip 200, product, thin
Copper face corrodes the back side circumferential side frame groove for product, and corrosion depth is exposes ceramic layer, the ceramic double-sided copper-clad that will be etched
The metal part of substrate does Gold plated Layer, lower caulking groove bottom tin coating；
Specifically, such as Fig. 4 after etching, corrode on the thick copper on surface and lower caulking groove 104, corrode between each unit
Intervallum 105, corresponding bottom surface is 106, and these intervallums are also dicing lane when full wafer product is scratched in the future.Entire substrate
Do gold-plated processing, such as Fig. 5, the bottom plating Gold plated Layer 600 of the ceramic double-sided copper-clad substrate, both sides plating thick copper layer 601, lower caulking groove
Bottom tin plating 300, such as Fig. 6.So far, ceramic double-sided copper-clad processing substrate finishes.
Step 2：Into the thin slice of 100um thickness, wafer frontside grid and source electrode expose full wafer MOSFET grinding wafers
Part Gold plated Layer processing, wafer rear drain electrode do metal layer, single MOSFET chip 200 are diced into by design size；
Specifically, it is sheet during high-power MOS FET wafers output, thickness is in 600um or so, to optimize leading for its own
Be powered the thermal resistance of resistance and raceway groove to outside, is thinned to 50~200um.Chip back plates metal 201, and the composition of metal is
The combination of titanium, nickel, silver, gold, tin, the following region metal cladding 700 for planting tin ball of chip surface, increase and the adhesion of tin.Under
One step, full wafer wafer are attached on blue film, then carry out piece, are scratched at film channel 206, and every turns into relatively independent chip.
Step 3：The single MOSFET chip pulled is transferred to the lower caulking groove of ceramic double-sided copper-clad substrate, full wafer ceramics are double
Chip and substrate are bonded to together by face copper-clad base plate heating；
Step 4：The surface printing insulation material layer of the single MOSFET chip；
Step 5：Three electrodes of the single MOSFET chip plant multiple tin balls；
Step 6：Whole plate test, it is diced into single finished product.
Specifically, after electrode is drawn, functional test can be carried out, defective products is marked with ink dot.Last scribing, reject bad
Product, obtain finished product metal-oxide-semiconductor as shown in Figure 9.
The foregoing is only a preferred embodiment of the present invention, is not intended to limit the scope of the present invention.
Claims (7)
1. a kind of high-power MOS FET's is fanned out to shape encapsulating structure, it is characterised in that including the ceramics set gradually from down to up
Single MOSFET chip, the tin ball that double-sided copper-clad substrate, Gold plated Layer, high-power MOS FET wafers are formed after scribing, the pottery
The lower caulking groove for built-in single MOSFET chip is provided with porcelain double-sided copper-clad substrate, is set on the single MOSFET chip
There are grid, source electrode and drain electrode, the tin ball includes the first tin ball, the second tin ball, the 3rd tin ball, the 4th tin ball, first tin
Ball is located at the outer both sides of lower caulking groove and the drain electrode for drawing finished product is contacted with Gold plated Layer, and the second tin ball, which is located on grid, to be used
In the grid for drawing finished product, the 3rd tin ball, the 4th tin ball are located at the upper source electrode for being used to draw finished product on source electrode.
2. high-power MOS FET's according to claim 1 is fanned out to shape encapsulating structure, it is characterised in that the ceramics are two-sided
Copper-clad base plate includes back side thin copper layer, ceramic layer, the thick copper layer set gradually from down to up, is provided with and is used on the thick copper layer
The lower caulking groove of built-in single MOSFET chip.
3. high-power MOS FET's according to claim 1 or 2 is fanned out to shape encapsulating structure, it is characterised in that described second
Regional metal layer is provided between tin ball, the 3rd tin ball, the 4th tin ball and grid or source electrode.
4. high-power MOS FET's according to claim 3 is fanned out to shape encapsulating structure, it is characterised in that the ceramics are two-sided
The bottom of copper-clad base plate is provided with Gold plated Layer, and both sides are provided with thick copper layer.
5. high-power MOS FET's according to claim 4 is fanned out to shape encapsulating structure, it is characterised in that described single
The gap of MOSFET chips and single MOSFET chips side wall and the gap of lower caulking groove are provided with insulation material layer.
6. high-power MOS FET's according to claim 5 is fanned out to shape encapsulating structure, it is characterised in that described single
The surface of MOSFET chips is provided with passivation layer except other regions of tin ball bottom.
7. a kind of high-power MOS FET manufacturing process for being fanned out to shape encapsulating structure, it is characterised in that the technique passes through following step
It is rapid to realize：
Step 1：Ceramic double-sided copper-clad substrate cut into wafer size, using precise etching method in ceramic double-sided copper-clad substrate
Thick copper face corrode the surface circumferential side frame groove of the lower caulking groove for be put into single MOSFET chip 200, product, in thin copper face
Corrode the back side circumferential side frame groove for product, corrosion depth is exposes ceramic layer, the ceramic double-sided copper-clad substrate that will be etched
Metal part do Gold plated Layer, lower caulking groove bottom tin coating；
Step 2：Full wafer MOSFET grinding wafers are into the thin slice of 100um thickness, wafer frontside grid and source electrode exposed portion
Gold plated Layer processing, wafer rear drain electrode do metal layer, single MOSFET chip are diced into by design size；
Step 3：The single MOSFET chip pulled is transferred to the lower caulking groove of ceramic double-sided copper-clad substrate, full wafer ceramics are two-sided to be covered
Chip and substrate are bonded to together by copper base heating；
Step 4：The surface printing insulation material layer of the single MOSFET chip；
Step 5：Three electrodes of the single MOSFET chip plant multiple tin balls；
Step 6：Whole plate test, it is diced into single finished product.
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