CN106298692A - Chip package base plate, chip-packaging structure and preparation method thereof - Google Patents
Chip package base plate, chip-packaging structure and preparation method thereof Download PDFInfo
- Publication number
- CN106298692A CN106298692A CN201510200591.1A CN201510200591A CN106298692A CN 106298692 A CN106298692 A CN 106298692A CN 201510200591 A CN201510200591 A CN 201510200591A CN 106298692 A CN106298692 A CN 106298692A
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- Prior art keywords
- layer
- chip
- conductive circuit
- conductive
- circuit layer
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 31
- 238000002360 preparation method Methods 0.000 title description 5
- 238000003466 welding Methods 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims description 54
- 239000002184 metal Substances 0.000 claims description 54
- 229910052751 metal Inorganic materials 0.000 claims description 54
- 239000000463 material Substances 0.000 claims description 40
- 238000000465 moulding Methods 0.000 claims description 40
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 33
- 239000010931 gold Substances 0.000 claims description 32
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 31
- 229910052737 gold Inorganic materials 0.000 claims description 31
- 229910052759 nickel Inorganic materials 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 12
- 238000007747 plating Methods 0.000 claims description 6
- 238000005253 cladding Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000000295 complement effect Effects 0.000 claims description 2
- 238000011161 development Methods 0.000 claims description 2
- 238000001035 drying Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 212
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 12
- 229910052802 copper Inorganic materials 0.000 description 12
- 239000010949 copper Substances 0.000 description 12
- 239000000084 colloidal system Substances 0.000 description 8
- 238000012856 packing Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000007654 immersion Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 238000011010 flushing procedure Methods 0.000 description 3
- 239000003973 paint Substances 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 239000012778 molding material Substances 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 229920006336 epoxy molding compound Polymers 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- NIFIFKQPDTWWGU-UHFFFAOYSA-N pyrite Chemical compound [Fe+2].[S-][S-] NIFIFKQPDTWWGU-UHFFFAOYSA-N 0.000 description 1
- 229910052683 pyrite Inorganic materials 0.000 description 1
- 239000011028 pyrite Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The present invention relates to a kind of chip package base plate, comprising: help layer, first conductive circuit layer, conductive pole and welding resisting layer, described welding resisting layer includes multiple first opening, described layer and described first conductive circuit layer is helped to be both formed in multiple described first opening, described first conductive circuit layer helps the surface of layer, described conductive pole to be formed at the surface of described first conductive circuit layer described in being formed at, and extends to the surface away from described first conductive circuit layer.The present invention also provides for a kind of chip-packaging structure and the manufacture method of a kind of chip-packaging structure.
Description
Technical field
The present invention relates to a kind of chip package base plate, chip-packaging structure and preparation method thereof.
Background technology
Chip package base plate due to can be chip provide electrically connect, protect, support, dispel the heat, the merit such as assembling
Effect, is widely used in electronic product.Along with the lightening development of electronic product, chip package
Substrate is the most lightening.Chip-packaging structure includes chip package base plate and is arranged on chip package base
Chip on plate.But, it is provided that a kind of lightening chip package base plate is those skilled in the art's letter
Problem to be solved.
Summary of the invention
In view of this, it is necessary to provide a kind of and can solve the chip package base plate of the problems referred to above, chip package
Structure and preparation method thereof.
A kind of chip package base plate, comprising: help layer, the first conductive circuit layer, conductive pole are with anti-welding
Layer, described welding resisting layer includes multiple first opening, described in help layer and the described first equal shape of conductive circuit layer
Become in multiple described first openings, described first conductive circuit layer be formed at described in help the surface of layer,
Described conductive pole is formed at the surface of described first conductive circuit layer, and to away from described first conducting wire
The surface of layer extends.
A kind of chip-packaging structure, comprising: chip package base plate and chip；Described chip package base plate
It includes helping layer, the first conductive circuit layer, conductive pole and welding resisting layer, and described welding resisting layer includes multiple
One opening, described in help layer and described first conductive circuit layer to be both formed in multiple described first opening,
Described first conductive circuit layer helps the surface of layer described in being formed at, and described conductive pole is formed at described first
The surface of conductive circuit layer also extends to the surface away from described first conductive circuit layer, described chip and institute
State and help layer to be electrically connected with.
A kind of manufacture method of chip-packaging structure, including step:
Thering is provided double-sided copper-clad substrate, described double-sided copper-clad substrate includes insulating barrier, is positioned at insulating barrier opposing two
The first metal layer on individual surface and the second metal level；
Form welding resisting layer on described the first metal layer surface, described welding resisting layer includes multiple first opening, the
One opening exposes the described the first metal layer of part；
Described first opening is formed and helps layer, helping layer surface to form the first conductive circuit layer,
The surface away from described the first metal layer of described first conductive circuit layer forms conductive pole；
Form the 3rd opening, institute to the direction of the first metal layer from the second metal level in double-sided copper-clad substrate
State the 3rd opening and expose part welding resisting layer and described first conductive circuit layer；
Help layer surface configuration one chip described, form described chip-packaging structure.
Compared with prior art, the making of chip package base plate and chip-packaging structure that the present invention provides
Method, is formed at the first conductive circuit layer between the first opening in described welding resisting layer, reduces chip
The thickness of encapsulating structure, the fine rule road also helping conducting wire makes.
Accompanying drawing explanation
Fig. 1 is the generalized section of the double-sided copper-clad substrate that first embodiment of the invention provides.
Fig. 2 is the welding resisting layer of formation on the first metal layer in Fig. 1 and forms first on the second metal level
The generalized section on barrier layer.
Fig. 3 is the generalized section forming layer gold on the first metal layer surface.
Fig. 4 is the generalized section forming nickel dam on the basis of Fig. 4.
Fig. 5 is the generalized section forming internal layer circuit layer on the basis of Fig. 5.
Fig. 6 is to form the 3rd barrier layer on the surface of described welding resisting layer, and at described second layer on surface of metal
Described layers of copper surface formed the 4th barrier layer generalized section.
Fig. 7 is the generalized section forming conductive pole on the surface of described wire line layer.
Fig. 8 is the generalized section after the described conductive pole forming Fig. 7 is ground.
Fig. 9 is the generalized section removing the 3rd barrier layer with the 4th barrier layer.
Figure 10 is the generalized section forming moulding material on the basis of Fig. 9.
Figure 11 is the generalized section after being ground the moulding material described in Figure 10.
Figure 12 is the generalized section forming the 4th barrier layer in described layers of copper and described moulding material surface.
Figure 13 forms opening on the basis of Figure 12 on described second metal level and exposes described layer gold
Generalized section.
Figure 14 is the generalized section removing described 4th barrier layer.
Figure 15 is the generalized section arranging the chip-packaging structure that chip obtains on the basis of Figure 14.
Main element symbol description
| Chip package base plate | 100 |
| Double-sided copper-clad substrate | 10 |
| Insulating barrier | 11 |
| The first metal layer | 12 |
| Second metal level | 13 |
| Through hole | 14 |
| Welding resisting layer | 21 |
| First barrier layer | 22 |
| First opening | 210 |
| Help layer | 31 |
| Layer gold | 32 |
| Nickel dam | 33 |
| Layers of copper | 35 |
| First conductive circuit layer | 34 |
| Second conductive circuit layer | 36 |
| Conductive pole | 44 |
| Second barrier layer | 41 |
| 3rd barrier layer | 42 |
| Second opening | 410 |
| Chip bearing unit | 50 |
| Moulding material | 45 |
| 3rd opening | 51 |
| 4th barrier layer | 61 |
| Chip | 70 |
| Soldered ball | 71 |
| Bonding lead | 72 |
| Chip-packaging structure | 200 |
| Bottom surface | 211 |
| Upper surface | 212 |
| Conductive hole | 15 |
| Circuit base plate | 101 |
| Packing colloid | 73 |
Following detailed description of the invention will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Detailed description of the invention
The chip package base plate that the technical program provided below in conjunction with drawings and Examples, chip package
Structure and preparation method thereof is described in further detail.
The manufacture method of the chip package base plate 100 that the technical program the first embodiment provides, including step
Rapid:
The first step, refers to Fig. 1, it is provided that a double-sided copper-clad substrate 10.Described double-sided copper-clad substrate 10
The first metal layer 12 including insulating barrier 11, laying respectively at opposing two surfaces of insulating barrier 11 and the second gold medal
Belong to layer 13 and at least one through hole 14.Described the first metal layer 12 and described second metal level 13
Material can be copper, ferrum or pyrite etc..In the present embodiment, described the first metal layer 12 with
The material of described second metal level 13 is copper.
Second step, refers to Fig. 2-5, forms the first conductive circuit layer 34 and the second conductive circuit layer 36.
Wherein form described first conductive circuit layer 34 and the second conductive circuit layer 36 include step:
First, double-sided copper-clad substrate 10 is carried out, removes its surface and the dirt of through hole 14 inwall
Stain, is beneficial to the carrying out of subsequent step.
Secondly, refer to Fig. 2, form welding resisting layer 21 on described the first metal layer 12 surface, second
Metal level 13 surface forms the first barrier layer 22.Described welding resisting layer 21 is formed many by exposure imaging processing procedure
Individual first opening 210, thus at the first opening 210, expose the described the first metal layer of part 12.Institute
State the first barrier layer 22 and second metal level 13 is completely covered.Described welding resisting layer 21 is anti-welding green paint (Solder
Mask), its thickness is about 30um, and described first barrier layer 22 is dry film solder mask (Dry film).When
So, described first barrier layer 22 can also replace with the coverlay of low viscosity (i.e. easily removing), glue
The shelters such as band.
Thirdly, see also Fig. 3-4, at the first metal layer 12 that described first opening 210 exposes
On plate and help layer 31.This helps layer 31 selected from electroless nickel layer, plating layer gold, electroless nickel plating layer gold
(electroless Ni/Au), immersion silver (immersion silver), immersion tin (immersion tin).At this
In embodiment, described in help layer 31 to include electroplating layer gold 32 and electroless nickel layer 33, described layer gold 32
Being positioned at the surface of described the first metal layer 12, described nickel dam 33 is positioned at the surface of described layer gold 32.Institute
The thickness stating layer gold 32 is about 0.3um.
And then, refer to Fig. 5, remove described first barrier layer 22, in the hole of described through hole 14
One layer of layers of copper of electroplating surface of wall, the surface of described nickel dam 33 and described second metal level 13, is positioned at
The layers of copper on nickel dam 33 surface forms the first described conductive circuit layer 34, described second metal level 13 surface
Layers of copper 35 and described second metal level 13 be collectively forming the second conductive circuit layer 36, described second conduction
Line layer 36 is for realizing the increasing layer of chip-packaging structure.Wherein, described first conductive circuit layer 34 with
Described welding resisting layer 21 keeps concordant.This step achieves and has been formed at anti-welding by the first conductive circuit layer 34
In the first opening 210 that layer 21 is formed.Welding resisting layer 21 in the present invention refers to anti-welding green paint, by
Less in the molecule of anti-welding green paint material, intermolecular gap is less than 10um, by the first conductive circuit layer
34 are embedded in the first opening being placed in welding resisting layer 21, thus can also make leading of the first conductive circuit layer 34
The thickness of electric line drops to 10um, namely the making on beneficially fine rule road.The inwall of described through hole 14
It is plated layers of copper, for realizing the first metal layer 12 and second metal on opposing two surfaces of insulating barrier 11
Electrically conducting of layer 13.
In the present embodiment, it is covered in described due to described the first metal layer 12 and the second metal level 13
The whole surface of insulating barrier 11, so described the first metal layer 12 and the second metal level 13 can conducts
The path of electric current conduction, so helping layer 31 and in described the first conduction helping plating on layer 31
Line layer 34 and the second conductive circuit layer 36 all can utilize electroless plating wire (Bussless) to electroplate
Mode is formed, namely just can realize plating help layer 31 to lead with first without additionally arranging electroplated lead
Electric line layer 34.
3rd step, refers to Fig. 6-9, forms multiple conduction on the surface of described first conductive circuit layer 34
Post 44.Wherein form described conductive pole 44 and include step:
First, refer to Fig. 6, in described first conductive circuit layer in the surface of described welding resisting layer 21 and part
The surface of 34 forms the second barrier layer 41, and forms the 3rd on the surface of described second conductive circuit layer 36
Barrier layer 42.In the present embodiment, described second barrier layer 41 and described 3rd barrier layer 42 are dry film.
In the present embodiment, described second barrier layer 41 forms multiple second opening through exposure imaging process
410, the first conductive circuit layer 34 described in described second opening 410 expose portion.
Secondly, Fig. 7 is referred to, in described first conducting wire exposed from described second opening 410
On layer 34, plating forms described conductive pole 44.Described conductive pole 44 away from described first conductive circuit layer
One end of 34 protrudes from the diameter of conductive pole 44 described in described second barrier layer 41 and is about 150um, length
It is about 90um.
Then, refer to Fig. 8, described conductive pole 44 be ground, make described conductive pole 44 away from
The end face of described first conductive circuit layer 34 keeps flushing and is beneficial to follow-up be attached with other circuit board
Or realize on the surface of conductive pole 44 increasing layer.Certainly, this step is not necessary to, it is also possible to follow-up
Carry out again described conductive pole 44 is ground after forming moulding material 45.
Finally, refer to Fig. 9, remove described welding resisting layer 21 and described first conductive circuit layer 34 surface
Described second barrier layer 41 and described 3rd barrier layer 42 on the second conductive circuit layer 36 surface.
4th step, refers to Figure 10, forms moulding material on the surface of described first conductive circuit layer 34
(Molding material) 45, obtains a chip bearing unit 50, and described moulding material 45 is coated with
Described first conductive circuit layer 34 and described conductive pole 44.
Refer to Figure 11, also include after forming described moulding material 45 grinding described moulding material 45, make
Described moulding material 45 away from described first conductive circuit layer 34 surface and described conductive pole 44 away from
The surface of described first conductive circuit layer 34 keeps flushing, and to expose described conductive pole 44, exposes institute
State the described conductive pole 44 in moulding material 45 for increasing layer or welding other circuit boards.Described molding
The thermal coefficient of expansion of material 45 is suitable with the thermal coefficient of expansion of the follow-up chip 70 needing encapsulation.In this reality
Executing in mode, described moulding material 45 is epoxy resin, and the value of its thermal coefficient of expansion CTE is about
3～6ppm/ DEG C, and be by the way of molding (Molding), form moulding material 45, such as,
The complementary structure of die cavity, the structure of described die cavity and described conductive pole 44 can be made in advance, then will
Third step final (removing the structure behind described second barrier layer 41 and described 3rd barrier layer 42) shape
The structure become is put in described die cavity, is flowed into by moulding material and fill up described die cavity in the way of mould stream,
Make described first conductive circuit layer 34 of described moulding material cladding and described conductive pole 44, treat described molding
Material carries out the demoulding after drying, and described moulding material 45 i.e. can be coated with described conductive pole 44.
5th step, refers to Figure 12-13, on described chip bearing unit 50, from the second conducting wire
Layer 36 offers one the 3rd opening 51 of formation along near described welding resisting layer 21, and described 3rd opening 51 is sudden and violent
Expose described layer gold 32 and the described welding resisting layer of part 21.Wherein, the method forming described 3rd opening 51
Including:
First, refer to Figure 12, respectively at described second conductive circuit layer 36 and described moulding material 45
Surface formed the 4th barrier layer 61, described 4th barrier layer 61 is photosensitive dry film.
Secondly, refer to Figure 13, etch away the part layers of copper not covered by described 4th barrier layer 61
35, the second metal level 13, cut are removed described insulating barrier 11 and etch away described first gold medal
Belonging to layer 12 thus form described 3rd opening 51, the most described 3rd opening 51 exposes described layer gold
32 and the described welding resisting layer of part 21.
Refer to Figure 14, remove described 4th barrier layer 61, thus obtain chip package base plate 100.?
In present embodiment, also include after removing described 4th barrier layer 61 described layer gold 32 surface is carried out clearly
Clean process processes with surface, and (figure is not to weld film described one layer of organic guarantor of conductive pole 44 Surface Creation
Show) (Organic Solderability Preservatives, OSP).
6th step, refers to Figure 15, by routing combination technology, surface mounting technology or chip package
Described chip 70 structure is loaded on the 3rd opening 51 that is exposed at described chip package base plate 100 by technology
Position thus form chip-packaging structure 200.Chip 70 can include memory chip, logic chip
Or digit chip.Wherein, the second conductive circuit layer 36 of this chip-packaging structure 70 is used for realizing core
The circuit of chip package increases layer.
In the present embodiment, the thermal coefficient of expansion of described chip 70 (Coefficient of thermal expansion,
CTE) it is about 2.6ppm/ DEG C.Namely the thermal coefficient of expansion of moulding material and the thermal expansion of chip in this case
Coefficient is suitable, such that it is able to prevent chip warpage.
In the present embodiment, described chip 70 is by flip chip packaging technologies (Flip Chip Technology)
Structure helps the surface of layer 31 described in being loaded on, and specifically, one of them surface of chip 70 is to pass through soldered ball
71 are welded in described layer gold 32 surface, and another surface is electrical with described layer gold 32 by bonding lead 72
Connect (wire bonding, routing combination technology), thus realize chip 70 and chip package base plate 100
Signal transmission.Packing colloid 73 also it is perfused with, preferably between described chip 70 and described layer gold 32
Ensure the stability after described chip 70 and the encapsulation of described chip package base plate 100.Specifically, can lead to
Over-molded (molding) technology arranges packing colloid 73 at described 3rd opening 51, described to obtain
Chip package base plate 100.In the present embodiment, the packing colloid 73 being positioned in the 3rd opening 51 with
The surface of the layers of copper 35 being positioned at the second metal level 13 surface keeps flushing.
Referring to Figure 15, the present invention also provides for a kind of by said chip encapsulating structure manufacture method system
The chip-packaging structure 200 become.Described chip-packaging structure 200 includes: chip package base plate 100 with
Chip 70.
Described chip package base plate 100 include welding resisting layer 21, help layer the 31, first conductive circuit layer 34,
Conductive pole 44, moulding material 45 and circuit base plate 101.
Described circuit base plate 101 includes: the first metal layer 12, be positioned at described the first metal layer 12 surface
Insulating barrier 11, be positioned at insulating barrier 11 surface the second conductive circuit layer 36.Described insulating barrier 11
In be provided with conductive hole 15, described conductive hole 15 is used for turning on the first metal layer 12 and the second metal level
13.Described second conductive circuit layer 36 includes the second metal level 13 and the position being positioned at insulating barrier 11 surface
Layers of copper 35 in the second metal level 13 surface.
Described welding resisting layer 21 is formed at the surface of described the first metal layer 12.Described welding resisting layer 21 includes
Multiple first openings 210, described in help layer 31 and described first conductive circuit layer 34 to be both formed in described
In first opening 210, described in help layer 31 to include layer gold 32 and nickel dam 33, described in help layer 31 first
Being formed in described first conductive circuit layer 34, described nickel dam 33 is formed at the surface of described layer gold 32,
Described first conductive circuit layer 34 is formed at the surface of described nickel dam 33.Described circuit base plate 101 includes
One the 3rd opening 51, welding resisting layer 21 described in the 3rd opening 51 expose portion and described layer gold 32.
Described welding resisting layer 21 includes a bottom surface 211 and the upper surface 212 opposing with bottom surface.Described first
Conductive circuit layer 34 flushes with described bottom surface 211, and described layer gold 32 is away from described first conductive circuit layer
The surface of 34 flushes with described upper surface 212.
Described conductive pole 44 is formed at the surface of described first conductive circuit layer 34 and to away from described first
The surface of conductive circuit layer 34 extends, and described moulding material 45 is formed at the bottom surface of described welding resisting layer 21
211 and covering part described in the first conductive circuit layer 34 and conductive pole 44, described conductive pole 44 is away from institute
The surface stating the first conductive circuit layer 34 flushes with described moulding material 45.
Described chip 70 is arranged on the position of described 3rd opening 51.Described chip 70 is by described
Soldered ball 71 is fixing with described chip package base plate 100 to be connected, it addition, in present embodiment, described
Chip 70 is additionally provided with bonding lead 72 away from the surface of described layer gold 32, described bonding lead 72
Two ends connect described chip 70 and described layer gold 32 respectively, thus realize chip 70 and chip package base plate
The signal transmission of 100.Packing colloid 73 also it is perfused with, more between described chip 70 and described layer gold 32
Ensure well described chip 70 and described chip package base plate 100 encapsulation after between stability.
In the present embodiment, also include after being provided with by chip 70 position of the 3rd opening 51 is filled out
Fill packing colloid 73, make packing colloid 73 be coated with this bonding lead 72, chip 70 and chip package base
The welding resisting layer 21 exposed of plate 100 and help organic guarantor on layer 31 surface to weld film, thus by chip 70
It is embedded in the 3rd opening 51 that circuit base plate 101 is formed.In the present embodiment, this packing colloid 73
For black glue or epoxy molding plastic (epoxy molding compound).
In sum, the chip package base plate of present invention offer and the manufacture method of chip-packaging structure, will
First conductive circuit layer is formed between the first opening in described welding resisting layer, reduces chip-packaging structure
Thickness, also help conducting wire fine rule road make.
It is understood that for the person of ordinary skill of the art, can be according to the skill of the present invention
Other various corresponding changes and deformation is made in art design, and all these change all should belong to this with deformation
Invention scope of the claims.
Claims (13)
1. a chip package base plate, comprising: help layer, the first conductive circuit layer, conductive pole are with anti-
Layer, described welding resisting layer includes multiple first opening, described in help layer equal with described first conductive circuit layer
Be formed in multiple described first opening, described first conductive circuit layer be formed at described in help the table of layer
Face, described conductive pole is formed at the surface of described first conductive circuit layer, and to away from described first conduction
The surface of line layer extends.
2. chip package base plate as claimed in claim 1, it is characterised in that described chip package base plate
Also including moulding material, the first conductive circuit layer described in described moulding material shape covering part and cladding are described
Conductive pole, described conductive pole is away from surface mutually neat with described moulding material of described first conductive circuit layer
Flat.
3. chip package base plate as claimed in claim 2, it is characterised in that described base plate for packaging also wraps
Vinculum base board, described circuit base plate includes the first metal layer being positioned at welding resisting layer surface, is positioned at the first gold medal
Belong to insulating barrier and second conductive circuit layer on layer surface, described insulating barrier is provided with conductive hole, described
Conductive hole conducting the first metal layer and the second conductive circuit layer, described circuit base plate includes that one the 3rd is opened
Mouthful, help layer and the described welding resisting layer of part, the position of described 3rd opening described in described 3rd opening exposure
Chip is set.
4. chip package base plate as claimed in claim 3, it is characterised in that described in help layer to include gold
Layer and nickel dam, described 3rd opening exposes described layer gold and the described welding resisting layer of part, described first conductor wire
Road floor is formed at the surface of described nickel dam.
5. a chip-packaging structure, comprising: chip package base plate and chip；Described chip package base
Plate it include helping layer, the first conductive circuit layer, conductive pole and welding resisting layer, described welding resisting layer includes multiple
First opening, described in help layer and described first conductive circuit layer to be both formed in multiple described first opening
In, described first conductive circuit layer be formed at described in help the surface of layer, described conductive pole to be formed at described
The surface of the first conductive circuit layer also extends to the surface away from described first conductive circuit layer, described chip
Layer is helped to be electrically connected with described.
6. chip-packaging structure as claimed in claim 5, it is characterised in that described chip package base plate
Also including moulding material, the first conductive circuit layer described in described moulding material shape covering part and cladding are described
Conductive pole, described conductive pole is away from surface mutually neat with described moulding material of described first conductive circuit layer
Flat.
7. chip-packaging structure as claimed in claim 6, it is characterised in that the heat of described moulding material
The coefficient of expansion is close with the thermal coefficient of expansion of described chip.
8. chip-packaging structure as claimed in claim 6, it is characterised in that described base plate for packaging also wraps
Vinculum base board, described circuit base plate includes the first metal layer being positioned at welding resisting layer surface, is positioned at the first gold medal
Belong to insulating barrier and second conductive circuit layer on layer surface, described insulating barrier is provided with conductive hole, described
Conductive hole conducting the first metal layer and the second conductive circuit layer, described circuit base plate includes that one the 3rd is opened
Mouthful, helping layer and the described welding resisting layer of part described in described 3rd opening expose portion, described chip is contained in
Described 3rd opening.
9. a manufacture method for chip-packaging structure, including step:
Thering is provided double-sided copper-clad substrate, described double-sided copper-clad substrate includes insulating barrier, is positioned at insulating barrier opposing two
The first metal layer on individual surface and the second metal level；
Form welding resisting layer on described the first metal layer surface, described welding resisting layer includes multiple first opening, the
One opening exposes the described the first metal layer of part；
Described first opening is formed and helps layer, helping layer surface to form the first conductive circuit layer,
The surface away from described the first metal layer of described first conductive circuit layer forms conductive pole；
Form the 3rd opening, institute to the direction of the first metal layer from the second metal level in double-sided copper-clad substrate
State the 3rd opening expose part welding resisting layer and described help layer；
Put a chip at described 3rd open inner, and make to help layer described in the electrical connection of described chip, formed
Described chip-packaging structure.
10. the manufacture method of chip-packaging structure as claimed in claim 9, it is characterised in that formed
Being additionally included on the surface of described welding resisting layer formation moulding material before chip, described moulding material is coated with institute
Stating the first conductive circuit layer and described conductive pole, described conductive pole is away from the table of described first conductive circuit layer
Face flushes away from the surface of described conductive circuit layer with described moulding material.
The manufacture method of 11. chip-packaging structures as claimed in claim 9, it is characterised in that described in help
Layer includes nickel dam and layer gold, and described layer gold is formed prior to described nickel dam, and described first conductive circuit layer is formed
On the surface of described nickel dam, described chip is arranged on described layer gold surface.
The manufacture method of 12. chip-packaging structures as claimed in claim 9, it is characterised in that form institute
State conductive pole and include step:
The second barrier layer and the 3rd is formed on the described surface of the first conductive circuit layer and the surface of welding resisting layer
Barrier layer, is exposed development to described second barrier layer, makes second group to work as and is shaped as multiple second opening,
First conductive circuit layer described in described second opening expose portion；
Conductive pole is formed to carrying out plating in described first conductive circuit layer exposed from described second opening；
Remove described 3rd barrier layer and the 4th barrier layer.
The manufacture method of 13. chip-packaging structures as claimed in claim 9, it is characterised in that form institute
State moulding material and include step:
Make the complementary structure of die cavity, the structure of described die cavity and described conductive pole；
Carrier after forming conductive pole is put in described die cavity；
In the way of mould stream, moulding material flowed into and fill up described die cavity, making moulding material cladding described the
One conductive circuit layer and described conductive pole, treat that described moulding material carries out the demoulding, described mold member after drying
Material is i.e. coated with described first conductive circuit layer and described conductive pole.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510200591.1A CN106298692B (en) | 2015-04-24 | 2015-04-24 | The production method of chip-packaging structure |
| TW104113605A TWI562293B (en) | 2015-04-24 | 2015-04-28 | Manufacturing method of chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510200591.1A CN106298692B (en) | 2015-04-24 | 2015-04-24 | The production method of chip-packaging structure |
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| CN106298692A true CN106298692A (en) | 2017-01-04 |
| CN106298692B CN106298692B (en) | 2019-02-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201510200591.1A Active CN106298692B (en) | 2015-04-24 | 2015-04-24 | The production method of chip-packaging structure |
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| CN (1) | CN106298692B (en) |
| TW (1) | TWI562293B (en) |
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| CN108461405A (en) * | 2017-02-21 | 2018-08-28 | 碁鼎科技秦皇岛有限公司 | Line carrier plate and its manufacturing method |
| CN109935521A (en) * | 2019-01-30 | 2019-06-25 | 深圳市志金电子有限公司 | Package substrate manufacturing process, package substrate and chip-packaging structure |
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Also Published As
| Publication number | Publication date |
|---|---|
| TWI562293B (en) | 2016-12-11 |
| CN106298692B (en) | 2019-02-01 |
| TW201639089A (en) | 2016-11-01 |
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