CN107863292A - A kind of semiconductor devices and its manufacture method and electronic installation - Google Patents
A kind of semiconductor devices and its manufacture method and electronic installation Download PDFInfo
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- CN107863292A CN107863292A CN201610843992.3A CN201610843992A CN107863292A CN 107863292 A CN107863292 A CN 107863292A CN 201610843992 A CN201610843992 A CN 201610843992A CN 107863292 A CN107863292 A CN 107863292A
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- floating boom
- plough groove
- fleet plough
- groove isolation
- isolation structure
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- 238000007667 floating Methods 0.000 claims abstract description 190
- 238000002955 isolation Methods 0.000 claims abstract description 86
- 239000000463 material Substances 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 51
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- 230000014759 maintenance of location Effects 0.000 description 4
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- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- JTCFNJXQEFODHE-UHFFFAOYSA-N [Ca].[Ti] Chemical compound [Ca].[Ti] JTCFNJXQEFODHE-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention provides a kind of semiconductor devices and its manufacture method and electronic installation, is related to technical field of semiconductors.This method includes：The first floating gate material layer is formed on the surface of the Semiconductor substrate；Some fleet plough groove isolation structures and the first floating boom isolated by the fleet plough groove isolation structure are formed in the Semiconductor substrate, wherein, the top surface of the fleet plough groove isolation structure is higher than the top surface of first floating boom；Etch-back is carried out to the fleet plough groove isolation structure exposed, to reduce the width of the fleet plough groove isolation structure exposed；The second floating boom is formed, to cover the first floating boom and fill the gap between fleet plough groove isolation structure, and the top surface of the second floating boom flushes with the top surface of fleet plough groove isolation structure；The part of the fleet plough groove isolation structure between adjacent second floating boom is removed, so as to form the T-shaped floating boom including the first floating boom and the second floating boom.The method of the present invention, maintains less active area dimensions, and remain able to meet high request of the device for coupling ratio.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacture method and electronics
Device.
Background technology
Memory is used to store a large amount of digital informations, and nearest investigation is shown, worldwide, memory chip is about
The 30% of semiconductor transaction is account for, for many years, the progress of technology and the market demand expedite the emergence of more and more highdensity various
Type memory.
Random access memory, such as DRAM and SRAM (SRAM) are deposited store number after a power failure in use
The problem of according to losing.In order to overcome this problem, people have designed and have developed a variety of nonvolatile memories.Recently, base
In the flash memory of floating boom concept, because there is small unit size and good service behaviour to have turned into most general non-volatile for it
Memory.
Flash memories are FLASH, and it turns into the main flow of non-volatile semiconductor storage technology, various
In FLASH devices, embedded flash memory is on-chip system (SOC) one kind, in a piece of integrated circuit simultaneously integrated logic circuit
Module and flash memory circuit module, have been widely used in the products such as smart card, microcontroller.In the flash memory of embedded logic circuit
Memory technology is gradually ripe, in the evolution that storage speed is constantly accelerated, cost is gradually reduced, and people start to make it
Method proposes new requirement.
Embedded flash memory memory is faced with the different desired challenges with application of logic circuit module of balance flash memory circuit module.
Physically, as the continuous diminution of chip size, the critical size (CD) of active area (AA) also become less and less therewith.So
And consider from flash memory capability performance perspective, higher coupling ratio (coupling ratio) is advantageous to embedded flash memory memory
With good performance, such as more preferable programmed and erased velocity efficiency (speed efficiency) performance, it is therefore desirable to more
Big active area (AA) size, to improve coupling ratio.
Therefore, how on the premise of keeping active area that there is small critical size, remain able to meet device for coupling
The requirement of composition and division in a proportion, it is one of our urgent problems to be solved.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In view of the shortcomings of the prior art, a kind of manufacture method of semiconductor devices is provided in the embodiment of the present invention one, including：
Semiconductor substrate is provided, the first floating gate material layer is formed on the surface of the Semiconductor substrate；
Form some fleet plough groove isolation structures in the Semiconductor substrate, and formed by the fleet plough groove isolation structure every
From the first floating boom, wherein, the top surface of the fleet plough groove isolation structure is higher than the top surface of first floating boom；
Etch-back is carried out to the fleet plough groove isolation structure exposed, to reduce the fleet plough groove isolation structure exposed
Width；
The second floating boom is formed, to cover first floating boom and fill the gap between the fleet plough groove isolation structure, and
The top surface of second floating boom flushes with the top surface of the fleet plough groove isolation structure；
The part of the fleet plough groove isolation structure between adjacent second floating boom is removed, is floated so as to form T-shaped
Grid, the T-shaped floating boom include first floating boom and second floating boom.
Further, before the first floating gate material layer is formed, the surface for being additionally included in the Semiconductor substrate is formed
The step of tunnel oxide.
Further, the step of forming some fleet plough groove isolation structures in the Semiconductor substrate includes procedure below：
Hard mask layer is formed on the surface of the first floating gate material layer, the hard mask layer includes the nitrogen stacked gradually
Compound layer and oxide skin(coating)；
The photoresist layer of patterning is formed on the hard mask layer；
Using the photoresist layer as mask, the hard mask layer, the first floating gate material layer and part institute are etched successively
Semiconductor substrate is stated, to form some shallow trench and first floating boom in the Semiconductor substrate；
Remove the photoresist layer；
Isolation oxide is filled in the shallow trench, and the isolation oxide is planarized, is stopped at described
On the top surface of nitride layer, to form the fleet plough groove isolation structure；
The nitride layer is removed, so that the part fleet plough groove isolation structure protrudes from first floating boom.
Further, before the step of filling the isolation oxide in the shallow trench, it is additionally included in the shallow trench
Bottom and side wall on formed laying the step of.
Further, the width range at the top of the T-shaped floating boom is 20~110nm, the width range of the T-shaped floating boom bottom
For 10~80nm.
Further, the thickness range of first floating boom is 100~700 angstroms, and the thickness range of second floating boom is 100
~800 angstroms.
Further, second floating boom is formed using the method for selective epitaxial growth method or deposition.
Further, the material of first floating boom includes polysilicon, and the material of second floating boom includes Si or SiGe.
Further, the material of second floating boom is the SiGe of phosphorus doping.
Further, the material of first floating boom includes polysilicon, the material of second floating boom include polysilicon or
The polysilicon of phosphorus doping.
Further, it is further comprising the steps of after the T-shaped floating boom is formed：
The dielectric layer between formation grid on the surface that the T-shaped floating boom and the fleet plough groove isolation structure expose；
Between the grid control gate is formed on dielectric layer.
Further, the width of second floating boom is wider than the width of first floating boom 10~30 nanometers.
The present invention also provides a kind of semiconductor devices prepared using foregoing method.
The present invention also provides a kind of electronic installation, and it includes foregoing semiconductor devices.
Manufacturing method according to the invention, on the premise of semiconductor device area drastically reduces, maintaining less has
Source region size, and remain able to meet high request of the device for coupling ratio, and the data for further increasing device are kept
(Data retention) reliability, and then improve the overall performance of semiconductor devices.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
The structure for the device that Figure 1A -1D are obtained by a kind of existing correlation step for making embedded flash memory device structure
Schematic diagram；
Fig. 2 is the process chart that embedded flash memory device structure is made according to one embodiment of the present invention；
Fig. 3 A-3H are obtained to make the correlation step of embedded flash memory device structure according to one embodiment of the present invention
Device structural representation；
Fig. 4 shows the schematic diagram of the electronic installation in one embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although it can make
Various elements, part, area, floor and/or part are described with term first, second, third, etc., these elements, part, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, part, area, floor or part with it is another
One element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion
Part, area, floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with
The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to also include making
With the different orientation with the device in operation.For example, if the device upset in accompanying drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
Describe to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the change of shown shape.Therefore,
Embodiments of the invention should not necessarily be limited to the given shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, it is shown as that the injection region of rectangle generally has circle at its edge or bending features and/or implantation concentration ladder
Degree, rather than the binary change from injection region to non-injection regions.Equally, the disposal area can be caused by injecting the disposal area formed
Some injections in area between the surface passed through during injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, but except these detailed descriptions
Outside, the present invention can also have other embodiment.
The knot for the device that Figure 1A-Fig. 1 D are obtained by a kind of existing correlation step for making embedded flash memory device structure
Structure schematic diagram, simple introduction is done to the method for existing making embedded flash memory device structure with reference to figure 1A- Fig. 1 D.
First, as shown in Figure 1A, the hard mask layer for defining active area and isolated area is formed on a semiconductor substrate 100, firmly
Mask layer includes pad oxide skin(coating) 101 and pad nitride layer 102, etches Semiconductor substrate 100 according to hard mask layer to form ditch
Groove, isolated material 103 is filled in the trench, the width of the pad nitride layer 102 between isolated material 103 is (alternatively referred to as
Critical size CD) depend on active area width.
Then, as shown in Figure 1B, the pad nitride layer 102 is removed, to expose the pad oxide skin(coating) 101.
Then, as shown in Figure 1 C, well region ion implantation technology is performed, to form well region in the semiconductor substrate, and is carried out
Unit ion implantation technology.
Then, as shown in figure iD, floating gate material layer 104, the floating gate material layer are formed in the Semiconductor substrate 100
The 104 coverings pad oxide skin(coating) 101 and the isolated material 103, it is unnecessary to remove to perform cmp (CMP) technique
The floating gate material layer 104 so that the top of the floating gate material layer 104 and the isolated material 103 flushes, formed floating
Grid 104.
Physically, as the continuous diminution of chip size, the critical size (CD) of active area (AA) also become to get over therewith
Come smaller.However, considering from flash memory capability performance perspective, higher coupling ratio (coupling ratio) is advantageous to embedded sudden strain of a muscle
Depositing memory has good performance, such as more preferable programmed and erased velocity efficiency (speed efficiency) performance, because
This needs bigger active area (AA) size, to improve coupling ratio.
Therefore, how on the premise of keeping active area that there is small critical size, remain able to meet device for coupling
The requirement of composition and division in a proportion, it is one of our urgent problems to be solved.
In order to solve foregoing technical problem, the invention provides a kind of manufacture method of semiconductor devices, such as Fig. 2 institutes
Show, it is mainly included the following steps that：
Step S201, there is provided Semiconductor substrate, the first floating gate material layer is formed on the surface of the Semiconductor substrate；
Step S202, some fleet plough groove isolation structures are formed in the Semiconductor substrate, and formed by the shallow trench
First floating boom of isolation structure isolation, wherein, the top surface of the fleet plough groove isolation structure is higher than the top surface of first floating boom；
Step S203, etch-back is carried out to the fleet plough groove isolation structure exposed, to reduce the shallow trench exposed
The width of isolation structure；
Step S204, the second floating boom is formed, to cover first floating boom and fill between the fleet plough groove isolation structure
Gap, and the top surface of second floating boom flushes with the top surface of the fleet plough groove isolation structure；
Step S205, the part of the fleet plough groove isolation structure between adjacent second floating boom is removed, so as to
T-shaped floating boom is formed, the T-shaped floating boom includes first floating boom and second floating boom.
Manufacturing method according to the invention, on the premise of semiconductor device area drastically reduces, maintaining less has
Source region size, and remain able to meet device for coupling ratio high request, and the data for further increasing device keep (Data
Retention) reliability, and then improve the overall performance of semiconductor devices.
Embodiment one
Below, the manufacture method of the semiconductor devices of the present invention is described in detail with reference to figure 3A- Fig. 3 H, wherein, Fig. 3 A-
Fig. 3 H are the knot of the device obtained according to the correlation step of one embodiment of the present invention making embedded flash memory device structure
Structure schematic diagram.
First, as shown in Figure 3A, there is provided Semiconductor substrate 300, sequentially formed on the surface of the Semiconductor substrate 300
Tunnel oxide 301, the first floating gate material layer 3021a and hard mask layer 303, the hard mask layer 303 include what is stacked gradually
Nitride layer 3031 and oxide skin(coating) 3032.
The Semiconductor substrate 300 can be at least one of following material being previously mentioned：Silicon, silicon-on-insulator
(SOI) silicon (SSOI), is laminated on insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator
And germanium on insulator (GeOI) etc. (SiGeOI).As an example, in the present embodiment, the constituent material of Semiconductor substrate is selected
Monocrystalline silicon.
The Semiconductor substrate 300 includes three regions, is respectively：For forming the firstth area of logic circuit grid structure
Domain, i.e. logic region；To form the second area of high voltage transistor grid structure, i.e. high-tension circuit region；To shape
Into the grid structure of selection transistor and the 3rd region of memory cell grid structure, i.e. flash cell region.Need to illustrate
, logic region and high-tension circuit region are all to be located at peripheral circuit region in true layout.
Tunnel oxide 301 is sequentially formed on the surface of the Semiconductor substrate 300.Specifically, tunnel oxide 301
It can be formed by thermal oxide, chemical vapor deposition (CVD) or oxynitridation process.Tunnel oxide 301 can include following
Any conventional dielectric：SiO2、SiON、SiON2And other similar oxides including perofskite type oxide.Wherein, tunnel
Silica can be selected in the material for wearing oxide layer 301, and generation type uses thermal oxidation method.The thickness of the tunnel oxide of formation is several
Ten Izods are right, and in one example, the thickness of the tunnel oxide is 80 angstroms to 110 angstroms.
Afterwards, various well regions can be also formed in the semiconductor substrate by ion implantation technology etc., and unit
Doped region etc., will not be described here.
The first floating gate material layer 3021a is formed on the tunnel oxide 301.First floating gate material layer 3021a material
Polysilicon or the polysilicon of doping, such as the polysilicon of phosphorus doping, alternatively, the first floating gate material layer can be selected in material
3021a thickness range is 100~700 angstroms.
Low-pressure chemical vapor phase deposition can be selected in the forming method for forming the first floating gate material layer 3021a in the present invention
(LPCVD) technique or furnace process (Furnace).Forming the process conditions of the polysilicon layer includes：Reacting gas is silicon
Alkane (SiH4), the range of flow of the silane can be 100~300 cc/mins (sccm), such as 150sccm；In reaction chamber
Temperature range can be 700~750 degrees Celsius；It can be 250~350 milli millimetress of mercury (mTorr) to react cavity pressure, such as
300mTorr；It may also include buffer gas in the reacting gas, the buffer gas can be helium (He) or nitrogen, the helium
The range of flow of gas and nitrogen can be 5~20 liters/min (slm), such as 8slm, 10slm or 15slm.
It should be noted that above-mentioned formation the first floating gate material layer 3021a method is exemplary, it is not limited to
Methods described, as long as this area other method can realize the purpose, the present invention is can apply to, will not be repeated here.
Then, hard mask layer 303 is formed on the surface of the first floating gate material layer 3021a.
The hard mask layer includes the nitride layer 3031 and oxide skin(coating) 3032 stacked gradually, specifically, floating first
It is sequentially depositing to form nitride layer 3031 and oxide skin(coating) 3032 on gate material layer 3021a, the material of nitride layer 3031 is optional
Use silicon nitride.It can use and be formed the methods of chemical vapor deposition, physical vapour deposition (PVD) and atomic layer deposition.Oxide skin(coating)
3032 can be formed by thermal oxide, chemical vapor deposition (CVD) or oxynitridation process.Oxide skin(coating) can include following appoint
What conventional dielectric：SiO2、SiON、SiON2And other similar oxides including perofskite type oxide.Wherein, aoxidize
Silica can be selected in the material of nitride layer, and generation type uses chemical vapour deposition technique.
Then, as shown in Figure 3 B, the photoresist layer of patterning is formed on the hard mask layer 303, with the photoresist
Layer is mask, etches the hard mask layer 303, the first floating gate material layer, the tunnel oxide 301 and part institute successively
Semiconductor substrate 300 is stated, to form some shallow trench 3041 in the Semiconductor substrate 300, removes the photoresist layer.
In the specific embodiment of the present invention, the method for defining shallow trench is：Photoetching is coated with semiconductor substrate surface
Glue-line, photoresist layer is exposed and developed, predefined figure is transferred on photoresist layer, form the photoetching of patterning
Glue-line.Then be etched using the photoresist layer of patterning as mask, the part that Semiconductor substrate is not covered by photoresist by according to
Secondary etching, etch the hard mask layer 303 (including oxide skin(coating) 3032 and nitride layer 3031), first floating gate material
Layer, the tunnel oxide 301 and the part Semiconductor substrate 300, form shallow trench 3041, the bottom of the shallow trench 3041
In Semiconductor substrate 300, and form the first floating boom 3021 isolated by shallow trench 3041.
Afterwards, photoresist layer is removed by the method for ashing.
Then, as shown in Figure 3 C, isolation oxide is filled in the shallow trench 3041, and the isolation oxide is entered
Row planarization, is stopped on the top surface of the nitride layer 3031, to form fleet plough groove isolation structure 304, to isolate active area,
Wherein, the top surface of the fleet plough groove isolation structure 304 is higher than the top surface of first floating boom 3021, and the first adjacent floating boom
3021 are isolated by fleet plough groove isolation structure 304.
Exemplarily, before the step of filling the isolation oxide in the shallow trench 3041, it is additionally included in described
The step of laying (not shown) is formed on the bottom of shallow trench 3041 and side wall.Laying can be oxide, such as aoxidize
Silicon liner layer etc..
Silica can be selected in the material of isolation oxide.In an embodiment of the present invention, using HDP (high-density plasma)
Depositing operation forms isolation oxide in the shallow trench and on hard mask layer, using HDP-CVD (high-density plasmas
Learn vapour deposition) oxide skin(coating) is formed, HDP-CVD techniques are that deposition is synchronously carried out in same reaction chamber and is sputtered anti-
Should, the reacting gas that HDP-CVD techniques use includes SiH4And O2, and the gas hydrogen and helium of sputtering.Due to deposition and
Sputtering technology is carried out simultaneously, by adjusting SiH4And O2And the content of hydrogen and helium is so that sputtering sedimentation ratio is 1:1.
It should be noted that the method for above-mentioned formation isolation oxide is exemplary, it is not limited to methods described,
As long as this area other method can realize the purpose, the present invention is can apply to, will not be repeated here.
Planarization process, the top surface and nitride layer of the isolation oxide are carried out to the isolation oxide of Semiconductor substrate
3031 either flush, namely in the lump remove oxide skin(coating) 3032 during planarization, the method for planarization can be
Chemical mechanical milling method.
As shown in Figure 3 D, the nitride layer 3031 is removed, so that the part fleet plough groove isolation structure 304 protrudes from institute
State the first floating boom 3021.
Any suitable method well known to those skilled in the art can be used to remove the nitride layer 3031, including but
It is not limited to the method for wet etching or dry etching.
Wherein it is possible to using the wet etch process to nitride layer 3031 with high etch-rate, for example, using heat
Phosphoric acid solution as etchant, wet method removes the nitride layer 3031.
Then, as shown in FIGURE 3 E, etch-back is carried out to the fleet plough groove isolation structure 304 exposed, to reduce what is exposed
The width of the fleet plough groove isolation structure 304.
Specifically, the method for dry etching or wet etching can be used to the fleet plough groove isolation structure that exposes
304 carry out etch-back.
Wherein, in the present embodiment, etch-back in this step, wet etching are carried out preferably with the method for wet etching
There is high etch-rate to the isolation oxide in groove isolation construction 304, and there is low erosion for the first floating boom 3021
Etching speed.
For example, wet etching can use hydrofluoric acid solution, such as buffer oxide etch agent (buffer oxide
Etchant (BOE)) or hydrofluoric acid cushioning liquid (buffer solution of hydrofluoric acid (BHF)).
Exemplarily, after etch-back, the width of the fleet plough groove isolation structure 304 exposed is reduced to 100~1000 angstroms,
The width range according to actual process only as an example, specifically can also suitably be adjusted.
Then, as illustrated in Figure 3 F, the second floating boom 3022 is formed, to cover first floating boom 3021 and fill the shallow ridges
Gap between recess isolating structure 304, and the top surface of the top surface of second floating boom 3022 and the fleet plough groove isolation structure 304
Flush.
Alternatively, first floating boom 3021 and second floating boom 3022 can be different semi-conducting materials, for example,
The material of first floating boom 3021 includes polysilicon or the polysilicon of doping, and the polysilicon of doping can be the polysilicon of phosphorus doping,
The material of second floating boom 3022 can include the SiGe or SiGe of doping, such as the SiGe of phosphorus doping, the second floating boom 3022
Can also be the Si of epitaxial growth.
Wherein, second floating boom 3022 can also use with the identical material of the first floating boom 3021, for example, first
Floating boom 3021 is polysilicon, and the material of the second floating boom 3022 can also be polysilicon or the polysilicon of doping, such as phosphorus doping
Polysilicon.
Alternatively, the thickness range of second floating boom is 100~800 angstroms, and the numerical value is only as an example, can also be it
The numerical value that he is adapted to.
Second floating boom 3022 can also be formed using different forming methods, it is, for example, possible to use selective epitaxial
The method of growth or the deposition process of routine.
In one example, the method for selective epitaxial growth can be used to form second floating boom 3022 can use
Low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD
(UHVCVD), one kind in rapid thermal CVD (RTCVD) and molecular beam epitaxy (MBE).
For example, the material of second floating boom 3022 can include the SiGe or SiGe of doping, chemical vapor deposition can be used
Product method or gas source molecular beam epitaxy method growth SiGe, by the use of silane or disilane as silicon source, while are added certain
The germane of amount.For example, from GeH4And SiH2Cl2As reacting gas, and select H2As carrier gas, wherein reacting gas and load
The flow-rate ratio of gas is 0.01-0.1, and the temperature of deposition is 300-1000 DEG C, preferably 650-750 DEG C, gas pressure 1-
50Torr, preferably 20-40Torr, phosphine can also be introduced simultaneously as n-type doping gas, form the SiGe of phosphorus doping.
In another example, the method for deposition can also be used to form second floating boom 3022, and to the second floating boom
3022 are planarized, and are stopped on the top surface of the fleet plough groove isolation structure 304, and the method for deposition includes but is not limited to chemistry
Vapour deposition, physical vapour deposition (PVD) etc., for example, the material of the second floating boom 3022 can be polysilicon or the polysilicon of doping,
Low-pressure chemical vapor phase deposition (LPCVD) technique can be selected in the forming method of polysilicon.Form the process conditions bag of the polysilicon
Include：Reacting gas is silane (SiH4), the range of flow of the silane can be 100~300 cc/mins (sccm), such as
150sccm；Temperature range can be 700~750 degrees Celsius in reaction chamber；It can be 250~350 millimetress of mercury to react cavity pressure
(mTorr), such as 300mTorr；May also include buffer gas in the reacting gas, the buffer gas can be helium or nitrogen,
The range of flow of the helium and nitrogen can be 5~20 liters/min (slm), such as 8slm, 10slm or 15slm.
The flat of the surface of the second floating boom 3022 can be realized using flattening method conventional in field of semiconductor manufacture
Change.The non-limiting examples of the flattening method include mechanical planarization method and cmp flattening method.Chemistry
Mechanical polishing/planarization method is more often used.
As shown in Figure 3 G, the fleet plough groove isolation structure 304 between adjacent second floating boom 3022 is removed
Part, so as to form T-shaped floating boom 302, the T-shaped floating boom 302 includes first floating boom 3021 and second floating boom 3022.
The part of the fleet plough groove isolation structure 304 between adjacent second floating boom 3022 is removed, namely is returned
Etching removes the part that width reduces in the fleet plough groove isolation structure, so as to form T-shaped floating boom 302.
In a specific embodiment of the invention, the photoresist layer of patterning is formed in Semiconductor substrate 300, using photoetching
The photoresist layer of patterning is formed after the steps such as the exposed development of technique.Photoresist layer exposes fleet plough groove isolation structure 304.
Using the photoresist layer of patterning as mask, etch-back removes what width in the fleet plough groove isolation structure 304 reduced
Part, using a dry ecthing manufacturing process, such as with sulfur fluoride (SF6), nitrogen and chlorine there is height as etchant and to silica
Selective reaction ion(ic) etching (RIE) manufacturing process of selectivity, carry out etch-back manufacturing process.Conventional dry etch technique,
Such as reactive ion etching, ion beam milling, plasma etching, any combination of laser ablation or these methods.It can make
With single engraving method, or more than one engraving method can also be used.
The method of wet etching can also be used to remove the part that width reduces in the fleet plough groove isolation structure 304, it is wet
Method etching has high etch-rate to the isolation oxide in groove isolation construction 304, and has for the second floating boom 3022
Low etch-rate.
For example, wet etching can use hydrofluoric acid solution, such as buffer oxide etch agent (buffer oxide
Etchant (BOE)) or hydrofluoric acid cushioning liquid (buffer solution of hydrofluoric acid (BHF)).
Alternatively, the width range at the top of T-shaped floating boom 302 is 20~110nm, the width of the bottom of T-shaped floating boom 302
Degree scope is 10~80nm.
In one example, the T-shaped floating boom 302 is by first floating boom 3021 and described two parts of second floating boom 3022
Composition, the width range at the top of T-shaped floating boom 302 is defined by the width of the second floating boom 3022, and the T-shaped floating boom
The width range of 302 bottoms is defined by the width (width for being also substantially equal to active area) of the first floating boom 3021.
Wherein, the width of the second floating boom 3022 is more than the width of first floating boom 3021, for example, the second floating boom 3022
The width of the first floating boom of width wall 3021 is wide 10~30 nanometers, and the number range is only as an example, can also be according to the device of reality
Demand is suitably adjusted, wherein, the width of the second floating boom 3022 by it is foregoing etch-back is carried out to fleet plough groove isolation structure 304 when
Etch quantity controlled.
By forming the floating boom of T-shaped structure in the present invention, increase the width (namely critical size CD) at the top of floating boom, to increase
Add coupling ratio, while increase the distance between the floating boom and the active area, there is more preferable breakdown voltage property, improve
The reliability of device.
Then, as shown in figure 3h, the shape on the surface that the T-shaped floating boom 302 and the fleet plough groove isolation structure 304 expose
Into dielectric layer 305 between grid；Control gate (not shown) is formed on dielectric layer 305 between the grid.
The T-shaped floating boom 302 and the fleet plough groove isolation structure 304 expose successively in the Semiconductor substrate 300
Dielectric layer 305 between grid is formed on surface, ONO (oxide/nitride/oxide, oxide- can be selected in dielectric layer 305 between grid
Nitride-oxide) dielectric layer.Specifically, dielectric layer 305 can be three layers altogether of oxidenitride oxide between grid
ONO sandwich structures, those skilled in the art it should be appreciated that between grid dielectric layer 305 can also be one layer of nitride or
The insulation systems such as one layer of oxide are formed on one layer of oxide of person or one layer of nitride.It can use and include but is not limited to：It is low
The method of pressure chemical vapor deposition method, chemical gaseous phase depositing process and physical gas-phase deposite method forms dielectric layer 305 between grid.
It should be noted that the method for dielectric layer 305 is exemplary between above-mentioned formation grid, it is not limited to the side
Method, as long as this area other method can realize the purpose, the present invention is can apply to, will not be repeated here.
Control gate is formed on dielectric layer 305 between the grid, polysilicon can be selected in the material of control gate.
Low-pressure chemical vapor phase deposition (LPCVD) technique can be selected in the forming method of polysilicon.Form the work of the polysilicon
Skill condition includes：Reacting gas is silane (SiH4), the range of flow of the silane can be 100~300 cc/mins
(sccm), such as 150sccm；Temperature range can be 700~750 degrees Celsius in reaction chamber；It can be 250~350 to react cavity pressure
Milli millimetres of mercury (mTorr), such as 300mTorr；Buffer gas is may also include in the reacting gas, the buffer gas can be
Helium or nitrogen, the range of flow of the helium and nitrogen can be 5~20 liters/min (slm), such as 8slm, 10slm or 15slm.
It should be noted that the method for above-mentioned formation control gate is exemplary, it is not limited to methods described, ability
As long as domain other method can realize the purpose, the present invention is can apply to, will not be repeated here.
The manufacture method of the semiconductor devices of the present invention goes for the making of any flush memory device, such as 28nm sections
Following making of flush memory device of point etc..
In summary, manufacturing method according to the invention, on the premise of flush memory device area drastically reduces, maintain compared with
Small active area dimensions, and remain able to meet device for coupling ratio high request, and the data for further increasing device are protected
(Data retention) reliability is held, and then improves the overall performance of semiconductor devices.
Embodiment two
It is proposed according to the present invention to the semiconductor devices that a kind of method using in previous embodiment one is formed, this partly leads
Body device is the flush memory device below flush memory device, such as 28nm nodes.
Specifically, as shown in figure 3h, semiconductor devices of the invention includes：Semiconductor substrate 300.
Wherein, the Semiconductor substrate 300 can be at least one of following material being previously mentioned：On silicon, insulator
Silicon (SSOI) is laminated on silicon (SOI), insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator
And germanium on insulator (GeOI) etc. (SiGeOI).As an example, in the present embodiment, the constituent material of Semiconductor substrate is selected
Monocrystalline silicon.
Exemplarily, the Semiconductor substrate 300 includes three regions, is respectively：For forming logic circuit grid knot
The first area of structure, i.e. logic region；To form the second area of high voltage transistor grid structure, i.e. high voltage circuit area
Domain；To form the 3rd region of the grid structure of selection transistor and memory cell grid structure, i.e. flash cell region.
It should be noted that logic region and high-tension circuit region are all to be located at peripheral circuit region in true layout.
Further, some fleet plough groove isolation structures 304 are provided with the Semiconductor substrate 300, to isolate active area
(AA), wherein, the top surface of the fleet plough groove isolation structure 304 is higher than the top surface of the Semiconductor substrate 300.
Formed with T-shaped floating boom 302 in Semiconductor substrate 300 in the active area, the top of T-shaped floating boom 302
Width is more than the width of the bottom of T-shaped floating boom 302.
Further, the T-shaped floating boom 302 includes the first floating boom 3021 and the second floating boom 3022, wherein, described first is floating
The top surface of grid 3021 is higher than the top surface of the fleet plough groove isolation structure 304, and second floating boom 3022 is located at first floating boom
On 3021 surface, and its top surface is higher than the top surface of the fleet plough groove isolation structure 304, and further extends into the shallow trench
On the part surface of isolation structure 304.
In one example, the T-shaped floating boom 302 is by first floating boom 3021 and described two parts of second floating boom 3022
Composition, the width range at the top of T-shaped floating boom 302 is defined by the width of the second floating boom 3022, and the T-shaped floating boom
The width range of 302 bottoms is defined by the width (width for being also substantially equal to active area) of the first floating boom 3021.
Alternatively, the width range at the top of T-shaped floating boom 302 is 20~110nm, the width of the bottom of T-shaped floating boom 302
Degree scope is 10~80nm.
Wherein, the width of the second floating boom 3022 is more than the width of first floating boom 3021, for example, the second floating boom 3022
The width of the first floating boom of width wall 3021 is wide 10~30 nanometers, and the number range is only as an example, can also be according to the device of reality
Demand is suitably adjusted, wherein, the width of the second floating boom 3022 by it is foregoing etch-back is carried out to fleet plough groove isolation structure 304 when
Etch quantity controlled.
Alternatively, first floating boom 3021 and second floating boom 3022 can be different semi-conducting materials, for example,
The material of first floating boom 3021 includes polysilicon or the polysilicon of doping, and the polysilicon of doping can be the polysilicon of phosphorus doping,
The material of second floating boom 3022 can include the SiGe or SiGe of doping, such as the SiGe of phosphorus doping, the second floating boom 3022
Can also be the Si of epitaxial growth.
Wherein, the material of second floating boom 3022 can also be polysilicon or the polysilicon of doping, such as phosphorus doping
Polysilicon.
Alternatively, the thickness range of second floating boom is 100~800 angstroms, and the numerical value is only as an example, can also be it
The numerical value that he is adapted to.
Second floating boom 3022 can also be formed using different forming methods, it is, for example, possible to use selective epitaxial
The method of growth or the deposition process of routine.
In one example, the method for selective epitaxial growth can be used to form second floating boom 3022 can use
Low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD
(UHVCVD), one kind in rapid thermal CVD (RTCVD) and molecular beam epitaxy (MBE).
For example, the material of second floating boom 3022 can include the SiGe or SiGe of doping, chemical vapor deposition can be used
Product method or gas source molecular beam epitaxy method growth SiGe, by the use of silane or disilane as silicon source, while are added certain
The germane of amount.For example, from GeH4And SiH2Cl2As reacting gas, and select H2As carrier gas, wherein reacting gas and load
The flow-rate ratio of gas is 0.01-0.1, and the temperature of deposition is 300-1000 DEG C, preferably 650-750 DEG C, gas pressure 1-
50Torr, preferably 20-40Torr, phosphine can also be introduced simultaneously as n-type doping gas, form the SiGe of phosphorus doping.
In another example, the method for deposition can also be used to form second floating boom 3022, and to the second floating boom
3022 are planarized, and are stopped on the top surface of the fleet plough groove isolation structure 304, and the method for deposition includes but is not limited to chemistry
Vapour deposition, physical vapour deposition (PVD) etc., for example, the material of the second floating boom 3022 can be polysilicon or the polysilicon of doping,
Low-pressure chemical vapor phase deposition (LPCVD) technique can be selected in the forming method of polysilicon.Form the process conditions bag of the polysilicon
Include：Reacting gas is silane (SiH4), the range of flow of the silane can be 100~300 cc/mins (sccm), such as
150sccm；Temperature range can be 700~750 degrees Celsius in reaction chamber；It can be 250~350 millimetress of mercury to react cavity pressure
(mTorr), such as 300mTorr；May also include buffer gas in the reacting gas, the buffer gas can be helium or nitrogen,
The range of flow of the helium and nitrogen can be 5~20 liters/min (slm), such as 8slm, 10slm or 15slm.
In one example, between the T-shaped floating boom 302 and the surface of the Semiconductor substrate 300 formed with tunnelling oxygen
Change layer 301, tunnel oxide 301 can include following any conventional dielectric：SiO2、SiON、SiON2And including calcium titanium
Other similar oxides of ore deposit type oxide.Wherein, silica can be selected in the material of tunnel oxide 301, and generation type uses
Thermal oxidation method.The thickness of the tunnel oxide of formation is right in tens Izods, in one example, the thickness of the tunnel oxide
For 80 angstroms to 110 angstroms.
Further, semiconductor devices of the invention also includes：Be arranged on the T-shaped floating boom 302 and the shallow trench every
From dielectric layer 305 between the grid on the surface of structure 304, and it is arranged on the control gate (not shown) between the grid on dielectric layer 305.
ONO (oxide/nitride/oxide, oxide-nitride-oxide) dielectric can be selected in dielectric layer 305 between grid
Layer.Specifically, dielectric layer 305 can be oxidenitride oxide three layers of ONO sandwich structures altogether between grid, this area
Technical staff it should be appreciated that dielectric layer 305 can also be one layer of nitride or one layer of oxide or one between grid
The insulation systems such as one layer of oxide are formed on layer nitride.
The material of control gate can be polysilicon, or any other applicable material well known to those skilled in the art.
The semiconductor devices of the present invention includes the floating boom of T-shaped structure, adds width (namely the critical size at the top of floating boom
CD), to increase coupling ratio, while increase the distance between the floating boom and the active area, there is more preferable breakdown voltage
Energy.Therefore, on the premise of flush memory device area drastically reduces, semiconductor devices of the invention maintains less active area chi
It is very little, and remain able to meet device for coupling ratio high request, and keep (Data retention) can with good data
By property, therefore the overall performance of semiconductor devices is higher.
Embodiment three
Present invention also offers a kind of electronic installation, including the semiconductor devices described in embodiment two, the semiconductor
Device method according to embodiment one is prepared.
The electronic installation of the present embodiment, can be mobile phone, tablet personal computer, notebook computer, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, DPF, camera, video camera, recording pen, MP3, MP4, PSP is set
It is standby, or any intermediate products including circuit.The electronic installation of the embodiment of the present invention, due to having used above-mentioned semiconductor
Device, thus there is better performance.
Wherein, Fig. 4 shows the example of mobile phone handsets.Mobile phone handsets 400, which are equipped with, to be included in shell 401
Display portion 402, operation button 403, external connection port 404, loudspeaker 405, microphone 406 etc..
Wherein described mobile phone handsets include the semiconductor devices described in embodiment two, and the semiconductor devices mainly wraps
Include：
Semiconductor substrate, some fleet plough groove isolation structures are provided with the Semiconductor substrate, to isolate active area, its
In, the top surface of the fleet plough groove isolation structure is higher than the top surface of the Semiconductor substrate；
Formed with T-shaped floating boom in Semiconductor substrate in the active area.
The electronic installation of the present invention includes foregoing semiconductor devices, therefore also has the advantages of identical.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (14)
1. a kind of manufacture method of semiconductor devices, it is characterised in that methods described includes：
Semiconductor substrate is provided, the first floating gate material layer is formed on the surface of the Semiconductor substrate；
Some fleet plough groove isolation structures are formed in the Semiconductor substrate, and form what is isolated by the fleet plough groove isolation structure
First floating boom, wherein, the top surface of the fleet plough groove isolation structure is higher than the top surface of first floating boom；
Etch-back is carried out to the fleet plough groove isolation structure exposed, to reduce the width of the fleet plough groove isolation structure exposed
Degree；
The second floating boom is formed, to cover first floating boom and fill the gap between the fleet plough groove isolation structure, and it is described
The top surface of second floating boom flushes with the top surface of the fleet plough groove isolation structure；
The part of the fleet plough groove isolation structure between adjacent second floating boom is removed, so as to form T-shaped floating boom, institute
Stating T-shaped floating boom includes first floating boom and second floating boom.
2. manufacture method as claimed in claim 1, it is characterised in that before the first floating gate material layer is formed, also wrap
Include the step of forming tunnel oxide on the surface of the Semiconductor substrate.
3. manufacture method as claimed in claim 1, it is characterised in that formed in the Semiconductor substrate some shallow trench every
The step of from structure, includes procedure below：
Hard mask layer is formed on the surface of the first floating gate material layer, the hard mask layer includes the nitride stacked gradually
Layer and oxide skin(coating)；
The photoresist layer of patterning is formed on the hard mask layer；
Using the photoresist layer as mask, the hard mask layer, the first floating gate material layer and part described half are etched successively
Conductor substrate, to form some shallow trench and first floating boom in the Semiconductor substrate；
Remove the photoresist layer；
Isolation oxide is filled in the shallow trench, and the isolation oxide is planarized, stops at the nitridation
On the top surface of nitride layer, to form the fleet plough groove isolation structure；
The nitride layer is removed, so that the part fleet plough groove isolation structure protrudes from first floating boom.
4. manufacture method as claimed in claim 3, it is characterised in that the isolation oxide is filled in the shallow trench
Before step, in addition on the bottom of the shallow trench and side wall formed laying the step of.
5. manufacture method as claimed in claim 1, it is characterised in that width range at the top of the T-shaped floating boom for 20~
110nm, the width range of the T-shaped floating boom bottom is 10~80nm.
6. manufacture method as claimed in claim 1, it is characterised in that the thickness range of first floating boom is 100~700
Angstrom, the thickness range of second floating boom is 100~800 angstroms.
7. manufacture method as claimed in claim 1, it is characterised in that use the side of selective epitaxial growth method or deposition
Method forms second floating boom.
8. manufacture method as claimed in claim 1, it is characterised in that the material of first floating boom includes polysilicon, described
The material of second floating boom includes Si or SiGe.
9. manufacture method as claimed in claim 1, it is characterised in that the material of second floating boom is the SiGe of phosphorus doping.
10. manufacture method as claimed in claim 1, it is characterised in that the material of first floating boom includes polysilicon, described
The material of second floating boom includes the polysilicon of polysilicon or phosphorus doping.
11. manufacture method as claimed in claim 1, it is characterised in that after the T-shaped floating boom is formed, in addition to it is following
Step：
The dielectric layer between formation grid on the surface that the T-shaped floating boom and the fleet plough groove isolation structure expose；
Between the grid control gate is formed on dielectric layer.
12. manufacture method as claimed in claim 1, it is characterised in that the width of second floating boom is than first floating boom
Width it is wide 10~30 nanometers.
A kind of 13. semiconductor devices that method using as described in any one of claim 1 to 12 prepares.
14. a kind of electronic installation, it is characterised in that including semiconductor devices as claimed in claim 13.
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| CN105575968A (en) * | 2014-10-17 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Embedded flash memory, preparation method thereof, and electronic device |
| CN105845631A (en) * | 2015-01-14 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Embedded flash memory, manufacturing method therefor, and electronic device |
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| KR20080061476A (en) * | 2006-12-28 | 2008-07-03 | 주식회사 하이닉스반도체 | Method of manufacturing a non volatile memory device |
| CN105575968A (en) * | 2014-10-17 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Embedded flash memory, preparation method thereof, and electronic device |
| CN105845631A (en) * | 2015-01-14 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Embedded flash memory, manufacturing method therefor, and electronic device |
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