CN107305891A - A kind of semiconductor devices and preparation method thereof, electronic installation - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic installation Download PDFInfo
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- CN107305891A CN107305891A CN201610240678.6A CN201610240678A CN107305891A CN 107305891 A CN107305891 A CN 107305891A CN 201610240678 A CN201610240678 A CN 201610240678A CN 107305891 A CN107305891 A CN 107305891A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, electronic installation.This method includes：Semiconductor substrate is provided, gate material layers and hard mask layer are formed with the semiconductor substrate, groove is formed with the Semiconductor substrate, gate material layers and hard mask layer, cushion oxide layer is formed with the side wall of the groove, in the trench filled with separation layer；Remove the hard mask layer；Additional oxide layer is formed on the semiconductor substrate, and the additional oxide layer includes being located at the part on the gate material layers and the part on the trenched side-wall；Remove part of the additional oxide layer on the gate material layers.This method can avoid subsequent control grid etching from producing polycrystalline silicon residue and cause control gate and floating boom short circuit.The semiconductor devices and electronic installation have more preferable yields.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its
Preparation method, electronic installation.
Background technology
With the development of manufacture of semiconductor technology, access speed has been developed in terms of storage device
Faster flash memory (flash memory).Flash memory, which has, can repeatedly enter row information
Deposit, read and the action such as erasing, and the spy that will not also disappear after a loss of power of information of deposit
Property, therefore, flash memory turns into PC and the widely used one kind of electronic equipment
Nonvolatile memory.And NAND (NAND gate) flash memories with big storage due to holding
Amount and relatively high performance, are widely used in the field that read/write requires higher.Recently, NAND
The capacity of flash memory chip has reached 2GB, and size increases sharply.Develop
Go out the solid state hard disc based on NAND quick-flash memory chip, and be used as in pocket computer
Storage device.Therefore, in recent years, NAND quick-flash memory is widely used as in embedded system
Storage device, also serve as the storage device in personal computer system.
For the NAND memory cell (NAND cell) of 3Xnm (for example, 32nm) below,
Outer peripheral areas active area side wall STI (fleet plough groove isolation structure) performance is for ensuing work
Skill is extremely important, and the opening process of current NAND memory cell finds that side wall lacks
Angle (devoit), this unfilled corner can cause control gate etching to there is polycrystalline silicon residue, and then cause
Floating boom and control gate short circuit.
Therefore, it is necessary to a kind of new preparation method be proposed, to solve the above problems.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be specific real
Apply in mode part and be further described.The Summary of the present invention is not meant to
Attempt to limit the key feature and essential features of technical scheme claimed, less
Mean the protection domain for attempting to determine technical scheme claimed.
In order to overcome the problem of presently, there are, one aspect of the present invention provides a kind of semiconductor devices
Preparation method, this method includes：Semiconductor substrate is provided, formed on the semiconductor substrate
There are gate material layers and hard mask layer, in the Semiconductor substrate, gate material layers and hard mask
Groove is formed with layer, cushion oxide layer is formed with the side wall of the groove, in the ditch
Separation layer is filled with groove；Remove the hard mask layer；Formed on the semiconductor substrate attached
Plus oxide layer, the additional oxide layer is including being located at part and position on the gate material layers
Part on the trenched side-wall；The additional oxide layer is removed positioned at the gate material layers
On part.
Exemplarily, the hard mask layer is removed by wet etching.
Exemplarily, the additional oxide layer passes through chemical vapour deposition technique or thermal oxidation method shape
Into.
Exemplarily, the additional oxide layer is removed by dry etching or wet etching and is located at institute
State the part on gate material layers.
Exemplarily, the semiconductor devices is NAND memory cell.
Exemplarily, the gate material layers are floating gate material layer.
The present invention semiconductor devices preparation method, by remove hard mask layer after,
Additional oxide layer is formed on Semiconductor substrate, the additional oxide layer can fill the hard mask of removal
The unfilled corner formed during layer in sti structure, so as to avoid subsequent control grid etching from producing polysilicon
It is remaining and cause control gate and floating boom short circuit.
Another aspect of the present invention, which provides a kind of semiconductor devices of use above method making, to be included：
Semiconductor substrate, the gate material layers in the Semiconductor substrate, positioned at the semiconductor
Groove in substrate, gate material layers, the pad oxygen on the bottom of the groove and side wall
Change layer, the additional oxide layer on trenched side-wall top, and in the groove
And by the cushion oxide layer and the additional oxide layer around the separation layer surrounded.
Exemplarily, the semiconductor devices is NAND memory cell.
Exemplarily, the gate material layers are floating gate material layer.
Semiconductor devices proposed by the present invention, in the side wall of the groove for forming isolation structure
Additional oxide layer is formed with, the unfilled corner of the full groove of additional oxide layer filling, so as to prevent
Follow-up be controlled has polycrystalline silicon residue when grid are etched, and then causes control gate/floating boom short-circuit,
Therefore with more preferable yields.
Further aspect of the present invention provides a kind of electronic installation, and it includes above-mentioned semiconductor device.
Electronic installation proposed by the present invention, due to above-mentioned semiconductor device, thus with class
As advantage.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A and Figure 1B show that the section that a kind of conventional STI preparation methods obtain device shows
It is intended to；
Fig. 2 shows the preparation method of semiconductor devices according to an embodiment of the present invention
Flow chart of steps；
Fig. 3 A~Fig. 3 D show the making of semiconductor devices according to an embodiment of the present invention
Method implements the diagrammatic cross-section that each step obtains semiconductor devices successively；
Fig. 4 shows the structural representation of semiconductor devices according to an embodiment of the present invention.
Fig. 5 is the schematic diagram of the electronic installation according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that of the invention
It can be carried out without one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, be not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, and it will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
For clarity, the size and relative size in Ceng He areas may be exaggerated identical accompanying drawing from beginning to end
Mark represents identical element.
It should be understood that be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer, with
It is adjacent, be connected or coupled to other elements or layer, or there may be element or layer between two parties.
On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then in the absence of element or layer between two parties.Should
Understand, although can be used term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term is limited.These terms be used merely to distinguish element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, do not depart from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., can describe for convenience herein and by using from
And an element shown in figure or feature and other elements or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of and operation
In device different orientation.If for example, the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
For other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this hair
Bright limitation.Herein in use, " one " of singulative, " one " and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " comprising ", when in this specification in use, determine the feature,
Integer, step, operation, the presence of element and/or part, but be not excluded for it is one or more its
Its feature, integer, step, operation, element, the presence or addition of part and/or group.
Herein in use, term "and/or" includes any and all combination of related Listed Items.
Analyzed first with reference to Figure 1A and Figure 1B in current NAND memory cell manufacture craft
The reason for easily there is unfilled corner in outer peripheral areas active area side wall STI.
Figure 1A and Figure 1B show that the section that a kind of conventional STI preparation methods obtain device shows
It is intended to.Wherein, Figure 1A is the outer peripheral areas formation STI (shallow ridges in NAND memory cell
Recess isolating structure) when, device profile signal after having filled isolating oxide layer and having planarized
Figure.
As shown in Figure 1A, pad oxide (pad is formed with a semiconductor substrate 100
Oxide) 101, polysilicon layer 102, hard mask layer 103, the Semiconductor substrate 100,
Groove is formed in pad oxide (pad oxide) 101, polysilicon layer 102 and hard mask layer 103,
And cushion oxide layer (linear oxide) 104 and filling institute are formed on the side wall of the groove
State the separation layer 105 of groove, wherein 103 property of hard mask layer are nitride, such as silicon nitride,
Cushion oxide layer 104 is high-temperature oxide (HTO), and separation layer 105 is the hot oxygen of high-aspect-ratio
Compound (HARP), after planarization Operation has been performed, then performs and removes hard mask layer
It is 103 the step of, general that hard mask layer 103 is removed using phosphoric acid solution wet method, but be due to temperature
The wet-etch rate of oxide is (for example, be 5:1) than the wet method of high-aspect-ratio thermal oxide
Etch rate is (for example, be 2：1) it is much larger, therefore, hard mask layer 103 is removed in wet method
When, a part of cushion oxide layer 104 on trenched side-wall can be also removed, so as to cause external zones
Easily there is unfilled corner in domain active area side wall STI, and then it is residual to cause control gate etching to there is polysilicon
It is remaining, and floating boom and control gate short circuit may finally be made.
In order to solve the above problems, the present invention provides a kind of manufacture method of semiconductor devices, uses
In making NAND quick-flash memory.
As shown in Fig. 2 this method includes：
Step 201：Semiconductor substrate is provided, grid material is formed with the semiconductor substrate
Material and hard mask layer, are formed with the Semiconductor substrate, gate material layers and hard mask layer
Groove, is formed with cushion oxide layer on the side wall of the groove, is filled with the trench
Separation layer；
Step 202：Remove the hard mask layer；
Step S203：Additional oxide layer, the additional oxygen are formed on the semiconductor substrate
Change layer including the part on the gate material layers and on the trenched side-wall
Part；
Step S204：Remove portion of the additional oxide layer on the gate material layers
Point.
The present invention semiconductor devices preparation method, by remove hard mask layer after,
Additional oxide layer is formed on Semiconductor substrate, the additional oxide layer can fill the hard mask of removal
The unfilled corner formed during layer in sti structure, so as to avoid subsequent control grid etching from producing polysilicon
It is remaining and cause control gate and floating boom short circuit.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description
Suddenly, to explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail
It is as follows, but in addition to these detailed descriptions, the present invention can also have other embodiment.
Embodiment one
Below by making sides of Fig. 3 A~Fig. 3 D to the semiconductor devices of an embodiment of the present invention
Method is described in detail.
First as shown in Figure 3A there is provided Semiconductor substrate 300, in the Semiconductor substrate 300
Upper formation pad oxide 301, gate material layers 302 and hard mask layer 303, partly lead described
It is formed with body substrate 300, pad oxide 301, polysilicon layer 302 and hard mask layer 303
Groove, forms cushion oxide layer 304 on the side wall of the groove, fills in the trench
There is separation layer 304.
Wherein, Semiconductor substrate 300 can be at least one of following material being previously mentioned：
Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V chemical combination
Thing semiconductor, in addition to the sandwich construction etc. that constitutes of these semiconductors or be silicon-on-insulator
(SOI), be laminated on insulator silicon (SSOI), stacking SiGe (S-SiGeOI) on insulator,
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..As an example,
In the present embodiment, the constituent material of Semiconductor substrate 300 selects monocrystalline silicon.
STI (fleet plough groove isolation structure) is formed by method commonly used in the art, exemplary property,
The formation of fleet plough groove isolation structure comprises the steps：Formed in the Semiconductor substrate 300
Pad oxide 301, the cushion oxide layer 301 is illustratively silicon dioxide layer, and it passes through
Thermal oxidation method is formed, and thickness isIt is used as the stress-buffer layer of subsequent nitridation silicon layer；
Because the manufacturing method of semiconductor device of the present embodiment is used to make the external zones of NAND device
Domain, therefore, forms on the cushion oxide layer 301 and is also formed with gate material layers 302,
It is by conventional CVD (chemical vapour deposition technique) formation, thickness
Then hard mask layer 303 is formed in gate material layers 302, exemplary hard mask layer 303 is
Silicon nitride layer, it is formed by CVD method, and thickness isIn follow-up STI
Protect active area in isolated material filling, and can as subsequent CMP barrier layer；Etching institute
The formation of hard mask layer 303 pattern corresponding with sti structure is stated, is then with hard mask layer 303
Mask etching gate material layers 302, pad oxide (pad oxide) 301 and Semiconductor substrate
300 form groove；Cushion oxide layer 304 is formed on the side wall of the groove and bottom, is shown
Cushion oxide layer 304 is formed to example property by high temperature oxide layer, when being filled as follow-up separation layer
Generation layer；Separation layer 305 is filled in the trench, such as then the oxide of silicon is held
Row planarization, removes the part that the separation layer 305 is located on hard mask layer 303, with shape
Into fleet plough groove isolation structure.
Then, as shown in Figure 3 B, the hard mask layer 303 is removed.
It is exemplary, in the present embodiment, hard mask layer 303 is removed by wet-etching technology,
Hard mask layer 303 is such as removed by the phosphoric acid solution of suitable concn, as previously described, because lining
The wet-etch rate of pad oxide 304 is very fast, thus after hard mask layer 303 are removed,
Portions of pads oxide layer 304 under hard mask layer 303 is also removed, in sti structure
Form unfilled corner.
Then, as shown in Figure 3 C, additional oxide layer 306 is formed on the semiconductor substrate,
The additional oxide layer 306 includes the part being located on the gate material layers 302 and is located at
Part on the trenched side-wall.
Exemplarily, in the present embodiment, CVD techniques, heating TEOS are heated by silane
The technique such as CVDP techniques, PECVD, PE-TEOS or regular oxidation technique are in the grid
Additional oxide layer 306 is formed on material layer 302, the additional oxide layer 306 can be filled
Unfilled corner present in sti structure, and in order to be sufficient filling with the unfilled corner, additional oxide layer 306
Also cover the surface of gate material layers 302.
Finally, as shown in Figure 3 D, remove additional oxide layer 306 and be located at gate material layers 302
On part.
It is exemplary, in the present embodiment, removed by dry etch process or wet-etching technology
Additional oxide layer 306 is located at the part on gate material layers 302, due to additional oxide layer
306 etching quantity is consistent, thus unfilled corner will not be formed in sti structure, and is formed before
Unfilled corner also because being disappeared filled with additional oxide layer.
Wherein, wet etching process is described dry exemplarily using the hydrofluoric acid (HF) of dilution
Method etch process includes but is not limited to：Reactive ion etching (RIE), ion beam milling, etc. from
Daughter is etched or is cut by laser.The source gas of the dry etching can include CF4, CHF3
Or other fluorocarbon gas.It is exemplary, in this embodiment, gone using dry etch process
Except additional oxide layer 306 be located at gate material layers 302 on part, and as an example,
Described to be etched to dry etching in the present embodiment, the technological parameter of the dry etching includes：
Etching gas includes the gas such as CF4, CHF3, its flow be respectively 50sccm~500sccm,
10sccm~100sccm, pressure is 2mTorr~50mTorr, wherein, sccm representatives cube li
M/min, mTorr represents milli millimetres of mercury.
So far, the processing step that method according to embodiments of the present invention is implemented, Ke Yili are completed
Solution, the present embodiment manufacturing method of semiconductor device not only includes above-mentioned steps, in above-mentioned step
Before rapid, among or may also include other desired step, such as the control gate of external zones afterwards
The etching of/floating boom, the making of NAND device memory block (cell), it is included in this implementation
In the range of preparation method.
, not only can be with it is understood that the manufacture method of semiconductor devices proposed by the present invention
For the fast storage component parts of NAND, and it can be used for making other and easily go out in STI
The device of existing side wall unfilled corner.
The method, semi-conductor device manufacturing method of the present embodiment is by after hard mask layer is removed, half
Conductor substrate formation additional oxide layer, the additional oxide layer can fill removal hard mask layer
When the unfilled corner that is formed in sti structure so that it is residual to avoid subsequent control grid etching from producing polysilicon
It is remaining and cause control gate and floating boom short circuit.
Embodiment two
The present invention also provides a kind of semiconductor devices.
As shown in figure 4, the semiconductor devices includes：Semiconductor substrate 400, partly leads described
Pad oxide 401 and gate material layers 402 on body substrate 400, in the Semiconductor substrate
400th, the groove formed in pad oxide 401 and gate material layers 402, in the groove
The cushion oxide layer 403 and additional oxide layer 404 formed on the wall of side, is filled in the trench
There is separation layer 405.
Wherein Semiconductor substrate 400 can be at least one of following material being previously mentioned：Si、
Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compounds half
Conductor, in addition to the sandwich construction etc. that constitutes of these semiconductors or for silicon-on-insulator (SOI),
Silicon (SSOI), stacking SiGe (S-SiGeOI), insulator on insulator are laminated on insulator
Upper SiGe (SiGeOI) and germanium on insulator (GeOI) etc..Can in Semiconductor substrate
To be formed with device, such as NMOS and/or PMOS.Equally, in Semiconductor substrate also
Conductive member is could be formed with, conductive member can be the grid, source electrode or drain electrode of transistor,
It can also be metal interconnection structure for being electrically connected with transistor, etc..In the present embodiment, half
The constituent material of conductor substrate 400 selects monocrystalline silicon.
The semiconductor devices of the present embodiment, due to the side wall in the groove for forming isolation structure
On be formed with additional oxide layer, the unfilled corner of the full groove of additional oxide layer filling, so that anti-
There is polycrystalline silicon residue when being only subsequently controlled grid etching, and then cause control gate/floating boom short circuit.
Embodiment three
Yet another embodiment of the present invention provides a kind of electronic installation, including above-described embodiment two
Described semiconductor devices and the electronic building brick being connected with the semiconductor devices.
Wherein, the electronic building brick, can be any electronic building bricks such as discrete device, integrated circuit.
The electronic installation of the present embodiment, can be mobile phone, tablet personal computer, notebook computer, on
Net sheet, game machine, television set, VCD, DVD, navigator, camera, video camera,
Any electronic product such as recording pen, MP3, MP4, PSP or equipment, or it is any including
The intermediate products of the semiconductor devices.
Wherein, Fig. 5 shows the example of mobile phone.The outside of mobile phone 500 is provided with including outside
Display portion 502, operation button 503, external connection port 504 in shell 501, raise one's voice
Device 505, microphone 506 etc..
The electronic installation of the embodiment of the present invention, by the ditch for being used to form isolation structure included
Additional oxide layer is formed with the side wall of groove, the additional oxide layer fills lacking for the full groove
Angle, so as to prevent there is polycrystalline silicon residue when being subsequently controlled grid etching, and then causes control gate
/ floating boom short circuit, therefore the electronic installation equally have the advantages that it is similar.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
The purpose that embodiment is only intended to illustrate and illustrated, and be not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that not office of the invention
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repaiied
Change, these variants and modifications are all fallen within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (10)
1. a kind of preparation method of semiconductor devices, it is characterised in that comprise the steps：
Semiconductor substrate is provided, gate material layers are formed with the semiconductor substrate and are covered firmly
Film layer, groove is formed with the Semiconductor substrate, gate material layers and hard mask layer,
Cushion oxide layer is formed with the side wall of the groove, in the trench filled with separation layer；
Remove the hard mask layer；
Additional oxide layer is formed on the semiconductor substrate, and the additional oxide layer includes being located at
Part on the gate material layers and the part on the trenched side-wall；
Remove part of the additional oxide layer on the gate material layers.
2. the preparation method of semiconductor devices according to claim 1, it is characterised in that
The hard mask layer is removed by wet etching.
3. the preparation method of semiconductor devices according to claim 1, it is characterised in that
The additional oxide layer is formed by chemical vapour deposition technique or thermal oxidation method.
4. the preparation method of semiconductor devices according to claim 1, it is characterised in that
The additional oxide layer is removed by dry etching or wet etching and is located at the gate material layers
On part.
5. the preparation method of the semiconductor devices according to one of claim 1-4, it is special
Levy and be, the semiconductor devices is NAND memory cell.
6. the preparation method of semiconductor devices according to claim 5, it is characterised in that
The gate material layers are floating gate material layer.
7. the semiconductor devices that a kind of method using as described in one of claim 1-5 makes,
It is characterised in that it includes：Semiconductor substrate, the grid material in the Semiconductor substrate
Layer, the groove in the Semiconductor substrate, gate material layers, positioned at the bottom of the groove
Cushion oxide layer in portion and side wall, the additional oxide layer on trenched side-wall top,
And around bag in the groove and by the cushion oxide layer and the additional oxide layer
The separation layer enclosed.
8. semiconductor devices according to claim 7, it is characterised in that described partly to lead
Body device is NAND memory cell.
9. semiconductor devices according to claim 8, it is characterised in that the grid
Material layer is floating gate material layer.
10. a kind of electronic installation, it is characterised in that including described in one of claim 7-9
Semiconductor devices and the electronic building brick being connected with the semiconductor devices.
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| CN201610240678.6A CN107305891B (en) | 2016-04-18 | 2016-04-18 | Semiconductor device, manufacturing method thereof and electronic device |
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| CN201610240678.6A CN107305891B (en) | 2016-04-18 | 2016-04-18 | Semiconductor device, manufacturing method thereof and electronic device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019200582A1 (en) * | 2018-04-19 | 2019-10-24 | Yangtze Memory Technologies Co., Ltd. | Memory device and forming method thereof |
| CN112908858A (en) * | 2021-03-09 | 2021-06-04 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010015046A1 (en) * | 1999-06-03 | 2001-08-23 | Hong Sug-Hun | Trench isolation method |
| US20030054608A1 (en) * | 2001-09-17 | 2003-03-20 | Vanguard International Semiconductor Corporation | Method for forming shallow trench isolation in semiconductor device |
| CN101000910A (en) * | 2006-01-13 | 2007-07-18 | 三星电子株式会社 | Trench isolation type semiconductor device and related method of manufacture |
-
2016
- 2016-04-18 CN CN201610240678.6A patent/CN107305891B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010015046A1 (en) * | 1999-06-03 | 2001-08-23 | Hong Sug-Hun | Trench isolation method |
| US20030054608A1 (en) * | 2001-09-17 | 2003-03-20 | Vanguard International Semiconductor Corporation | Method for forming shallow trench isolation in semiconductor device |
| CN101000910A (en) * | 2006-01-13 | 2007-07-18 | 三星电子株式会社 | Trench isolation type semiconductor device and related method of manufacture |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019200582A1 (en) * | 2018-04-19 | 2019-10-24 | Yangtze Memory Technologies Co., Ltd. | Memory device and forming method thereof |
| US10910390B2 (en) | 2018-04-19 | 2021-02-02 | Yangtze Memory Technologies Co., Ltd. | Memory device and forming method thereof |
| US11211393B2 (en) | 2018-04-19 | 2021-12-28 | Yangtze Memory Technologies Co., Ltd. | Memory device and forming method thereof |
| US11271004B2 (en) | 2018-04-19 | 2022-03-08 | Yangtze Memory Technologies Co., Ltd. | Memory device and forming method thereof |
| US11380701B2 (en) | 2018-04-19 | 2022-07-05 | Yangtze Memory Technologies Co., Ltd. | Memory device and forming method thereof |
| CN112908858A (en) * | 2021-03-09 | 2021-06-04 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107305891B (en) | 2020-02-11 |
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