CN107863059B

CN107863059B - Display panel and display device

Info

Publication number: CN107863059B
Application number: CN201711214226.1A
Authority: CN
Inventors: 郑志伟; 杨康鹏; 许育民
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2017-11-28
Filing date: 2017-11-28
Publication date: 2021-02-02
Anticipated expiration: 2037-11-28
Also published as: CN107863059A

Abstract

The invention discloses a display panel and a display device, which belong to the technical field of display and comprise: a display area and a non-display area; the pixel arrangement is a zig-zag structure; the display panel further comprises a plurality of switches; when the x-th pixel row is refreshed, the first data signal port transmits an electric signal to the first data line through the exchanger, and the second data signal port transmits an electric signal to the second data line through the exchanger; when refreshing the x +1 th row of pixels, when Δ V₁≥V_yAnd Δ V₂When the data signal is more than or equal to 0, the first data signal port transmits an electric signal to the second data line through the exchanger, and the second data signal port transmits an electric signal to the first data line through the exchanger; when Δ V₁＜V_yOr Δ V₂When the number is less than 0, the first data signal port transmits an electric signal to the first data line through the exchanger, and the second data signal port transmits an electric signal to the second data line through the exchanger; wherein, V_yIs a preset voltage, and x and j are positive integers. Compared with the prior art, the power consumption of the signal processing unit can be reduced.

Description

Display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

Referring to fig. 1, fig. 1 is a schematic view of a partial structure of a display panel provided in the prior art. The display panel shown in fig. 1 includes a plurality of pixels 01. A plurality of pixels 01 located in the same column in the column direction constitute one pixel column, and in fig. 1, 6 pixel columns are illustrated, which are a first pixel column 011, a second pixel column 012, a third pixel column 013, a fourth pixel column 014, a fifth pixel column 015, and a sixth pixel column 016, respectively. The display panel further includes a signal processing unit 03 for supplying a data signal to the data lines 02, and a plurality of data lines 02. In fig. 1, 5 data lines are illustrated, namely a first data line 021, a second data line 022, a third data line 023, a fourth data line 024 and a fifth data line 025.

In the display panel shown in fig. 1, the pixels are arranged in a zigzag structure, and specifically, a part of the pixels 01 in two adjacent pixel columns are electrically connected to the same data line 02. For example, odd pixels 01 in the first pixel column 011 are electrically connected to the first data line 021, even pixels 01 in the second pixel column 012 are electrically connected to the first data line 021, and odd pixels 01 in the second pixel column 012 are electrically connected to the second data line 022.

During the working process of the display panel, some heavy-load pictures need to be displayed. For example, as shown in fig. 1, in one frame, the pixels 01 in the first, third, and

fifth pixel columns

011, 013, and 015 receive a voltage of 5V through the data lines, and the pixels 01 in the second, fourth, and

sixth pixel columns

012, 014, and 016 receive a voltage of 0V through the data lines. When the pixels 01 in the first row are refreshed, the first data line 021, the third data line 023 and the fifth data line 025 transmit data signals with the voltage of 5V to the pixels 01 electrically connected with the first data line 021, the third data line 023 and the fifth data line 025; when the second row of pixels 01 is refreshed, the first, third, and fifth data lines 021, 023, and 025 transmit data signals having a voltage of 0V to the pixels 01 electrically connected thereto. In the refresh process of the display frame of one frame, the first data line 021, the third data line 023 and the fifth data line 025 need to alternately transmit a 5V data signal and a 0V data signal, and the voltage variation of the data signals of the first data line 021, the third data line 023 and the fifth data line 025 is large. Similarly, in the refresh process of the display screen of one frame, the second data line 022 and the fourth data line 024 need to alternately transmit a data signal of 0V and a data signal of 5V, and the voltage variation of the data signals of the second data line 022 and the fourth data line 024 is large.

Since a data signal having a large voltage variation needs to be transmitted to each data line 02, a load of the signal processing unit 03 is excessively large, and power consumption of the signal processing unit 03 is large, thereby increasing power consumption of the display panel.

Disclosure of Invention

In view of the foregoing, the present invention provides a display panel and a display device.

The present invention provides a display panel, comprising: a display area and a non-display area surrounding the display area; the display area includes a plurality of pixels; the plurality of pixels includes a plurality of pixel rows and a plurality of pixel columns; each pixel row comprises j pixels; the display area comprises a plurality of data lines; the data line is arranged between two adjacent pixel columns;the data line comprises a first side and a second side which are opposite; the data line is electrically connected with the pixels in the odd rows in the pixel columns on the first side, and the data line is electrically connected with the pixels in the even rows in the pixel columns on the second side; the non-display area comprises a plurality of data signal ports, the data signal ports are electrically connected with the signal processing unit, and the data signal ports transmit electric signals to the data lines; the plurality of data lines comprise a plurality of data line groups, and each data line group comprises two adjacent data lines; two adjacent data lines are respectively a first data line and a second data line; the plurality of data signal ports comprises a plurality of port groups, and each port group comprises two adjacent data signal ports; two adjacent data signal ports are respectively a first data signal port and a second data signal port; the display panel further comprises a plurality of switches; the exchanger comprises a first signal input end, a second signal input end, a first signal output end and a second signal output end; the first signal input end is electrically connected with the first data signal port, the second signal input end is electrically connected with the second data signal port, the first signal output end is electrically connected with the first data wire, and the second signal output end is electrically connected with the second data wire; in the display stage of the display panel, refreshing a plurality of pixel rows in sequence; the voltages of the j pixels in the x-th pixel row are respectively V_X1、V_X2To V_Xj(ii) a The voltages of j pixels in the x +1 th pixel row are respectively V_(x+1)1、V_(x+1)2To V_(x+1)j(ii) a In the x pixel row, the sum of the voltages of at least some odd pixels is V1, and the sum of the voltages of even pixels is V2; when j is an odd number, V1 ═ V_X1+V_X3+……+V_X(j-2)，V2＝V_X2+V_X4+……+V_X(j-1)(ii) a When j is an even number, V1 ═ V_X1+V_X3+……+V_X(j-1)，V2＝V_X2+V_X4+……+V_Xj(ii) a In the x +1 th pixel row, the sum of the voltages of the even numbered pixels is V3; when j is an odd number, V3 ═ V_(x+1)2+V_(x+1)4+……+V_(x+1)(j-1)(ii) a When j is an even number, V3 ═ V_(x+1)2+V_(x+1)4+……+V_(x+1)j；△V₁| (V1-V3) |/h; when j is an odd number, h is (j-1)2; when j is an even number, h is j/2; delta V₂V1-V3-V2-V3; when the x-th pixel row is refreshed, the first data signal port transmits an electric signal to the first data line through the exchanger, and the second data signal port transmits an electric signal to the second data line through the exchanger; when refreshing the x +1 th row of pixels, when Δ V₁≥V_yAnd Δ V₂When the data signal is more than or equal to 0, the first data signal port transmits an electric signal to the second data line through the exchanger, and the second data signal port transmits an electric signal to the first data line through the exchanger; when Δ V₁＜V_yOr Δ V₂When the number is less than 0, the first data signal port transmits an electric signal to the first data line through the exchanger, and the second data signal port transmits an electric signal to the second data line through the exchanger; wherein, V_yIs a preset voltage, and x and j are positive integers.

The invention also provides a display device which comprises the display panel provided by the invention.

Compared with the prior art, the display panel and the display device provided by the invention at least realize the following beneficial effects:

in the display panel and the display device provided by the invention, the pixels are arranged in a zigzag structure. In the display panel, the data signal port is electrically connected with the signal processing unit and transmits an electric signal to the data line. The display panel includes a plurality of data line groups including a first data line and a second data line and a plurality of port groups including a first data signal port and a second data signal port. The display panel is provided with a plurality of exchangers, and the data signal ports transmit electric signals to the data lines through the exchangers. Specifically, the exchanger comprises a first signal input end, a second signal input end, a first signal output end and a second signal output end; the first signal input end is electrically connected with the first data signal port, the second signal input end is electrically connected with the second data signal port, the first signal output end is electrically connected with the first data wire, and the second signal output end is electrically connected with the second data wire. When the pixels of two adjacent rows are refreshed, the working mode that the port group transmits the electric signals to the data line group is selected according to the voltage change condition of the pixels of the two adjacent rows. The data signal port can reduce the load of the signal processing unit without transmitting an electric signal with large voltage change to the data line, thereby reducing the power consumption of the signal processing unit and the power consumption of the display panel.

Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic partial structure diagram of a display panel provided in the prior art;

fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a partial structure of the display panel provided in FIG. 3;

FIG. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a partial structure of the display panel provided in FIG. 5;

FIG. 7 is a schematic diagram of a partial structure of another display panel according to an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 9 is a schematic diagram showing waveforms of signals of a control signal unit in the display panel provided in FIG. 8;

fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

Referring to fig. 2, the present embodiment provides a display panel, including: a display area AA and a non-display area BB surrounding the display area AA; the display area AA includes a plurality of pixels P; the plurality of pixels P includes a plurality of pixel rows 101 and a plurality of pixel columns 102; each pixel row 101 comprises j pixels P; the display area AA includes a plurality of data lines 20; the data line 20 is disposed between two adjacent pixel columns 102; the data line 20 includes opposite first and second sides S1 and S2; the data line 20 is electrically connected to the odd-numbered row of pixels P in the pixel column 102 at the first side S1 thereof, and the data line 20 is electrically connected to the even-numbered row of pixels P in the pixel column 102 at the second side S2 thereof; the non-display area BB includes a plurality of data signal ports 30, the data signal ports 30 are electrically connected to a signal processing unit (not shown), and the data signal ports 30 transmit electrical signals to the data lines 20;

the plurality of data lines 20 includes a plurality of data line groups 200, and the data line groups 200 include two adjacent data lines 20; two adjacent data lines 20 are respectively a first data line 21 and a second data line 22;

the plurality of data signal ports 30 includes a plurality of port groups 300, the port groups 300 including two adjacent data signal ports 30; the two adjacent data signal ports 30 are respectively a first data signal port 31 and a second data signal port 32;

the display panel further comprises a plurality of switches 40; the switch 40 comprises a first signal input terminal R1, a second signal input terminal R2, a first signal output terminal C1, and a second signal output terminal C2; the first signal input terminal R1 is electrically connected to the first data signal port 31, the second signal input terminal R2 is electrically connected to the second data signal port 32, the first signal output terminal C1 is electrically connected to the first data line 21, and the second signal output terminal C2 is electrically connected to the second data line 22;

in the display stage of the display panel, a plurality of pixel rows 101 are refreshed in sequence; the voltages of the j pixels in the x-th pixel row are respectively V_X1、V_X2To V_Xj(ii) a The voltages of j pixels in the x +1 th pixel row are respectively V_(x+1)1、V_(x+1)2To V_(x+1)j；

In the x pixel column, the sum of the voltages of at least some odd pixels P is V1, and the sum of the voltages of even pixels P is V2; when j is an odd number, V1 ═ V_X1+V_X3+……+V_X(j-2)，V2＝V_X2+V_X4+……+V_X(j-1)(ii) a When j is an even number, V1 ═ V_X1+V_X3+……+V_X(j-1)，V2＝V_X2+V_X4+……+V_Xj；

In the x +1 th pixel row, the sum of the voltages of the even numbered pixels P is V3; when j is an odd number, V3 ═ V_(x+1)2+V_(x+1)4+……+V_(x+1)(j-1)(ii) a When j is an even number, V3 ═ V_(x+1)2+V_(x+1)4+……+V_(x+1)j；△V₁| (V1-V3) |/h; when j is an odd number, h is (j-1)/2; when j is an even number, h is j/2; delta V₂＝|V1－V3|－|V2－V3|；

When the x-th pixel row is refreshed, the first data signal port 31 transmits an electric signal to the first data line 21 through the switch 40, and the second data signal port 32 transmits an electric signal to the second data line 22 through the switch 40;

when refreshing the x +1 th row of pixels, when Δ V₁≥V_yAnd Δ V₂When the data signal is equal to or larger than 0, the first data signal port 31 transmits the electric signal to the second data line 22 through the switch 40, and the second data signal port 32 transmits the electric signal to the first data line 21 through the switch 40;

when Δ V₁＜V_yOr Δ V₂When the signal is less than 0, the first data signal port 31 transmits an electric signal to the first data line 21 through the switch 40, and the second data signal port 32 transmits an electric signal to the second data line 22 through the switch 40; wherein, V_yIs a preset voltage, and x and j are positive integers.

In the display panel provided in this embodiment, the display area AA includes a plurality of pixels P, and the plurality of pixels P are used for implementing a display function. The pixels P located in the same row along the row direction a1 are a pixel row 101, and the pixels P located in the same column along the column direction a2 are a pixel column 102. The plurality of pixel rows 101 are, in order: a1 st pixel row 1011, a2 nd pixel row 1012, a 3 rd pixel row 1013, and a 4 th pixel row 1014 to an m-th pixel row 101 m. The multi-pixel row 101 includes an odd-numbered row and an even-numbered row, for example, the 1 st pixel row 1011 and the 3 rd pixel row 1013 are both odd-numbered rows, and the 2 nd pixel row 1012 and the 4 th pixel row 1014 are both even-numbered rows. Each pixel row 101 comprises j pixels P.

The display panel provided by the embodiment comprises j pixel columns:

pixel columns

1, 2, 3, 4, 1024 to 102j 1021.

The pixel located in the 1 st pixel row 1011 and the 1 st pixel column 1021 is a pixel P11, the pixel located in the 1 st pixel row 1011 and the 2 nd pixel column 1022 is a pixel P12, the pixel located in the 2 nd pixel row 1012 and the 2 nd pixel column 1022 is a pixel P22, and the pixel located in the m th pixel row 101m and the j th pixel column 102j is a pixel Pmj. And by analogy, the pixels positioned in the a-th pixel row and the b-th pixel column are pixels Pab, wherein a is less than or equal to m, and b is less than or equal to j.

Wherein the row direction a1 and the column direction a2 intersect; optionally, the row direction a1 and the column direction a2 are perpendicular.

In the display panel provided in this embodiment, the pixels are arranged in a zigzag structure. Specifically, the display area AA includes a plurality of data lines 20. Among the plurality of data lines 20, the first data line is a data line 20a, and the last data line is a data line 20 b. It is understood that the remaining data lines 20 are disposed in a region between two adjacent pixel columns 102 except for the

data lines

20a and 20 b.

The data line 20 includes opposite first and second sides S1 and S2, the data line 20 is electrically connected to the odd-numbered row of pixels P in the pixel column 102 at the first side S1 thereof, and the data line 20 is electrically connected to the even-numbered row of pixels P in the pixel column 102 at the second side S2 thereof. It is to be understood that, since the pixel column 102 is not disposed at the first side S1 of the data line 20a, the data line 20a is electrically connected only to the even-numbered row pixels P in the pixel column 102 at the second side S2 thereof. Since the second side S2 of the data line 20b is not provided with the pixel columns 102, the data line 20b is electrically connected to only the odd-numbered pixels P in the pixel columns 102 at the first side S1 thereof.

The non-display area BB includes a plurality of data signal ports 30, the data signal ports 30 are electrically connected to a signal processing unit (not shown), and the data signal ports 30 transmit electrical signals to the data lines 20. Alternatively, the data signal ports 30 may be conductive pads fabricated in the display panel. Optionally, the signal processing unit is an integrated circuit chip. The conductive pads may be electrically connected with the integrated circuit chip; alternatively, the conductive pad may be electrically connected to one end of a Flexible Printed Circuit (FPC) and the other end of the Flexible Printed Circuit may be electrically connected to an integrated Circuit chip provided in the display panel. Optionally, the signal processing unit is a signal processing circuit fabricated in the display panel, and the signal processing circuit is formed by fabricating circuit elements and circuit traces using a film structure in the display panel in a process of fabricating the display panel. The signal processing circuit has a signal input terminal and a signal output terminal, an electric signal outside the display panel can be transmitted to the data signal port 30 after entering the signal processing circuit from the signal input terminal, and the data signal port 30 can be the signal output terminal of the signal processing circuit.

In the display panel provided in the present embodiment, the plurality of data lines 20 includes a plurality of data line groups 200, the data line groups 200 include two adjacent data lines 20, and any one data line 20 cannot belong to two data line groups 200 at the same time. The plurality of data signal ports 30 includes a plurality of port groups 300, the port groups 300 include two adjacent data signal ports 30, and any one data signal port 30 cannot belong to two port groups 300 at the same time.

The display panel further includes a plurality of switches 40, the port groups 300 and the data line groups 200 are arranged in a one-to-one correspondence, and the port groups 300 transmit electrical signals to the correspondingly arranged data line groups 200 through the switches 40. The switch 40 has a function of switching electric signals. The operation mode of the port set 300 for transmitting the electrical signal to the data line set 200 includes two modes.

Specifically, in the first operation mode, the first data signal port 31 transmits an electrical signal to the first data line 21 through the switch 40, and the second data signal port 32 transmits an electrical signal to the second data line 22 through the switch 40; in the second operation mode, the first data signal port 31 transmits the electrical signal to the second data line 22 through the switch 40, and the second data signal port 32 transmits the electrical signal to the first data line 21 through the switch 40.

The display panel comprises a display stage in the working process, and in the display stage, the display panel executes a display function and displays image information. Specifically, the display panel sequentially refreshes the plurality of pixel rows 101 to update the image displayed by the plurality of pixels P in the plurality of pixel rows 101.

When the x-th pixel row is refreshed, the operation mode in which the port group 300 transmits an electrical signal to the data line group 200 is the first operation mode.

Before refreshing the x +1 th pixel row, the voltage variation of the electrical signal transmitted by the data line 20 is first determined to select the operation mode of the port set 300 for transmitting the electrical signal to the data line set 200.

Specifically, the voltage of the pixel Pab is V_ab. The voltages of the j pixels in the x-th pixel row are respectively V_X1、V_X2To V_XjFor example, the voltages of the j pixels in the 1 st pixel row are respectively V₁₁、V₁₂To V_1j. The voltages of j pixels in the x +1 th pixel row are respectively V_(x+1)1、V_(x+1)2To V_(x+1)jE.g. 2 ndThe voltages of j pixels in the pixel row are respectively V₂₁、V₂₂To V_2j。

In the x-th pixel row, the sum of voltages of at least some of the odd-numbered pixels P is V1, and the sum of voltages of the even-numbered pixels P is V2. When j is an odd number, the sum of voltages of the pixels P except the jth pixel in the xth pixel row is V1, and V1 is V_X1+V_X3+……+V_X(j-2)(ii) a The sum of the voltages of all the even-numbered pixels P in the x-th pixel row is V2, and V2 is V_X2+V_X4+……+V_X(j-1)。

When j is an even number, the sum of voltages of all the odd-numbered pixels P in the x-th pixel row is V1, and V1 is V_X1+V_X3+……+V_X(j-1)(ii) a In the x-th pixel row, the sum of voltages of all the even-numbered pixels P is V2, and V2 is V_X2+V_X4+……+V_Xj。

In the x +1 th pixel row, the sum of the voltages of all the even-numbered pixels P is V3. When j is an odd number, V3 ═ V_(x+1)2+V_(x+1)4+……+V_(x+1)(j-1)(ii) a When j is an even number, V3 ═ V_(x+1)2+V_(x+1)4+……+V_(x+1)j。

△V₁| (V1-V3) |/h; when j is an odd number, h is (j-1)/2; when j is an even number, h is j/2. Specifically, the present embodiment is described herein with j as an even number. Since V1 is V_X1+V_X3+……+V_X(j-1)，V3＝V_(x+1)2+V_(x+1)4+……+V_(x+1)jThus Δ V₁＝(V1－V3)/h＝|【(V_X1+V_X3+……+V_X(j-1))－(V_(x+1)2+V_(x+1)4+……+V_(x+1)j)】|/h＝|【(V_X1－V_(x+1)2)+(V_X3－V_(x+1)4)+……+(V_X(j-1)－V_(x+1)j) H. Wherein, Px1 and P (x +1)2 are electrically connected with the same data line, Px3 and P (x +1)4 are electrically connected with the same data line, … …, Px (j-1) and P (x +1) j are electrically connected with the same data line.

Specifically, the present invention is described herein by taking x ═ 1 as an example, and Δ V₁＝|【(V₁₁－V₂₂)+(V₁₃－V₂₄)+……+(V_1(j-1)－V_2j) H. The pixel P11 and the pixel P22 are electrically connected to the same first data line 21, (V)₁₁－V₂₂) Is the variation value of the voltage of the one first data line 21; the pixel P13 and the pixel P24 are electrically connected to the same first data line 21, (V)₁₃－V₂₄) Is the variation value of the voltage of the one first data line 21; … …, respectively; the pixel P1 (j-1) and the pixel P2j are electrically connected to the same first data line 21, (V)_1(j-1)－V_2j) Is a variation value of the voltage of the one first data line 21. Delta V₁I.e., an average value of the variation values of the voltages of the plurality of first data lines 21.

When Δ V₁≥V_yWhen the voltage is equal to or higher than the preset voltage V, the average value of the variation values of the voltage of the first data line 21 is_yThat is, when the x-th pixel row and the x + 1-th pixel row are sequentially refreshed, the voltage of the first data line 21 has a large variation value.

△V₂Specifically, the present embodiment is described herein with j as an even number only as an example. Since V1 is V_X1+V_X3+……+V_X(j-1)，V2＝V_X2+V_X4+……+V_Xj，V3＝V_(x+1)2+V_(x+1)4+……+V_(x+1)jThus Δ V₂＝|V1－V3|－|V2－V3|＝|(V_X1+V_X3+……+V_X(j-1))－(V_(x+1)2+V_(x+1)4+……+V_(x+1)j)|－|(V_X2+V_X4+……+V_Xj)－(V_(x+1)2+V_(x+1)4+……+V_(x+1)j)|＝|(V_X1－V_(x+1)2)+(V_X3－V_(x+1)4)+……+(V_X(j-1)－V_(x+1)j)|－|(V_X2－V_(x+1)2)+(V_X4－V_(x+1)4)+……+(V_Xj－V_(x+1)j) L. Wherein, the pixel Px1 and the pixel P (x +1)2 are electrically connected with the same data line, the pixel Px3 and the pixel P (x +1)4 are electrically connected with the same data line, … …, and the pixel Px (j-1) and the pixel P (x +1) j are electrically connected with the same data lineConnecting; the pixel Px2 and the pixel P (x +1)2 are located in the same column, the pixel Px4 and the pixel P (x +1)4 are located in the same column, … …, and the pixel Pxj and the pixel P (x +1) j are located in the same column.

Specifically, the present invention is described herein by taking x ═ 1 as an example, and Δ V₂＝|(V₁₁－V₂₂)+(V₁₃－V₂₄)+……+(V_1(j-1)－V_2j)|－|(V₁₂－V₂₂)+(V₁₄－V₂₄)+……+(V_1j－V_2j)|。

The pixel P11 and the pixel P22 are electrically connected to the same first data line 21, (V)₁₁－V₂₂) Is the variation value of the voltage of the one first data line 21; the pixel P13 and the pixel P24 are electrically connected to the same first data line 21, (V)₁₃－V₂₄) Is the variation value of the voltage of the one first data line 21; … …, respectively; the pixel P1 (j-1) and the pixel P2j are electrically connected to the same first data line 21, (V)_1(j-1)－V_2j) Is a variation value of the voltage of the one first data line 21. The | V1-V3 | is the sum of the voltage changes of the first data lines 21.

Pixel P12 and pixel P22 are in the same column; pixel P14 and pixel P24 are in the same column; … …, respectively; the pixel P1j and the pixel P2j are in the same column. In the first mode of operation, the second data signal port 32 transmits electrical signals to the second data line 22 through the switch 40; in a second mode of operation, the second data signal port 32 transmits electrical signals to the first data line 21 through the switch 40. I.e., V2-V3 i, when the 2 nd row of pixels is refreshed, the sum of the voltage variation values of the second data signal port 32 is obtained if the operation mode of the port set 300 for transmitting the electrical signal to the data line set 200 is switched to the second operation mode. The smaller the value of | V2-V3 | indicates that the smaller the change in voltage of the second data signal port 32 is if the operation mode in which the port set 300 transmits the electrical signal to the data line set 200 is switched to the second operation mode. Therefore, the smaller the value of | V2-V3 |, the more advantageous the power consumption of the signal processing unit is to be reduced when the operation mode of the port set 300 for transmitting the electrical signal to the data line set 200 is switched to the second operation mode.

When Δ V₂And > 0, i.e. | V1-V3 | ≧ V2-V3 |, i.e. the sum of the variation values of the voltages of the plurality of first data lines 21 is larger than the sum of the variation values of the voltages of the second data signal ports 32 if the operation mode of the port group 300 for transmitting the electrical signals to the data line group 200 is switched to the second operation mode.

In the display panel provided in this embodiment, when the x-th row of pixels and the x + 1-th row of pixels are refreshed, Δ V is obtained₁≥V_yAnd Δ V₂When the voltage is larger than or equal to 0, the variation value of the voltage of the plurality of first data lines 21 is larger, and the second working mode is favorable for reducing the power consumption of the signal processing unit. Therefore, the operation mode of the port set 300 for transmitting the electrical signal to the data line set 200 is switched from the first operation mode to the second operation mode.

When refreshing the x row pixels and the x +1 row pixels, when Δ V₁＜V_yOr Δ V₂When < 0, it means that the variation value of the voltages of the plurality of first data lines 21 is relatively small, or the second operation mode may not reduce the power consumption of the signal processing unit. At this time, the operation mode of the port set 300 transmitting the electrical signal to the data line set 200 is not required to be switched, and the operation mode of the port set 300 transmitting the electrical signal to the data line set 200 is still the first operation mode.

In the display panel provided in this embodiment, when the pixels in two adjacent rows are refreshed, the operation mode in which the port group transmits the electrical signal to the data line group is selected according to the voltage variation of the pixels in two adjacent rows. The data signal port can reduce the load of the signal processing unit without transmitting an electric signal with large voltage change to the data line, thereby reducing the power consumption of the signal processing unit and the power consumption of the display panel.

Optionally, the voltage when the pixel displays 255 gray scales is V₂₅₅，V_y＝V₂₅₅/2. When Δ V₁≥V₂₅₅At time/2, the average value of the voltage variation of the first data line 21 is large, and may be used as one of the criteria for determining whether to switch the operation mode in which the port group 300 transmits the electrical signal to the data line group 200.

In some alternative embodiments, referring to fig. 3 and 4, the switch 40 includes a first switch T1, a second switch T2, a third switch T3, and a fourth switch T4; the first switch T1 receives a first voltage signal to control the connection or disconnection between the first data signal port 31 and the first data line 21; the second switch T2 receives the second voltage signal to control the connection or disconnection between the second data signal port 32 and the first data line 21; the third switch T3 receives the third voltage signal to control the second data signal port 32 and the second data line 22 to be turned on or off; the fourth switch T4 receives the fourth voltage signal to control the connection or disconnection between the first data signal port 31 and the second data line 22.

In some alternative embodiments, with continued reference to fig. 3 and 4, the gate of the first switch T1 is electrically connected to the first voltage signal line L1, the first pole of the first switch T1 is electrically connected to the first signal input terminal R1, and the second pole of the first switch T1 is electrically connected to the first signal output terminal C1. The first voltage signal line L1 transmits a first voltage signal for controlling the turn-on or turn-off of the first switch T1 to the gate of the first switch T1. When the first switch T1 is turned on, an electrical signal at the first signal input terminal R1 may be transmitted to the first data line 21.

The gate of the second switch T2 is electrically connected to the second voltage signal line L2, the first pole of the second switch T2 is electrically connected to the second signal input terminal R2, and the second pole of the second switch T2 is electrically connected to the first signal output terminal C1. The second voltage signal line L2 transmits a second voltage signal for controlling the turn-on or turn-off of the second switch T2 to the gate of the second switch T2. When the second switch T2 is turned on, an electrical signal at the second signal input terminal R2 may be transmitted to the first data line 21.

A gate of the third switch T3 is electrically connected to the third voltage signal line L3, a first pole of the third switch T3 is electrically connected to the second signal input terminal R2, and a second pole of the third switch T3 is electrically connected to the second signal output terminal C2. The third voltage signal line L3 transmits a third voltage signal for controlling the third switch T3 to be turned on or off to the gate of the third switch T3. When the third switch T3 is turned on, an electrical signal at the second signal input terminal R2 may be transmitted to the second data line 22.

The gate of the fourth switch T4 is electrically connected to the fourth voltage signal line L4, the first pole of the fourth switch T4 is electrically connected to the first signal input terminal R1, and the second pole of the fourth switch T4 is electrically connected to the second signal output terminal C2. The fourth voltage signal line L4 transmits a fourth voltage signal for controlling the fourth switch T4 to be turned on or off to the gate of the fourth switch T4. When the fourth switch T4 is turned on, an electrical signal at the first signal input terminal R1 may be transmitted to the second data line 22.

In some alternative embodiments, with continued reference to fig. 3 and 4, the first switch T1 and the third switch T3 are both N-type thin film transistors, and the second switch T2 and the fourth switch T4 are both P-type thin film transistors; alternatively, the first switch T1 and the third switch T3 are both P-type thin film transistors, and the second switch T2 and the fourth switch T4 are both N-type thin film transistors. In the display panel shown in fig. 3 and 4, only the first switch T1 and the third switch T3 are both N-type thin film transistors, and the second switch T2 and the fourth switch T4 are both P-type thin film transistors will be described as an example. Thin film transistors can be classified into N-type thin film transistors that conduct electricity through free electrons and P-type thin film transistors that conduct electricity through holes, according to the difference in conduction channel.

Optionally, the first voltage signal, the second voltage signal, the third voltage signal, and the fourth voltage signal are the same voltage signal. As is known, the voltage for controlling the P-type tft to be turned on is lower, and the voltage for controlling the N-type tft to be turned on is higher. A low-voltage electric signal can control the P-type thin film transistor to be switched on and control the N-type thin film transistor to be switched off; alternatively, a high voltage electrical signal may control the P-type tft to turn off and the N-type tft to turn on.

Specifically, the present embodiment is described herein by taking only the first switch T1 and the third switch T3 which are both N-type thin film transistors and the second switch T2 and the fourth switch T4 which are both P-type thin film transistors as examples. When the first voltage signal, the second voltage signal, the third voltage signal and the fourth voltage signal are all low voltage signals, the first switch T1 and the third switch T3 are turned off, and the second switch T2 and the fourth switch T4 are turned on, and the operation mode of the port group 300 for transmitting the electrical signal to the data line group 200 is the second operation mode, that is, the first data signal port 31 transmits the electrical signal to the second data line 22 through the switch 40, and the second data signal port 32 transmits the electrical signal to the first data line 21 through the switch 40. When the first voltage signal, the second voltage signal, the third voltage signal and the fourth voltage signal are all high voltage signals, the first switch T1 and the third switch T3 are turned on, the second switch T2 and the fourth switch T4 are turned off, and the operation mode of the port group 300 for transmitting the electrical signal to the data line group 200 is the first operation mode, that is, the first data signal port 31 transmits the electrical signal to the first data line 21 through the switch 40, and the second data signal port 32 transmits the electrical signal to the second data line 22 through the switch 40.

Optionally, with continued reference to fig. 3 and 4, the first voltage signal line L1, the second voltage signal line L2, the third voltage signal line L3 and the fourth voltage signal line L4 are electrically connected. Specifically, the first voltage signal line L1, the second voltage signal line L2, the third voltage signal line L3, and the fourth voltage signal line L4 are electrically connected to the common voltage signal line LC. In the display panel provided in this embodiment, the common voltage signal line LC is used to provide electrical signals for the first switch T1, the second switch T2, the third switch T3, and the fourth switch T4 in the switch 40, which is beneficial to saving the number of wires in the display panel, and is beneficial to saving the number of electrical signals provided by the signal processing unit, and simplifying the design of the display panel.

In some alternative embodiments, the display panel further includes a control signal unit 50, the control signal unit 50 including a first control signal input terminal RC1, a second control signal input terminal RC2, and a control signal output terminal CC; the first control signal input terminal RC1 is electrically connected to the signal processing unit for receiving a first control signal, and the second control signal input terminal RC2 is electrically connected to the signal processing unit for receiving a second control signal.

The control signal output terminal CC is electrically connected to the first voltage signal line L1, the second voltage signal line L2, the third voltage signal line 3 and the fourth voltage signal line L4; optionally, the control signal output terminal CC is electrically connected to the common voltage signal line LC.

When Δ V₁≥V_yAnd Δ V₂When the voltage is more than or equal to 0, the control signal output end CC outputs a first control signal to control the first switch T1 and the third switch T3 to be switched off, and the second switch T2 and the fourth switch T4 to be switched on. Under the action of the first control signal, the operation mode of the port group 300 for transmitting the electrical signal to the data line group 200 is the second operation mode, that is, the first data signal port 31 transmits the electrical signal to the second data line 22 through the switch 40, and the second data signal port 32 transmits the electrical signal to the first data line 21 through the switch 40.

When Δ V₁＜V_yOr Δ V₂When the output voltage is less than 0, the control signal output terminal CC outputs the second control signal to control the second switch T2 and the fourth switch T4 to be turned off, and the first switch T1 and the third switch T3 to be turned on. Under the action of the second control signal, the operation mode of the port group 300 for transmitting the electrical signal to the data line group 200 is the first operation mode, that is, the first data signal port 31 transmits the electrical signal to the first data line 21 through the switch 40, and the second data signal port 32 transmits the electrical signal to the second data line 22 through the switch 40.

In the display panel provided in the present embodiment, the control signal unit 50 is configured to output control signals to the first voltage signal line L1, the second voltage signal line L2, the third voltage signal line 3, and the fourth voltage signal line L4 to control the first switch T1, the second switch T2, the third switch T3, and the fourth switch T4 in the switch 40 to be turned on or off. The signal processing unit provides the first control signal and the second control signal to the control signal unit 50, and the control signal unit outputs one of the first control signal and the second control signal according to the demand of the display panel.

In some alternative embodiments, the control signal unit 50 includes a first control switch TC1, a second control switch TC2, and a switching signal input terminal RT; one of the first control switch TC1 and the second control switch TC2 is an N-type thin film transistor, and the other is a P-type thin film transistor; the grid of the first control switch TC1 is electrically connected with the switch signal input end RT, the first pole of the first control switch TC1 is electrically connected with the first control signal input end RC1, and the second pole of the first control switch TC1 is electrically connected with the control signal output end CC; the gate of the second control switch TC2 is electrically connected to the switching signal input terminal RT, the first pole of the second control switch TC2 is electrically connected to the second control signal input terminal RC2, and the second pole of the second control switch TC2 is electrically connected to the control signal output terminal CC.

In the display panel provided in this embodiment, the switch signal input terminal RT is used for receiving a switch control signal to control the first control switch TC1 and the second control switch TC2 to be turned on or off. Since one of the first control switch TC1 and the second control switch TC2 is an N-type thin film transistor and the other is a P-type thin film transistor, a low-voltage switch control signal can control the P-type thin film transistor to be turned on and the N-type thin film transistor to be turned off; alternatively, a high voltage switch control signal may control the P-type tft to be turned off and the N-type tft to be turned on. That is, in the control signal unit 50, one of the first control switch TC1 and the second control switch TC2 is turned on and the other is turned off, so that the control signal output terminal CC may output one of the first control signal and the second control signal according to the requirements of the display panel.

In some alternative embodiments, referring to fig. 7, the second switch T2, the fourth switch T4 and the first control switch TC1 are all P-type thin film transistors, and the first switch T1, the third switch T3 and the second control switch TC2 are all N-type thin film transistors.

Specifically, when Δ V₁≥V_yAnd Δ V₂When the voltage is more than or equal to 0, the switch signal input end RT receives a low-voltage switch control signal, the low-voltage switch control signal can control the first control switch TC1 to be switched on and control the second control switch TC2 to be switched off, and the control signal output end CC outputs the low-voltage first control signal; the first control signal with low voltage controls the second switch T2 and the fourth switch T4 to be turned on, and controls the first switch T1 and the third switch T3 to be turned off. The operation mode of the port set 300 transmitting the electrical signal to the data line set 200 is the second operation mode, that is, the first data signal port 31 transmits the electrical signal to the second data line 22 through the switch 40, and the second data signal port 32 transmits the electrical signal to the first data line 21 through the switch 40.

When Δ V₁＜V_yOr Δ V₂When the voltage is less than 0, the switch signal input end RT receives a high-voltage switch control signal which can control the first control switch TC1 to be cut off and control the second control switch TC2 to be switched on, and the control signal output end CC outputs a high-voltage second control signal; the second control signal with high voltage controls the second switch T2 and the fourth switch T4 to be turned off, and controls the first switch T1 and the third switch T3 to be turned on. The operation mode of the port set 300 for transmitting the electrical signal to the data line set 200 is the first operation mode, that is, the first data signal port 31 transmits the electrical signal to the first data line 21 through the switch 40, and the second data signal port 32 transmits the electrical signal to the second data line 22 through the switch 40.

Optionally, please refer to fig. 7, fig. 8 and fig. 9 in combination. When the display panel provided in this embodiment displays a heavy load picture, for example, in one frame picture, the pixel voltage of the pixels P in the odd-numbered pixel rows 102 is 5V, and the pixel voltage of the pixels P in the even-numbered pixel rows 102 is 0V.

In the display stage of the display panel, the process of displaying a frame of picture comprises the following steps: the first sub-phase Ti1 of refreshing the 1 st pixel row, the second sub-phase Ti2 of refreshing the 2 nd pixel row, the third sub-phase Ti3 of refreshing the 3 rd pixel row, the fourth sub-phase Ti4 of refreshing the 4 th pixel row, the fifth sub-phases Ti5, … … of refreshing the 5 th pixel row to the m-th sub-phase Tim of refreshing the m-th pixel row.

In the process of displaying a frame of picture, the switch signal input terminal RT always receives a high-voltage switch control signal, the high-voltage switch control signal can control the first control switch TC1 to be turned off and the second control switch TC2 to be turned on, and the control signal output terminal CC outputs a second control signal.

The second control signal input terminal RC2 receives a square wave signal, and the electrical signal at the second control signal input terminal RC2 changes every time a pixel row is refreshed. Specifically, the peaks of the square wave signal represent high voltage electrical signals, and the troughs of the square wave signal represent low voltage electrical signals.

In the first sub-phase Ti1 of refreshing the 1 st pixel row 1011, the high-voltage second control signal controls the second switch T2 and the fourth switch T4 to be turned off, and controls the first switch T1 and the third switch T3 to be turned on. The operation mode of the port set 300 for transmitting the electrical signal to the data line set 200 is the first operation mode, that is, the first data signal port 31 transmits the electrical signal to the first data line 21 through the switch 40, and the second data signal port 32 transmits the electrical signal to the second data line 22 through the switch 40. In the second sub-phase Ti2 of refreshing the 2 nd pixel row 1012, the second control signal with low voltage controls the second switch T2 and the fourth switch T4 to be turned on, and controls the first switch T1 and the third switch T3 to be turned off. The operation mode of the port set 300 transmitting the electrical signal to the data line set 200 is the second operation mode, that is, the first data signal port 31 transmits the electrical signal to the second data line 22 through the switch 40, and the second data signal port 32 transmits the electrical signal to the first data line 21 through the switch 40. The display panel refreshes each pixel row in turn until the m-th pixel row 101m is refreshed.

In the display panel, during the first sub-phase Ti1 to the mth sub-phase Tim, the operation mode of the port group 300 for transmitting the electrical signal to the data line group 200 is alternately switched between the first operation mode and the second operation mode. The first data signal port 31 always transmits a voltage of 5V, the second data signal port 32 always transmits a voltage of 0V, and the first data signal port 31 and the second data signal port 32 do not need to frequently switch electrical signals, so that power consumption of the signal processing unit can be reduced.

The invention also provides a display device comprising the display panel provided by any one of the above embodiments of the invention. Referring to fig. 10, fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention. Fig. 10 provides a display device 1000 including the display panel 1001 according to any of the above embodiments of the present invention. The embodiment of fig. 10 is only an example of a mobile phone, and the display device 1000 is described, but it should be understood that the display device provided in the embodiment of the present invention may be other display devices with a display function, such as a computer, a television, and a vehicle-mounted display device, and the present invention is not limited thereto. The display device provided in the embodiment of the present invention has the beneficial effects of the display panel provided in the embodiment of the present invention, and specific reference may be made to the specific description of the display panel in each of the above embodiments, which is not repeated herein.

As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

in the display panel and the display device provided by the embodiments of the present invention, the pixels are arranged in a zigzag structure. In the display panel, the data signal port is electrically connected with the signal processing unit and transmits an electric signal to the data line. The display panel includes a plurality of data line groups including a first data line and a second data line and a plurality of port groups including a first data signal port and a second data signal port. The display panel is provided with a plurality of exchangers, and the data signal ports transmit electric signals to the data lines through the exchangers. Specifically, the exchanger comprises a first signal input end, a second signal input end, a first signal output end and a second signal output end; the first signal input end is electrically connected with the first data signal port, the second signal input end is electrically connected with the second data signal port, the first signal output end is electrically connected with the first data wire, and the second signal output end is electrically connected with the second data wire. When the pixels of two adjacent rows are refreshed, the working mode that the port group transmits the electric signals to the data line group is selected according to the voltage change condition of the pixels of the two adjacent rows. The data signal port can reduce the load of the signal processing unit without transmitting an electric signal with large voltage change to the data line, thereby reducing the power consumption of the signal processing unit and the power consumption of the display panel.

Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, comprising:

a display area and a non-display area surrounding the display area;

the display area comprises a plurality of pixels; the plurality of pixels comprises a plurality of pixel rows and a plurality of pixel columns; each of said rows of pixels comprising j of said pixels;

the display area comprises a plurality of data lines; the data line is arranged between two adjacent pixel columns;

the data line comprises a first side and a second side which are opposite; the data line is electrically connected with the pixels of the odd-numbered rows in the pixel columns on the first side thereof, and the data line is electrically connected with the pixels of the even-numbered rows in the pixel columns on the second side thereof;

the non-display area comprises a plurality of data signal ports, the data signal ports are electrically connected with the signal processing unit, and the data signal ports transmit electric signals to the data lines;

the plurality of data lines comprise a plurality of data line groups, and each data line group comprises two adjacent data lines; the two adjacent data lines are respectively a first data line and a second data line;

the plurality of data signal ports comprises a plurality of port groups, and each port group comprises two adjacent data signal ports; the two adjacent data signal ports are respectively a first data signal port and a second data signal port;

the display panel further comprises a plurality of switches; the exchanger comprises a first signal input end, a second signal input end, a first signal output end and a second signal output end; the first signal input end is electrically connected with the first data signal port, the second signal input end is electrically connected with the second data signal port, the first signal output end is electrically connected with the first data line, and the second signal output end is electrically connected with the second data line;

in the display stage of the display panel, refreshing the plurality of pixel rows in sequence;

the voltages of j pixels in the x-th pixel row are respectively V_X1、V_X2To V_Xj；

The voltages of j pixels in the x +1 th pixel row are respectively V_(x+1)1、V_(x+1)2To V_(x+1)j；

In the x-th pixel row, the sum of the voltages of at least part of the odd-numbered pixels is V1, and the sum of the voltages of the even-numbered pixels is V2; when j is an odd number, V1 ═ V_X1+V_X3+……+V_X(j-2)，V2＝V_X2+V_X4+……+V_X(j-1)(ii) a When j is an even number, V1 ═ V_X1+V_X3+……+V_X(j-1)，V2＝V_X2+V_X4+……+V_Xj；

In the x +1 th pixel row, the sum of the voltages of the even numbered pixels is V3; when j is an odd number, V3 ═ V_(x+1)2+V_(x+1)4+……+V_(x+1)(j-1)(ii) a When j is an even number, V3 ═ V_(x+1)2+V_(x+1)4+……+V_(x+1)j；

△V₁| (V1-V3) |/h; when j is an odd number, h is (j-1)/2; when j is an even number, h is j/2;

△V₂＝|V1－V3|－|V2－V3|；

when the x-th pixel row is refreshed, the first data signal port transmits an electric signal to the first data line through the exchanger, and the second data signal port transmits an electric signal to the second data line through the exchanger;

when refreshing the pixel row of the x +1 th pixel row, when Δ V₁≥V_yAnd Δ V₂When the data signal is greater than or equal to 0, the first data signal port transmits an electric signal to the second data line through the exchanger, and the second data signal port transmits an electric signal to the first data line through the exchanger; when Δ V₁＜V_yOr Δ V₂When the number is less than 0, the first data signal port transmits an electric signal to the first data line through the exchanger, and the second data signal port transmits an electric signal to the second data line through the exchanger; wherein, V_yIs a preset voltage, and x and j are positive integers.

2. The display panel according to claim 1,

the switch comprises a first switch, a second switch, a third switch and a fourth switch;

the first switch receives a first voltage signal to control the connection or disconnection of the first data signal port and the first data line;

the second switch receives a second voltage signal to control the connection or disconnection of the second data signal port and the first data line;

the third switch receives a third voltage signal to control the second data signal port and the second data line to be switched on or switched off;

the fourth switch receives a fourth voltage signal to control the connection or disconnection of the first data signal port and the second data line.

3. The display panel according to claim 2,

the grid electrode of the first switch is electrically connected with a first voltage signal wire, the first pole of the first switch is electrically connected with the first signal input end, and the second pole of the first switch is electrically connected with the first signal output end;

the grid electrode of the second switch is electrically connected with a second voltage signal wire, the first pole of the second switch is electrically connected with the second signal input end, and the second pole of the second switch is electrically connected with the first signal output end;

a gate of the third switch is electrically connected to a third voltage signal line, a first pole of the third switch is electrically connected to the second signal input terminal, and a second pole of the third switch is electrically connected to the second signal output terminal;

the grid electrode of the fourth switch is electrically connected with a fourth voltage signal line, the first pole of the fourth switch is electrically connected with the first signal input end, and the second pole of the fourth switch is electrically connected with the second signal output end.

4. The display panel according to claim 3,

the first switch and the third switch are both N-type thin film transistors, and the second switch and the fourth switch are both P-type thin film transistors; alternatively, the first and second electrodes may be,

the first switch and the third switch are both P-type thin film transistors, and the second switch and the fourth switch are both N-type thin film transistors.

5. The display panel according to claim 4,

the first voltage signal, the second voltage signal, the third voltage signal, and the fourth voltage signal are the same voltage signal.

6. The display panel according to claim 5,

the first voltage signal line, the second voltage signal line, the third voltage signal line, and the fourth voltage signal line are electrically connected.

7. The display panel according to claim 6,

the display panel also comprises a control signal unit, wherein the control signal unit comprises a first control signal input end, a second control signal input end and a control signal output end;

the first control signal input end is electrically connected with the signal processing unit to receive a first control signal, and the second control signal input end is electrically connected with the signal processing unit to receive a second control signal;

the control signal output end is electrically connected with the first voltage signal line, the second voltage signal line, the third voltage signal line and the fourth voltage signal line;

when Δ V₁≥V_yAnd Δ V₂When the output voltage is more than or equal to 0, the control signal output end outputs the first control signal to control the first switch and the second switchThe third switch is turned off, and the second switch and the fourth switch are turned on;

when Δ V₁＜V_yOr Δ V₂When the voltage is less than 0, the control signal output end outputs the second control signal to control the second switch and the fourth switch to be switched off and the first switch and the third switch to be switched on.

8. The display panel according to claim 7,

the control signal unit comprises a first control switch, a second control switch and a switch signal input end; one of the first control switch and the second control switch is an N-type thin film transistor, and the other one of the first control switch and the second control switch is a P-type thin film transistor;

the grid electrode of the first control switch is electrically connected with the switch signal input end, the first pole of the first control switch is electrically connected with the first control signal input end, and the second pole of the first control switch is electrically connected with the control signal output end;

the grid electrode of the second control switch is electrically connected with the switch signal input end, the first pole of the second control switch is electrically connected with the second control signal input end, and the second pole of the second control switch is electrically connected with the control signal output end.

9. The display panel according to claim 8,

the second switch, the fourth switch and the first control switch are all P-type thin film transistors, and the first switch, the third switch and the second control switch are all N-type thin film transistors.

10. The display panel according to claim 1,

the voltage when the pixel displays 255 gray scales is V₂₅₅，V_y＝V₂₅₅/2。

11. A display device characterized by comprising the display panel according to any one of claims 1 to 10.