CN109903714B

CN109903714B - Display device and driving method thereof

Info

Publication number: CN109903714B
Application number: CN201910243620.0A
Authority: CN
Inventors: 谷其兵; 刘蕊; 陈相逸; 罗信忠; 孙伟; 陈明
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Priority date: 2019-03-28
Filing date: 2019-03-28
Publication date: 2023-02-28
Anticipated expiration: 2039-03-28
Also published as: CN109903714A

Abstract

The invention discloses a display device and a driving method thereof, relates to the technical field of display, and aims to solve the problem of how to more effectively reduce the module power consumption of a display product by a simple implementation mode. The display device includes: a plurality of charge sharing circuits and control circuits; each charge sharing circuit is respectively coupled with at least three adjacent target data lines in the plurality of data lines, and the at least three adjacent target data lines receive signals with the same polarity; the control circuit is used for acquiring a target control signal in a charge sharing stage, controlling the charge sharing circuit to conduct the coupling between at least two target data lines of at least three adjacent target data lines correspondingly coupled with the charge sharing circuit according to the target control signal, converting a first data voltage signal into a shared data voltage signal closest to a second data voltage signal, and loading the shared data voltage signal on at least three adjacent target data lines. The display device provided by the invention is used for displaying.

Description

Display device and driving method thereof

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display device and a driving method thereof.

Background

Along with the continuous development of the display industry, people have higher and higher requirements on the technical capability of display products, wherein the module power consumption of the display products is taken as an important factor influencing the technical capability of the display products and is widely valued by people.

Disclosure of Invention

The invention aims to provide a display device and a driving method thereof, which are used for effectively reducing the module power consumption of a display product by a simple implementation mode.

In order to achieve the above purpose, the invention provides the following technical scheme:

a first aspect of the present invention provides a display device, including a plurality of data lines and a plurality of pixel units distributed in an array, wherein a part of the data lines receive signals with a first polarity, and a remaining part of the data lines receive signals with a second polarity, the first polarity and the second polarity being opposite, the display device further including:

a plurality of charge sharing circuits, each of the charge sharing circuits being respectively coupled to at least three adjacent target data lines of the plurality of data lines, the at least three adjacent target data lines receiving signals having the same polarity, and each of the target data lines corresponding to one of the charge sharing circuits;

a control circuit respectively coupled to the plurality of charge-sharing circuits and the plurality of data lines, the control circuit to: in a scanning stage, controlling the charge sharing circuit to disconnect the coupling between any two target data lines of the at least three adjacent target data lines which are correspondingly coupled with the charge sharing circuit, and loading first data voltage signals corresponding to the pixel units of the current scanning row to the at least three adjacent target data lines; in a charge sharing stage, a target control signal is obtained according to the first data voltage signal and a second data voltage signal corresponding to a pixel unit of a next scanning line, and the charge sharing circuit is controlled to conduct coupling between at least two target data lines of the at least three adjacent target data lines coupled correspondingly according to the target control signal, so that the first data voltage signal is converted into a shared data voltage signal closest to the second data voltage signal and loaded on the at least three adjacent target data lines.

Optionally, the control circuit includes: the time schedule controller and the source electrode driving chip are coupled; in the charge sharing stage, the timing controller is configured to obtain a target control signal according to the first data voltage signal and a second data voltage signal corresponding to a pixel unit of a next scanning line, and transmit the target control signal to the source driver chip;

the source driver chip is configured to control the charge sharing circuit to switch on the coupling between at least two target data lines of the at least three adjacent target data lines coupled to the charge sharing circuit according to the target control signal, so that the first data voltage signal is converted into a target shared data voltage signal closest to the second data voltage signal and is loaded on the at least three adjacent target data lines.

Optionally, the timing controller includes: the arithmetic unit and the first register unit are coupled;

the arithmetic unit is used for: calculating shared data voltage signals loaded on at least three adjacent target data lines in different coupling modes when the at least three adjacent target data lines coupled by the charge sharing circuit are coupled in different coupling modes according to the first data voltage signals; obtaining a target shared data voltage signal which is closest to the second data voltage signal in the shared data voltage signals corresponding to the coupling modes, and generating the target control signal in the coupling mode corresponding to the target shared data voltage signal and storing the target control signal in the first register unit;

the first register unit is used for transmitting the target control signal to the source driving chip according to a preset interface protocol.

Optionally, the control circuit includes: the timing controller and source driver chip that couple mutually, the source driver chip includes: the device comprises a second register unit, a third register unit, and a comparison unit respectively coupled with the second register unit and the third register unit; in the charge-sharing phase,

the time schedule controller is used for outputting an enable signal;

the second register unit is used for storing the first data voltage signal;

the third register unit is used for storing the second data voltage signal;

based on the enable signal, the comparing unit is configured to obtain, according to the first data voltage signal, a shared data voltage signal loaded on the at least three adjacent target data lines in each coupling manner when the at least three adjacent target data lines coupled to the charge sharing circuit are coupled in different coupling manners; and obtaining a target shared data voltage signal which is closest to the second data voltage signal in the shared data voltage signals corresponding to the coupling modes, generating the target control signal in the coupling mode corresponding to the target shared data voltage signal, and controlling the charge sharing circuit to conduct the coupling between at least two target data lines in the at least three adjacent target data lines coupled to the charge sharing circuit according to the target control signal, so that the first data voltage signal is converted into the target shared data voltage signal which is closest to the second data voltage signal and is loaded on the at least three adjacent target data lines.

Optionally, when the charge sharing circuit is respectively coupled to three adjacent target data lines of the plurality of data lines, the three adjacent target data lines include a first data line, a second data line, and a third data line sequentially arranged in a direction perpendicular to the data lines,

the charge sharing circuit includes:

the first control sub-circuit is respectively coupled with a first control end, the first data line and the third data line in the control circuit and is used for controlling the connection or disconnection of the first data line and the third data line under the control of the first control end;

the second control sub-circuit is respectively coupled with a second control terminal in the control circuit, the first data line and the second data line, and is used for controlling to switch on or off the coupling between the first data line and the second data line under the control of the second control terminal;

and the third control sub-circuit is respectively coupled with a third control end in the control circuit, the second data line and the third data line, and is used for controlling the connection or disconnection of the second data line and the third data line under the control of the third control end.

Optionally, the first control sub-circuit includes a first transistor, a gate of the first transistor is coupled to the first control terminal, a first pole of the first transistor is coupled to the first data line, and a second pole of the first transistor is coupled to the third data line;

the second control sub-circuit comprises a second transistor, a gate of the second transistor is coupled to the second control terminal, a first pole of the second transistor is coupled to the first data line, and a second pole of the second transistor is coupled to the second data line;

the third control sub-circuit includes a third transistor, a gate of which is coupled to the third control terminal, a first pole of which is coupled to the second data line, and a second pole of which is coupled to the third data line.

Optionally, odd-numbered data lines of the plurality of data lines receive signals having a first polarity, even-numbered data lines of the plurality of data lines receive signals having a second polarity,

the odd data lines in the data lines are divided into a plurality of groups of odd data line groups, the plurality of groups of odd data line groups are sequentially arranged along the direction vertical to the data lines, and each group of odd data line groups comprises three adjacent target data lines;

even data lines in the data lines are divided into a plurality of groups of even data line groups, the plurality of groups of even data line groups are sequentially arranged along a direction perpendicular to the data lines, and each group of even data line groups comprises three adjacent target data lines.

Based on the technical solution of the display device, a second aspect of the present invention provides a driving method of a display device, for driving the display device, the driving method including:

in a scanning phase, a control circuit in the display device controls a charge sharing circuit in the display device to disconnect the coupling between any two target data lines of the at least three adjacent target data lines coupled correspondingly with the charge sharing circuit, and loads first data voltage signals corresponding to pixel units of a current scanning row to the at least three adjacent target data lines;

in a charge sharing stage, the control circuit obtains a target control signal according to the first data voltage signal and a second data voltage signal corresponding to a pixel unit of a next scanning line, and controls the charge sharing circuit to conduct coupling between at least two target data lines of the at least three adjacent target data lines coupled correspondingly according to the target control signal, so that the first data voltage signal is converted into a shared data voltage signal closest to the second data voltage signal and loaded on the at least three adjacent target data lines.

Optionally, when the control circuit includes a timing controller and a source driver chip coupled to each other, and the timing controller includes an algorithm unit and a first register unit coupled to each other, in the charge sharing stage, the working process of the control circuit specifically includes:

the arithmetic unit calculates shared data voltage signals loaded on the at least three adjacent target data lines in different coupling modes when the at least three adjacent target data lines coupled with the charge sharing circuit are coupled in different coupling modes according to the first data voltage signals; obtaining a target shared data voltage signal which is closest to the second data voltage signal in the shared data voltage signals corresponding to the coupling modes, and generating the target control signal in the coupling mode corresponding to the target shared data voltage signal and storing the target control signal in the first register unit;

and the first register unit transmits the target control signal to the source electrode driving chip by a preset interface protocol.

Optionally, when the control circuit includes a timing controller and a source driver chip that are coupled to each other, and the source driver chip includes a second register unit, a third register unit, and a comparison unit that is coupled to the second register unit and the third register unit, in the charge sharing stage, the working process of the control circuit specifically includes:

the time schedule controller outputs an enable signal;

the second register unit stores the first data voltage signal;

the third register unit stores the second data voltage signal;

based on the enable signal, the comparison unit obtains, according to the first data voltage signal, shared data voltage signals loaded on the at least three adjacent target data lines in different coupling manners when the at least three adjacent target data lines coupled to the charge sharing circuit are coupled in different coupling manners; and obtaining a target shared data voltage signal which is closest to the second data voltage signal in the shared data voltage signals corresponding to the coupling modes, generating the target control signal according to the coupling mode corresponding to the target shared data voltage signal, and controlling the charge sharing circuit to conduct the coupling between at least two target data lines in the at least three adjacent target data lines correspondingly coupled to the charge sharing circuit according to the target control signal, so that the first data voltage signal is converted into the target shared data voltage signal which is closest to the second data voltage signal and is loaded on the at least three adjacent target data lines.

In the technical scheme provided by the invention, a plurality of charge sharing circuits and a control circuit which is respectively coupled with the charge sharing circuits and a plurality of data lines are arranged, wherein the charge sharing circuits are respectively coupled with at least three adjacent target data lines which receive signals with the same polarity in the plurality of data lines; the control circuit can control the charge sharing circuit to disconnect the coupling between any two target data lines of at least three adjacent target data lines correspondingly coupled with the charge sharing circuit in a scanning stage, and load first data voltage signals corresponding to the pixel units of the current scanning line to the at least three adjacent target data lines, so as to control the pixel units of the current scanning line to realize a normal display function; in the charge sharing stage, a target control signal is obtained according to a first data voltage signal and a second data voltage signal corresponding to a pixel unit of a next scanning line, and according to the target control signal, the charge sharing circuit is controlled to be connected with the coupling between at least two target data lines of at least three adjacent target data lines correspondingly coupled with the charge sharing circuit, so that the first data voltage signal is converted into a shared data voltage signal which is closest to the second data voltage signal and is loaded on the at least three adjacent target data lines; therefore, when the next row of pixel units are scanned, the minimum data voltage signal can be written into the target data line, and the display brightness corresponding to the second target data voltage signal can be displayed by the next row of pixel units, so that the power consumption is reduced to the maximum extent.

In addition, in the technical scheme provided by the invention, the target control signal can be obtained through calculation by the control circuit according to the first data voltage signal and the second data voltage signal corresponding to the pixel unit of the next scanning line, and then the shared data voltage signal closest to the second data voltage signal is loaded on the target data line according to the target control signal, so that the power consumption is reduced to the maximum extent.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not limit the invention. In the drawings:

FIG. 1 is a schematic diagram of charge sharing within the inventive concept;

FIG. 2 is a schematic diagram of a charge sharing circuit according to an embodiment of the present invention;

fig. 3 is a first structural diagram of a control circuit according to an embodiment of the invention;

fig. 4 is a second schematic structural diagram of the control circuit according to the embodiment of the present invention.

Reference numerals:

1-a charge sharing circuit, 11-a first control sub-circuit,

12-a second control sub-circuit, 13-a third control sub-circuit,

t1-the first transistor, T2-the second transistor,

t3-a third transistor, ctr 1-a first control terminal,

ctr 2-second control terminal, ctr 3-third control terminal,

a TCON-timing controller, an SD-source driver chip,

20-an arithmetic unit, 21-a first register unit,

30-a second register unit, 31-a third register unit,

32-comparison unit.

Detailed Description

To further explain the display device and the driving method thereof according to the embodiments of the present invention, the following detailed description is made with reference to the accompanying drawings.

According to the structure and display principle of the display device in the related art, the display device includes a plurality of pixel units distributed in an array, a plurality of scan lines and a plurality of data lines (e.g., S1-S6 in fig. 1), the plurality of pixel units are divided into a plurality of rows of pixel units, the scan lines correspond to the row of pixel units one to one, and the scan lines can control the corresponding row of pixel units to write data signals; meanwhile, the plurality of pixel units can be divided into a plurality of columns of pixel units, the data lines correspond to the column pixel units one by one, and the data lines can provide data signals for the corresponding column pixel units. When the display device actually displays, the pixel units are scanned line by the scanning lines, and when each row of pixel units is scanned, corresponding data signals are written into the pixel units of the row through the data lines.

Based on the structure and display manner of the display device, the inventor of the present invention has found that after the data line provides the corresponding first data voltage signal to the pixel units in the current row, the data line also retains the charges corresponding to the first data voltage signal, and the charges can be applied to the pixel units in the next row. In more detail, when the next row of pixel units is driven to display, the corresponding second data voltage signal needs to be provided for the next row of pixel units, and since the first data voltage signal remains in the data line, the difference data voltage signal (which is the difference between the second data voltage signal and the first data voltage signal) can be directly provided for the next row of pixel units, and when the next row of pixel units is scanned, the difference signal and the first data voltage signal can be jointly written into the next row of pixel units as the second data voltage signal, so that the display function of the next row of pixel units is realized.

The inventor of the present invention further studies and finds that, in order to ensure that the existing display device can achieve better working performance during actual operation, data voltage signals with opposite polarities are written into different data lines, so that, in all the data lines included in the display device, the polarity of a signal received by one part of the data lines is opposite to the polarity of a signal received by another part of the data lines, and therefore, a switch unit (e.g., the label 4 in fig. 1) can be disposed between the data lines receiving the same-polarity signals, and after the current row of pixel units is driven to display, the data lines receiving the same-polarity signals can be conducted through the switch unit, so that charges stored on the data lines receiving the same-polarity signals are shared, and the data lines receiving the same-polarity signals have the same pre-stored voltage V _{Average out} Then, when the next row of pixel units is driven, the same pre-stored voltage can be written into the next row of pixel units.

Specifically, referring to fig. 1, in fig. 1, data voltage signals with a first polarity are input to odd-numbered data lines, data voltage signals with a second polarity are input to even-numbered data lines, the first polarity is opposite to the second polarity, a switch unit 4 is disposed between adjacent odd-numbered data lines, the switch unit 4 can control conduction between adjacent odd-numbered data lines, a switch unit 4' is disposed between adjacent even-numbered data lines, the switch unit 4' can control conduction between adjacent even-numbered data lines, and simultaneously a control terminal of the switch unit 4 corresponding to the odd-numbered data line and a control terminal of the switch unit 4' corresponding to the even-numbered data line can be connected to the same control Signal line, that is, charge Sharing between all odd-numbered data lines and charge Sharing between all even-numbered data lines in the display device can be controlled simultaneously through a control Signal line (shared Signal).

Although the above method saves power consumption to a certain extent, only one charge sharing method can be implemented between the data lines receiving signals with the same polarity, and this charge sharing method can only play a role of saving power in some display modes, and in some other display modes, due to excessive short circuit between the data lines, power consumption cannot be saved, but power consumption is wasted. Based on this, the inventors of the present invention considered to provide a charge sharing circuit and a control circuit in a display device, so that the control circuit can control the charge sharing circuit to achieve optimal charge sharing between data lines by calculation, thereby achieving reduction in power consumption to the maximum.

Specifically, referring to fig. 2, an embodiment of the present invention provides a display device, including a plurality of data lines and a plurality of pixel units distributed in an array, wherein a portion of the data lines in the plurality of data lines receive signals with a first polarity, and a remaining portion of the data lines receive signals with a second polarity, and the first polarity and the second polarity are opposite, the display device further including:

a plurality of charge sharing circuits 1, each charge sharing circuit 1 being coupled to at least three adjacent target data lines of the plurality of data lines, the at least three adjacent target data lines receiving signals having the same polarity, and each target data line corresponding to one charge sharing circuit 1;

a control circuit respectively coupled to the plurality of charge sharing circuits 1 and the plurality of data lines, the control circuit to: in a scanning stage, the charge sharing circuit 1 is controlled to disconnect the coupling between any two target data lines of at least three adjacent target data lines coupled correspondingly with the charge sharing circuit, and first data voltage signals corresponding to the pixel units of the current scanning row are loaded to the at least three adjacent target data lines; in the charge sharing stage, a target control signal is obtained according to a first data voltage signal and a second data voltage signal corresponding to a pixel unit of a next scanning line, and according to the target control signal, the charge sharing circuit 1 is controlled to conduct coupling between at least two target data lines of at least three adjacent target data lines coupled correspondingly to the charge sharing circuit, so that the first data voltage signal is converted into a shared data voltage signal closest to the second data voltage signal and loaded on the at least three adjacent target data lines.

Specifically, the first polarity and the second polarity may correspond to a positive polarity and a negative polarity, respectively, that is, when the display device is controlled to display, a positive data voltage signal may be written to some data lines in the display device, and a negative data voltage signal may be written to the remaining data lines.

The charge sharing circuit 1 is coupled to at least three adjacent target data lines of the plurality of data lines, and can control the on-off relationship between any two target data lines of the at least three adjacent target data lines. It is to be noted that the at least three adjacent target data lines receive signals with the same polarity, and thus when at least two target data lines of the at least three adjacent target data lines are connected, the at least two target data lines can implement charge sharing, that is, the at least two target data lines are loaded with the same voltage signal. In addition, each target data line can be coupled with only one charge sharing circuit 1, but not with a plurality of charge sharing circuits 1 at the same time.

The control circuit may be respectively coupled to the plurality of charge sharing circuits 1 and the plurality of data lines, and in the scanning phase, the control circuit may control the charge sharing circuit 1 to disconnect the coupling between any two target data lines of at least three adjacent target data lines coupled to the charge sharing circuit 1, so that any two target data lines of the at least three adjacent target data lines coupled to the charge sharing circuit 1 are insulated from each other, load the first data voltage signals corresponding to the pixel units of the current scanning row to the at least three adjacent target data lines, write the first data voltage signals into the pixel units of the current scanning row through the at least three adjacent target data lines, and control the current pixel unit to implement display.

In addition, the control circuit may further obtain a target control signal according to the first data voltage signal and a second data voltage signal corresponding to a pixel unit of a next scanning line in a charge sharing stage, and control the charge sharing circuit 1 to turn on coupling between at least two target data lines of at least three adjacent target data lines coupled to the charge sharing circuit according to the target control signal, so that charge sharing is implemented between the target data lines connected to each other, that is, the target data lines connected to each other have the same voltage, thereby implementing conversion of the first data voltage signal into a shared data voltage signal closest to the second data voltage signal and loading the shared data voltage signal on at least three adjacent target data lines.

It should be noted that the coupling mentioned in the embodiment of the present invention includes: electrical connections and signal connections.

The technical solution corresponding to fig. 1 and the technical solution provided by the embodiment of the present invention are simulated, and three natural diagrams (picture 1, picture 2, and picture 3) are used, and the simulation results are shown in the following table:

as can be seen from the above table, compared to the case where the scheme of fig. 1 turns on the charge sharing function and the case where the charge sharing function is turned off, the scheme of the present invention has a significant effect on the rate of reduction of power consumption when the charge sharing function is turned on. It should be noted that K in the above table represents a constant.

According to the specific structure of the display device and the operation process of the control circuit controlling the charge sharing circuit 1, the display device provided in the embodiment of the present invention is provided with a plurality of charge sharing circuits 1 and a control circuit respectively coupled to the plurality of charge sharing circuits 1 and a plurality of data lines, wherein the charge sharing circuits 1 are respectively coupled to at least three adjacent target data lines of the plurality of data lines that receive signals of the same polarity; the control circuit can control the charge sharing circuit 1 to disconnect the coupling between any two target data lines of at least three adjacent target data lines coupled with the charge sharing circuit in a scanning stage, and load first data voltage signals corresponding to the pixel units of the current scanning line on the at least three adjacent target data lines, so as to control the pixel units of the current scanning line to realize a normal display function; in the charge sharing stage, a target control signal is obtained according to a first data voltage signal and a second data voltage signal corresponding to a pixel unit of a next scanning line, and according to the target control signal, the charge sharing circuit 1 is controlled to be connected with the coupling between at least two target data lines of at least three adjacent target data lines correspondingly coupled with the charge sharing circuit 1, so that the first data voltage signal is converted into a shared data voltage signal which is closest to the second data voltage signal and is loaded on the at least three adjacent target data lines; therefore, when the next row of pixel units are scanned, the minimum data voltage signal can be written into the target data line, and the display brightness corresponding to the second data voltage signal can be displayed by the next row of pixel units, so that the power consumption is reduced to the maximum extent.

In addition, in the display device provided in the embodiment of the present invention, the control circuit may calculate the target control signal according to the first data voltage signal and the second data voltage signal corresponding to the pixel unit of the next scanning line, and then load the shared data voltage signal closest to the second data voltage signal on the target data line according to the target control signal, thereby reducing power consumption to the maximum extent.

In addition, the display device may be: the display device comprises a television, a display, a digital photo frame, a mobile phone, a tablet personal computer and any other product or component with a display function, wherein the display device further comprises a flexible circuit board, a printed circuit board, a back plate and the like.

As shown in fig. 3 and 4, in some embodiments, the control circuit provided in the above embodiments includes: the time schedule controller TCON and the source electrode driving chip SD are coupled; in the charge sharing stage, the timing controller TCON is configured to obtain a target control signal according to the first data voltage signal and a second data voltage signal corresponding to a pixel unit of a next scanning line, and transmit the target control signal to the source driver chip SD;

the source driver chip SD is configured to control the charge sharing circuit 1 to connect at least two target data lines of at least three adjacent target data lines coupled to the charge sharing circuit according to a target control signal, so that the first data voltage signal is converted into a target shared data voltage signal closest to the second data voltage signal and is loaded on the at least three adjacent target data lines.

Specifically, the display device may include a display substrate, and the timing controller TCON and the source driving chip SD may be bonded at an edge region of the display substrate. The timing controller TCON may obtain a target control signal according to the first data voltage signal and the second data voltage signal corresponding to the pixel unit of the next scanning line, and then transmit the target control signal to the source driving chip SD through the timing controller TCON and the interface on the source driving chip SD. It is noted that the above interface protocol can be defined according to actual needs, and exemplarily, as shown in the following table:

CS [0] is used to control the on/off of the charge sharing function, and after turning on the charge sharing function of the timing controller TCON and the source driver chip SD, three charge sharing modes can be selected, for example, a specific charge sharing mode is determined by CS [1], CS [2] and CS [3], where CS [1] is used to control the on/off of the line charge sharing function, i.e. the charge sharing mode shown in FIG. 1; CS 2 is used to control the on or off of the frame charge sharing function, the frame charge sharing function controls whether the charge sharing is realized between the last line of the previous frame and the first line of the next frame in the two adjacent frames; CS 3 is used to control the on/off of the pixel charge sharing function, the pixel charge sharing function is that the timing controller TCON provided by the above embodiment obtains the target control signal and transmits the target control signal to the source driving chip SD, and the source driving chip SD controls the charge sharing circuit 1 to conduct the coupling between at least two target data lines of at least three adjacent target data lines coupled correspondingly according to the target control signal, so that the first data voltage signal is converted into the target shared data voltage signal closest to the second data voltage signal and loaded on at least three adjacent target data lines.

It should be noted that if only the charge sharing function of the timing controller TCON is turned on and the charge sharing function of the source driver chip SD is turned off, the display device cannot be controlled to realize the charge sharing function.

Further, as shown in fig. 3, the timing controller TCON provided by the above embodiment may be configured to include: an arithmetic unit 20 and a first register unit 21 coupled to each other; the arithmetic unit 20 is configured to calculate, according to the first data voltage signal, a shared data voltage signal loaded on at least three adjacent target data lines in different coupling manners when at least three adjacent target data lines coupled to the charge sharing circuit 1 are coupled in different coupling manners; and obtains the target shared data voltage signal closest to the second data voltage signal among the corresponding shared data voltage signals in each coupling mode, and stores the coupling mode generation target control signal corresponding to the target shared data voltage signal in the first register unit 21; the first register unit 21 is configured to transmit a target control signal to the source driver chip SD according to a predetermined interface protocol.

Specifically, an arithmetic unit 20 may be disposed in the timing controller TCON, where the arithmetic unit 20 is capable of calculating, according to the first data voltage signal, shared data voltage signals loaded on at least three adjacent target data lines in each coupling mode when at least three adjacent target data lines coupled to the charge sharing circuit 1 are coupled in different coupling modes, and in more detail, when the at least three adjacent target data lines are coupled in different coupling modes, the obtained shared data voltage signals are different, and exemplarily, the charge sharing circuit 1 is coupled to three adjacent target data lines in a plurality of data lines, respectively, where the three adjacent target data lines include a first data line, a second data line, and a third data line arranged in sequence along a direction perpendicular to the data lines, and when the first data voltage signal includes: when the voltage is applied to the first data line with 1V, the second data line with 1V, and the third data line with 0V, in the charge sharing stage, if the second data line is connected to the third data line, and the first data line is not connected to the second data line or the third data line, the shared data voltage signal converted from the first data voltage signal includes: similarly, if the first data line is connected to the second data line and the second data line is connected to the third data line, the shared data voltage signal converted from the first data voltage signal includes: 2/3V on the first data line, 2/3V on the second data line, and 2/3V on the third data line.

The shared data voltage signals obtained correspondingly under different coupling modes are compared with a second data voltage signal used for driving the pixel units in the next row to display, so that a target shared data voltage signal closest to the second data voltage signal is obtained, and a target control signal generated by the coupling mode corresponding to the target shared data voltage signal is stored in the first register unit 21.

The timing controller TCON with the above structure can obtain the target control signal through calculation, and then send the target control signal to the source driver chip SD, so that the source driver chip SD can directly control the charge sharing circuit 1 according to the target control signal to turn on the coupling between at least two target data lines of at least three adjacent target data lines coupled to the charge sharing circuit 1, and convert the first data voltage signal into a target shared data voltage signal closest to the second data voltage signal, and load the target shared data voltage signal on at least three adjacent target data lines. Therefore, the timing controller TCON with the above structure does not need to introduce an additional module unit into the source driving chip SD, so that the structure of the source driving chip SD is simpler.

It is noted that the arithmetic unit 20 takes approximately 30 bytes of data when performing the calculation.

In some other embodiments, as shown in fig. 4, the control circuit provided in the above embodiments includes: a timing controller TCON and a source driving chip SD coupled to each other, wherein the source driving chip SD includes: a second register unit 30, a third register unit 31, a comparison unit 32 coupled to the second register unit 30 and the third register unit 31, respectively; in the charge sharing stage, the timing controller TCON is used to output an enable signal EN; the second register unit 30 is used for storing the first data voltage signal; the third register unit 31 is used for storing the second data voltage signal; based on the enable signal EN, the comparing unit 32 is configured to obtain, according to the first data voltage signal, a shared data voltage signal loaded on at least three adjacent target data lines in different coupling manners when at least three adjacent target data lines coupled to the charge sharing circuit 1 are coupled in different coupling manners; and obtaining a target shared data voltage signal closest to the second data voltage signal in the corresponding shared data voltage signals in each coupling mode, generating a target control signal in the coupling mode corresponding to the target shared data voltage signal, and controlling the charge sharing circuit 1 to conduct the coupling between at least two target data lines in at least three adjacent target data lines coupled correspondingly according to the target control signal, so that the first data voltage signal is converted into the target shared data voltage signal closest to the second data voltage signal and loaded on at least three adjacent target data lines.

Specifically, when the above-mentioned target control signal is formed by the source driving chip SD, the timing controller TCON may supply only the enable signal EN to the source driving chip SD, i.e., control the source driving chip SD by the enable signal to implement the charge sharing function. In more detail, the source driving chip SD may specifically include: a second register unit 30, a third register unit 31 and a comparison unit 32 coupled to the second register unit 30 and the third register unit 31, respectively; based on the enable signal EN provided by the timing controller TCON, the comparing unit 32 can obtain, according to the first data voltage signal stored in the second register unit 30, the shared data voltage signal loaded on at least three adjacent target data lines in different coupling manners when at least three adjacent target data lines coupled to the charge sharing circuit 1 are coupled to each other in different coupling manners; and obtains the target shared data voltage signal closest to the second data voltage signal stored in the third register unit 31 among the corresponding shared data voltage signals in each coupling mode, generates a target control signal according to the coupling mode corresponding to the target shared data voltage signal, and controls the charge sharing circuit 1 to conduct the coupling between at least two target data lines of at least three adjacent target data lines correspondingly coupled thereto according to the target control signal, so that the first data voltage signal is converted into the target shared data voltage signal closest to the second data voltage signal and loaded on the at least three adjacent target data lines.

According to the specific structure of the control circuit provided in the above embodiment, when at least three adjacent target data lines coupled to the charge sharing circuit 1 are coupled in different coupling manners, the shared data voltage signals loaded on the at least three adjacent target data lines in each coupling manner are calculated; and in obtaining the corresponding shared data voltage signal in each coupling mode, the process of obtaining the target shared data voltage signal closest to the second data voltage signal stored in the third register unit 31 may be completed in the timing controller TCON or the source driver chip SD according to actual needs.

In order to more clearly illustrate the specific structure and operation of the charge sharing circuit 1 provided in the above embodiment, the following description takes as an example that the charge sharing circuit 1 is respectively coupled to three adjacent target data lines of a plurality of data lines, as shown in fig. 2, where the three adjacent target data lines include a first data line, a second data line and a third data line sequentially arranged along a direction perpendicular to the data lines, and the charge sharing circuit 1 includes: a first control sub-circuit 11, a second control sub-circuit 12 and a third control sub-circuit 13; the first control sub-circuit 11 is respectively coupled to a first control terminal ctr1, a first data line and a third data line in the control circuit, and is configured to control to turn on or turn off the coupling between the first data line and the third data line under the control of the first control terminal ctr 1; the second control sub-circuit 12 is respectively coupled to a second control terminal ctr2, a first data line and a second data line in the control circuit, and is configured to control to turn on or off the coupling between the first data line and the second data line under the control of the second control terminal ctr 2; the third control sub-circuit 13 is coupled to a third control terminal ctr3, a second data line and a third data line in the control circuit, respectively, and is configured to control to turn on or off the coupling between the second data line and the third data line under the control of the third control terminal ctr 3. It should be noted that the first control terminal ctr1, the second control terminal ctr2 and the third control terminal ctr3 may be control ports ctr in fig. 3 and 4, an OP coupled to the data line in fig. 2 is a buffer amplifier, and a specific setting position may be a position where the OP is located in fig. 3 and 4.

Specifically, when the charge sharing circuit 1 controls the coupling relationship among the three target data lines S1, S3, and S5 coupled thereto, the following four coupling methods are included:

(1) S1 is communicated with S3, S1 is not communicated with S5, and S3 is not communicated with S5;

(2) S1 is not communicated with S3, S1 is communicated with S5, and S3 is not communicated with S5;

(3) S1 and S3 are not communicated, S1 and S5 are not communicated, and S3 and S5 are communicated;

(4) S1 and S3 are communicated, S1 and S5 are not directly communicated, and S3 and S5 are communicated.

When the charge sharing circuit 1 controls the coupling relationship among the three target data lines S2, S4 and S6 coupled thereto, the following four coupling manners are included:

(1) S2 is communicated with S4, S2 is not communicated with S6, and S4 is not communicated with S6;

(2) S2 is not communicated with S4, S2 is communicated with S6, and S4 is not communicated with S6;

(3) S2 and S4 are not communicated, S2 and S6 are not communicated, and S4 and S6 are communicated;

(4) S2 and S4 are communicated, S2 and S6 are not directly communicated, and S4 and S6 are communicated.

As can be seen from the above analysis, the charge share circuit 1 with the above structure can form 16 different coupling modes for the six adjacent data lines, and therefore, the control circuit can calculate the target shared data voltage signal closest to the second data voltage signal in the 16 different coupling modes, generate the target control signal according to the coupling mode corresponding to the target shared data voltage signal, and control the target data line through the charge share circuit 1 to implement the corresponding coupling based on the target control signal.

Further, with reference to fig. 2, the specific structures of the first control sub-circuit 11, the second control sub-circuit 12 and the third control sub-circuit 13 provided in the above embodiments are various, and in some embodiments, the first control sub-circuit 11 may include a first transistor T1, a gate of the first transistor T1 is coupled to the first control terminal ctr1, a first pole of the first transistor T1 is coupled to the first data line, and a second pole of the first transistor T1 is coupled to the third data line; the second control sub-circuit 12 includes a second transistor T2, a gate of the second transistor T2 is coupled to the second control terminal ctr2, a first pole of the second transistor T2 is coupled to the first data line, and a second pole of the second transistor T2 is coupled to the second data line; the third control sub-circuit 13 includes a third transistor T3, a gate of the third transistor T3 is coupled to the third control terminal ctr3, a first pole of the third transistor T3 is coupled to the second data line, and a second pole of the third transistor T3 is coupled to the third data line.

Specifically, the first transistor T1 can be controlled to be turned on or off by the first control terminal ctr1, so as to control to turn on or off the coupling between the first data line and the third data line; the second transistor T2 can be controlled to be turned on or off by the second control terminal ctr2, so as to control the coupling between the first data line and the second data line to be turned on or off; the third transistor T3 may be controlled to be turned on or off by the third control terminal ctr3, so as to control the coupling between the second data line and the third data line to be turned on or off.

It should be noted that the transistors can be selected from various types, and for example, P-type thin film transistors or N-type thin film transistors can be selected.

In the display device provided by the above embodiment, the operating performance of the display device can be improved by providing the signal with the first polarity to some of the data lines and providing the signal with the second polarity to the rest of the data lines, and setting the first polarity and the second polarity to be opposite. In practical applications, the partial data lines and the remaining partial data lines may be arranged according to practical requirements, and in some embodiments, odd-numbered data lines of the plurality of data lines may be arranged to receive a signal with a first polarity, even-numbered data lines of the plurality of data lines may receive a signal with a second polarity, odd-numbered data lines of the plurality of data lines are divided into a plurality of odd-numbered data line groups, the plurality of odd-numbered data line groups are sequentially arranged in a direction perpendicular to the data lines, and each odd-numbered data line group includes the three adjacent target data lines; even data lines in the plurality of data lines are divided into a plurality of groups of even data line groups, the plurality of groups of even data line groups are sequentially arranged along the direction perpendicular to the data lines, and each group of even data line groups comprises three adjacent target data lines.

Specifically, the first polarity and the second polarity may be set according to actual needs, and for example, the odd-numbered data lines of the plurality of data lines may receive signals with positive polarity, and the even-numbered data lines of the plurality of data lines may receive signals with negative polarity, so that when the display device is controlled to display, the polarities of the signals received by the pixel units in adjacent columns of the display device are opposite, thereby being more beneficial to the working performance of the display device.

As shown in fig. 2, the odd-numbered data lines of the plurality of data lines are divided into a plurality of odd-numbered data line groups, and each odd-numbered data line group includes the three adjacent target data lines; dividing even data lines in the plurality of data lines into a plurality of groups of even data line groups, wherein each group of even data line groups comprises three adjacent target data lines; the data line groups (the general names of all the odd data line groups and all the even data line groups) are in one-to-one correspondence with the charge sharing circuits 1, and each charge sharing circuit 1 controls the corresponding data line group to realize charge sharing.

An embodiment of the present invention further provides a driving method of a display device, for driving the display device provided in the above embodiment, where the driving method includes:

in the scanning stage, a control circuit in the display device controls a charge sharing circuit 1 in the display device to disconnect the coupling between any two target data lines of at least three adjacent target data lines correspondingly coupled with the charge sharing circuit, and loads first data voltage signals corresponding to pixel units of a current scanning row to the at least three adjacent target data lines;

in the charge sharing stage, the control circuit obtains a target control signal according to the first data voltage signal and a second data voltage signal corresponding to the pixel unit of the next scanning line, and controls the charge sharing circuit 1 to conduct the coupling between at least two target data lines of at least three adjacent target data lines coupled to the charge sharing circuit according to the target control signal, so that the first data voltage signal is converted into a shared data voltage signal closest to the second data voltage signal and loaded on the at least three adjacent target data lines.

Specifically, the control circuit may be coupled to the plurality of charge sharing circuits 1 and the plurality of data lines, and in the scanning phase, the control circuit may control the charge sharing circuit 1 to disconnect the coupling between any two target data lines of at least three adjacent target data lines coupled to the charge sharing circuit 1, so that any two target data lines of the at least three adjacent target data lines coupled to the charge sharing circuit 1 are insulated from each other, load the first data voltage signals corresponding to the pixel units of the current scanning row to the at least three adjacent target data lines, write the first data voltage signals into the pixel units of the current scanning row through the at least three adjacent target data lines, and control the current pixel unit to implement display.

When the display device provided by the above embodiment is driven by the driving method provided by the embodiment of the present invention, the control circuit can control the charge sharing circuit 1 to disconnect the coupling between any two target data lines of at least three adjacent target data lines coupled to the charge sharing circuit in the scanning stage, and load the first data voltage signals corresponding to the pixel units of the current scanning line to the at least three adjacent target data lines, so as to control the pixel units of the current scanning line to realize a normal display function; in the charge sharing stage, a target control signal is obtained according to a first data voltage signal and a second data voltage signal corresponding to a pixel unit of a next scanning line, and according to the target control signal, the charge sharing circuit 1 is controlled to conduct coupling between at least two target data lines of at least three adjacent target data lines coupled correspondingly to the charge sharing circuit, so that the first data voltage signal is converted into a shared data voltage signal closest to the second data voltage signal and loaded on the at least three adjacent target data lines; therefore, when the next row of pixel units are scanned, the minimum data voltage signal can be written into the target data line, and the display brightness corresponding to the second target data voltage signal can be displayed by the next row of pixel units, so that the power consumption is reduced to the maximum extent.

In addition, when the display device provided by the above embodiment is driven by the driving method provided by the embodiment of the present invention, the target control signal can be calculated by the control circuit according to the first data voltage signal and the second data voltage signal corresponding to the pixel unit of the next scanning line, and then the shared data voltage signal closest to the second data voltage signal is loaded on the target data line according to the target control signal, thereby reducing the power consumption to the maximum.

In some embodiments, when the control circuit includes the timing controller TCON and the source driving chip SD coupled to each other, and the timing controller TCON includes the algorithm unit 20 and the first register unit 21 coupled to each other, during the charge sharing phase, the operation process of the control circuit specifically includes:

the arithmetic unit 20 calculates, according to the first data voltage signal, shared data voltage signals loaded on at least three adjacent target data lines in different coupling manners when at least three adjacent target data lines coupled to the charge sharing circuit 1 are coupled in different coupling manners; and obtains the target shared data voltage signal closest to the second data voltage signal among the corresponding shared data voltage signals in each coupling mode, and stores the coupling mode generation target control signal corresponding to the target shared data voltage signal in the first register unit 21;

the first register unit 21 transmits the target control signal to the source driver chip SD according to a predetermined interface protocol.

Specifically, an arithmetic unit 20 may be disposed in the timing controller TCON, and the arithmetic unit 20 is capable of calculating, according to the first data voltage signal, the shared data voltage signals loaded on at least three adjacent target data lines in each coupling mode when at least three adjacent target data lines coupled to the charge sharing circuit 1 are coupled in different coupling modes, comparing the shared data voltage signals obtained in correspondence with the different coupling modes with the second data voltage signal for driving the next row of pixel units to display, obtaining the target shared data voltage signal closest to the second data voltage signal, and storing the coupling mode generation target control signal corresponding to the target shared data voltage signal in the first register unit 21.

When the display device with the above structure is driven by using the driving method provided in the above embodiment, the timing controller TCON can obtain the target control signal through calculation, and then send the target control signal to the source driver chip SD, so that the source driver chip SD can directly control the charge sharing circuit 1 according to the target control signal to turn on the coupling between at least two target data lines of at least three adjacent target data lines coupled to the charge sharing circuit 1, so that the first data voltage signal is converted into the target shared data voltage signal closest to the second data voltage signal, and the target shared data voltage signal is loaded on at least three adjacent target data lines. Therefore, when the display device with the structure is driven by the driving method provided by the embodiment, an additional module unit does not need to be introduced into the source driving chip SD, so that the structure of the source driving chip SD is simpler.

In some other embodiments, when the control circuit includes a timing controller TCON and a source driver chip SD coupled to each other, and the source driver chip SD includes a second register unit 30, a third register unit 31, and a comparing unit 32 coupled to the second register unit 30 and the third register unit 31, during the charge sharing phase, the working process of the control circuit specifically includes:

the time schedule controller TCON outputs an enable signal;

the second register unit 30 stores the first data voltage signal;

the third register unit 31 stores the second data voltage signal;

based on the enable signal, the comparing unit 32 obtains, according to the first data voltage signal, a shared data voltage signal loaded on at least three adjacent target data lines in each coupling mode when at least three adjacent target data lines coupled to the charge sharing circuit 1 are coupled in different coupling modes; and obtaining a target shared data voltage signal closest to the second data voltage signal in the corresponding shared data voltage signals in each coupling mode, generating a target control signal in the coupling mode corresponding to the target shared data voltage signal, and controlling the charge sharing circuit 1 to conduct the coupling between at least two target data lines in at least three adjacent target data lines coupled correspondingly according to the target control signal, so that the first data voltage signal is converted into the target shared data voltage signal closest to the second data voltage signal and loaded on at least three adjacent target data lines.

Specifically, when the display device having the above structure is driven by using the driving method provided in the above embodiment, the timing controller TCON may only provide the enable signal to the source driving chip SD, that is, the source driving chip SD is controlled by the enable signal to realize the charge sharing function. In more detail, the source driver chip SD may specifically include: a second register unit 30, a third register unit 31 and a comparison unit 32 coupled to the second register unit 30 and the third register unit 31, respectively; based on the enable signal provided by the timing controller TCON, the comparing unit 32 can obtain the shared data voltage signal loaded on at least three adjacent target data lines in different coupling manners when at least three adjacent target data lines coupled to the charge sharing circuit 1 are coupled in different coupling manners; and obtains the target shared data voltage signal closest to the second data voltage signal stored in the third register unit 31 among the corresponding shared data voltage signals in each coupling mode, generates a target control signal according to the coupling mode corresponding to the target shared data voltage signal, and controls the charge sharing circuit 1 to conduct the coupling between at least two target data lines of at least three adjacent target data lines correspondingly coupled thereto according to the target control signal, so that the first data voltage signal is converted into the target shared data voltage signal closest to the second data voltage signal and loaded on the at least three adjacent target data lines.

It should be noted that, in the present specification, all the embodiments are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, the method embodiments are substantially similar to the product embodiments and therefore are described in a relatively simple manner, and reference may be made to some descriptions of the product embodiments for relevant points.

Unless defined otherwise, technical or scientific terms used herein should have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "coupled" or "connected," and the like, are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A display device including a plurality of data lines and a plurality of pixel units distributed in an array, wherein a portion of the data lines receive signals having a first polarity, and a remaining portion of the data lines receive signals having a second polarity, the first polarity and the second polarity being opposite, the display device further comprising:

a control circuit respectively coupled to the plurality of charge-sharing circuits and the plurality of data lines, the control circuit to: in a scanning stage, controlling the charge sharing circuit to disconnect the coupling between any two target data lines of the at least three adjacent target data lines which are correspondingly coupled with the charge sharing circuit, and loading first data voltage signals corresponding to the pixel units of the current scanning row to the at least three adjacent target data lines; in a charge sharing stage, acquiring a target control signal according to the first data voltage signal and a second data voltage signal corresponding to a pixel unit of a next scanning line, and controlling the charge sharing circuit to conduct coupling between at least two target data lines of the at least three adjacent target data lines coupled correspondingly according to the target control signal, so that the first data voltage signal is converted into a shared data voltage signal closest to the second data voltage signal and loaded on the at least three adjacent target data lines;

obtaining a shared data voltage signal loaded on the at least three adjacent target data lines in each coupling mode when the at least three adjacent target data lines coupled by the charge sharing circuit are coupled in different coupling modes according to the first data voltage signal; obtaining a target shared data voltage signal which is closest to the second data voltage signal in the shared data voltage signals corresponding to the coupling modes, and generating the target control signal according to the coupling mode corresponding to the target shared data voltage signal;

the control circuit includes: the time schedule controller and the source electrode driving chip are coupled; in the charge sharing stage, the timing controller is configured to obtain a target control signal according to the first data voltage signal and a second data voltage signal corresponding to a pixel unit of a next scanning line, and transmit the target control signal to the source driver chip;

the source driving chip is used for controlling the charge sharing circuit to conduct the coupling between at least two target data lines of the at least three adjacent target data lines which are correspondingly coupled with the charge sharing circuit according to the target control signal, so that the first data voltage signal is converted into a target shared data voltage signal which is closest to the second data voltage signal and is loaded on the at least three adjacent target data lines;

the timing controller includes: the arithmetic unit and the first register unit are coupled;

2. The display device according to claim 1, wherein the control circuit comprises: the timing controller and source driver chip that couple mutually, the source driver chip includes: the device comprises a second register unit, a third register unit and a comparison unit which is respectively coupled with the second register unit and the third register unit; in the charge-sharing phase,

the time schedule controller is used for outputting an enable signal;

the second register unit is used for storing the first data voltage signal;

the third register unit is used for storing the second data voltage signal;

based on the enable signal, the comparing unit is configured to obtain, according to the first data voltage signal, shared data voltage signals loaded on the at least three adjacent target data lines in different coupling manners when the at least three adjacent target data lines coupled to the charge sharing circuit are coupled to each other in different coupling manners; and obtaining a target shared data voltage signal which is closest to the second data voltage signal in the shared data voltage signals corresponding to the coupling modes, generating the target control signal according to the coupling mode corresponding to the target shared data voltage signal, and controlling the charge sharing circuit to conduct the coupling between at least two target data lines in the at least three adjacent target data lines correspondingly coupled to the charge sharing circuit according to the target control signal, so that the first data voltage signal is converted into the target shared data voltage signal which is closest to the second data voltage signal and is loaded on the at least three adjacent target data lines.

3. The display device according to any one of claims 1 to 2, wherein when the charge share circuit is respectively coupled to three adjacent target data lines of the plurality of data lines, the three adjacent target data lines include a first data line, a second data line, and a third data line arranged in order in a direction perpendicular to the data lines,

the charge sharing circuit includes:

the first control sub-circuit is respectively coupled with a first control end in a control circuit, the first data line and the third data line and is used for controlling the connection or disconnection of the first data line and the third data line under the control of the first control end;

the second control sub-circuit is respectively coupled with a second control end in the control circuit, the first data line and the second data line and is used for controlling the connection or disconnection between the first data line and the second data line under the control of the second control end;

and the third control sub-circuit is respectively coupled with a third control end in the control circuit, the second data line and the third data line and is used for controlling the connection or disconnection of the second data line and the third data line under the control of the third control end.

4. The display device according to claim 3,

the first control sub-circuit comprises a first transistor, a gate of the first transistor is coupled to the first control terminal, a first pole of the first transistor is coupled to the first data line, and a second pole of the first transistor is coupled to the third data line;

5. The display device according to claim 3, wherein an odd-numbered data line of the plurality of data lines receives a signal having a first polarity, an even-numbered data line of the plurality of data lines receives a signal having a second polarity,

the odd-numbered data lines in the data lines are divided into a plurality of groups of odd-numbered data line groups, the plurality of groups of odd-numbered data line groups are sequentially arranged along the direction perpendicular to the data lines, and each group of odd-numbered data line groups comprises the three adjacent target data lines;

6. A driving method for a display device, for driving the display device according to any one of claims 1 to 5, the driving method comprising:

in a charge sharing stage, the control circuit obtains a target control signal according to the first data voltage signal and a second data voltage signal corresponding to a pixel unit of a next scanning line, and controls the charge sharing circuit to connect and disconnect coupling between at least two target data lines of the at least three adjacent target data lines coupled to the charge sharing circuit according to the target control signal, so that the first data voltage signal is converted into a shared data voltage signal closest to the second data voltage signal and loaded on the at least three adjacent target data lines; obtaining a shared data voltage signal loaded on the at least three adjacent target data lines in each coupling mode when the at least three adjacent target data lines coupled by the charge sharing circuit are coupled in different coupling modes according to the first data voltage signal; and obtaining a target shared data voltage signal which is closest to the second data voltage signal in the corresponding shared data voltage signals in each coupling mode, and generating the target control signal by the coupling mode corresponding to the target shared data voltage signal.

7. The driving method of the display device according to claim 6, wherein when the control circuit comprises a timing controller and a source driver chip coupled to each other, and the timing controller comprises an arithmetic unit and a first register unit coupled to each other, during the charge sharing phase, the operation process of the control circuit specifically comprises:

8. The driving method of the display device according to claim 6, wherein when the control circuit comprises a timing controller and a source driver chip coupled to each other, and the source driver chip comprises a second register unit, a third register unit, and a comparison unit coupled to the second register unit and the third register unit, respectively, in the charge sharing stage, the operation process of the control circuit specifically comprises:

the time schedule controller outputs an enable signal;

the second register unit stores the first data voltage signal;

the third register unit stores the second data voltage signal;