CN107833524B - 一种芯片、柔性显示面板及显示装置 - Google Patents
一种芯片、柔性显示面板及显示装置 Download PDFInfo
- Publication number
- CN107833524B CN107833524B CN201711138114.2A CN201711138114A CN107833524B CN 107833524 B CN107833524 B CN 107833524B CN 201711138114 A CN201711138114 A CN 201711138114A CN 107833524 B CN107833524 B CN 107833524B
- Authority
- CN
- China
- Prior art keywords
- chip
- connection
- array substrate
- connection terminals
- display panel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 239000002245 particle Substances 0.000 claims description 5
- 238000007906 compression Methods 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims description 3
- 238000003491 array Methods 0.000 claims description 2
- 241001391944 Commicarpus scandens Species 0.000 abstract description 6
- 238000002788 crimping Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 239000003292 glue Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13013—Shape in top view being rectangular or square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13014—Shape in top view being circular or elliptic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13015—Shape in top view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1451—Function
- H01L2224/14515—Bump connectors having different functions
- H01L2224/14517—Bump connectors having different functions including bump connectors providing primarily mechanical bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/1601—Structure
- H01L2224/16012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/16014—Structure relative to the bonding area, e.g. bond pad the bump connector being smaller than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/1426—Driver
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Theoretical Computer Science (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Wire Bonding (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
本发明涉及显示技术领域,特别涉及一种芯片、柔性显示面板及显示装置。该芯片包括本体以及设置于所述本体的一侧表面的多个连接端子,每个连接端子设置有用于防止产生应力集中现象的防应力集中结构。该芯片通过设置在每个连接端子的防应力集中结构,能够解决现有连接端子的边角在压接时产生应力集中而导致阵列基板的线路容易断裂的问题。
Description
技术领域
本发明涉及显示技术领域,特别涉及一种芯片、柔性显示面板及显示装置。
背景技术
柔性显示面板因具有可弯折的特点而越来越受到广大用户的青睐。在制造过程中,柔性显示面板倾向于使用轻薄、抗冲击特性良好的阵列基板。目前,采用阵列基板的显示装置包括液晶显示装置、有机电致发光显示装置和电泳显示装置。柔性显示装置可以应用于手机、智能卡、便携式计算机以及电子纸等电子装置。
现有柔性显示面板的制备工艺为:先将阵列基板固定在玻璃基板上,再进行之后的背板制作工艺,制备完成后需要将阵列基板与玻璃基板分离,再在阵列基板的背面贴附膜材(背膜)使阵列基板平整化,最后再进行切割、IC(驱动电路)等芯片的绑定工艺。
为了提高柔性显示面板的分辨率,现有柔性显示面板一般将芯片直接绑定在阵列基板上。但是,由于芯片的硬度较高,在将芯片压接于阵列基板时容易造成芯片的连接端子下陷,使阵列基板上的线路断裂。而现有芯片的连接端子一般采用长方体结构或直平行六面体结构,连接端子的边角在压接时容易产生应力集中,导致阵列基板的线路容易断裂的问题。
发明内容
本发明提供了一种芯片、柔性显示面板及显示装置,该芯片通过设置在每个连接端子的防应力集中结构,能够解决现有连接端子的边角在压接时产生应力集中而导致阵列基板的线路容易断裂的问题。
为达到上述目的,本发明提供以下技术方案:
一种芯片,包括本体以及设置于所述本体的一侧表面的多个连接端子,每个连接端子设置有用于防止产生应力集中现象的防应力集中结构。
由于上述芯片在每个连接端子上设置有用于防止产生应力集中现象的防应力集中结构,因此,在将现有芯片压接于阵列基板时,能够通过设置于每个连接端子的防应力集中结构减小芯片产生应力集中现象的概率,进而减小阵列基板因应力集中而出现线路断裂问题的概率。
因此,该芯片通过设置在每个连接端子的防应力集中结构,能够解决现有连接端子的边角在压接时产生应力集中而导致阵列基板的线路容易断裂的问题。
优选地,每个所述连接端子具有沿其长度延伸方向相对设置的第一端部和第二端部,所述防应力集中结构设置于所述第一端部和所述第二端部。
优选地,每个所述连接端子在所述本体的一侧表面的投影为平行四边形,所述防应力集中结构为设置于所述平行四边形的至少一个角的倒圆角。
优选地,所述平行四边形为矩形。
优选地,沿从所述第一端部朝向所述第二端部的方向,所述第一端部的宽度逐渐增大、且所述第二端部的宽度逐渐减小。
优选地,所述第一端部在所述本体的一侧表面的投影的外轮廓为梯形、多边形或阶梯形,且所述第二端部在所述本体的一侧表面的投影的外轮廓为梯形、多边形或阶梯形。
优选地,每个所述连接端子包括主体,沿所述主体的长度延伸方向,所述第一端部和所述第二端部相对设置于所述主体;所述第一端部朝向所述主体的一端的宽度小于或等于所述主体的宽度、且所述第二端部朝向所述主体的一端的宽度小于或等于所述主体的宽度。
优选地,所述多个连接端子阵列分布于所述芯片。
优选地,所述芯片包括驱动电路。
优选地,所述多个连接端子包括输入端子和输出端子。
优选地,所述多个连接端子还包括伪端子。
优选地,每个连接端子的长度为80μm~120μm、且宽度为5μm~15μm。
另外,本发明还提供了一种柔性显示面板,该柔性显示面板包括阵列基板,所述阵列基板设置有多个接垫,该柔性显示面板还包括如上述技术方案提供的任意一种芯片,所述多个连接端子与所述多个接垫一一对应连接,用于使所述芯片安装于所述阵列基板。
优选地,所述芯片通过热压工艺安装于所述阵列基板,以使相互对应的连接端子和接垫电连接。
优选地,相互对应的所述连接端子和所述接垫之间设置有导电粒子胶。
优选地,每个接垫与对应的连接端子相对的表面的外轮廓形状为平行四边形。
优选地,在相互对应的接垫和连接端子中,所述连接端子在所述阵列基板上的投影全部位于所述接垫在所述阵列基板上的投影中。
本发明还提供了一种显示装置,该显示装置包括如上述技术方案提供的任意一种柔性显示面板。
与现有技术相比,本发明具有以下有益效果:
本发明提供了一种芯片、柔性显示面板及显示装置,该显示装置包括上述柔性显示面板,该柔性显示面板包括上述芯片;该芯片的每个连接端子设置有用于防止产生应力集中现象的防应力集中结构,并通过防应力集中结构减小芯片产生应力集中现象的概率,进而解决现有连接端子的边角在压接时产生应力集中而导致阵列基板的线路容易断裂的问题。
附图说明
图1为本发明一种实施例提供的柔性显示面板的结构示意图;
图2为图1中提供的柔性显示面板的阵列基板的结构示意图;
图3a为图2中阵列基板的A部分的一种局部放大示意图;
图3b为图2中阵列基板的A部分的另一种局部放大示意图;
图3c为图2中阵列基板的A部分的另一种局部放大示意图;
图4为图1中提供的柔性显示面板中芯片的连接端子的结构示意图;
图5a-5e为图4中芯片的B部分的多种局部放大示意图;
图6为芯片安装于阵列基板时连接端子与接垫的连接结构示意图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
本发明实施例提供了一种芯片、柔性显示面板及显示装置,该显示装置包括柔性显示面板,该柔性显示面板包括上述芯片;该芯片的每个连接端子设置有用于防止产生应力集中现象的防应力集中结构,并通过防应力集中结构减小芯片产生应力集中现象的概率,进而解决现有连接端子的边角在压接时产生应力集中而导致阵列基板的线路容易断裂的问题。
其中,请参考图1和图4,本发明一种实施例提供的芯片2,该芯片2包括本体21以及设置于本体21的一侧表面的多个连接端子22,每个连接端子22设置有用于防止产生应力集中现象的防应力集中结构223。
如图1结构所示,芯片2和电路板3均可以安装于阵列基板1上,芯片2可以包括驱动电路;如图4结构所示,为了方便芯片2与阵列基板1之间的信号传输,芯片2在朝向阵列基板1的一侧表面设置有多个连接端子22,如图2结构所示,阵列基板1在朝向芯片2的一侧表面设置有多个接垫11,通过连接端子22安装于阵列基板1的接垫11上且信号连接,以实现芯片2的信号输出到阵列基板1,并将阵列基板1的信号输出到芯片2。为防止因在连接端子22安装于接垫11时产生应力集中现象导致阵列基板1或芯片2损坏的问题出现,每个连接端子22设置有防应力集中结构223,如图5a结构所示,在每个连接端子22的第一端部221和第二端部222设置的防应力集中结构223为倒圆角,即,将每个连接端子22的直角边进行倒圆角,防止因直角边的存在而产生应力集中,进而损坏阵列基板1或芯片2;如图5b和图5c结构所示,每个连接端子22的第一端部221和第二端部222均制成圆弧形结构,采用圆滑过渡的弧形边形成防应力集中结构223;如图5d结构所示,对每个连接端子22的第一端部221和第二端部222的直角边进行倒角处理,采用倒角形成防应力集中结构223,进而采用倒角形成的斜边取代直角边而减少直角边的存在;如图5d结构所示,在每个连接端子22的第一端部221和第二端部222分别设置渐变结构,使第一端部221和第二端部222的尺寸由端部朝向本体21逐渐增大,进而使应力逐渐减小而防止出现应力集中现象。
由于上述芯片2在每个连接端子22上设置有用于防止产生应力集中现象的防应力集中结构223,因此,在将现有芯片2压接于阵列基板1时,能够通过设置于每个连接端子22的防应力集中结构223减小芯片2产生应力集中现象的概率,进而减小阵列基板1因应力集中而出现线路断裂问题的概率。
因此,该芯片2通过设置在每个连接端子22的防应力集中结构223,能够解决现有连接端子22的边角在压接时产生应力集中而导致阵列基板1的线路容易断裂的问题。
一种具体的实施方式中,如图5a-5e结构所示,每个连接端子22具有沿其长度延伸方向相对设置的第一端部221和第二端部222,防应力集中结构223设置于第一端部221和第二端部222。
具体地,如图5a、图5b和图5c结构所示,每个连接端子22在本体21的一侧表面的投影可以为平行四边形,防应力集中结构223可以为设置于平行四边形的至少一个角的倒圆角。每个连接端子22在本体21的一侧表面的投影的平行四边形可以为矩形。
当每个连接端子22在本体21的一侧表面的投影为矩形时,即,每个连接端子22为长方体结构。但是,每个连接端子22的具体结构可以为长方体,也可以为正方体,还可以为圆柱体、多边形体等结构,并不限于上述提到的长方体或平行四边形体结构。芯片2的多个连接端子22中可以包括长方体结构的连接端子22、平行四边形体结构的连接端子22、圆柱体结构的连接端子22和多边形体结构的连接端子22中的任意一种或任意组合。
如图5a-5e结构所示,沿从第一端部221朝向第二端部222的方向,第一端部221的宽度逐渐增大、且第二端部222的宽度逐渐减小。
由于第一端部221和第二端部222的宽度逐渐变化,因此,在将连接端子22安装于阵列基板1时,能够使连接端子22与阵列基板1上的接垫11之间的接触压力逐渐变化,而不会急剧增大导致应力集中现象的出现。
如图5d和图5e结构所示,第一端部221在本体21的一侧表面的投影的外轮廓为梯形、多边形或阶梯形,且第二端部222在本体21的一侧表面的投影的外轮廓为梯形、多边形或阶梯形。
每个连接端子22可以包括主体,沿主体的长度延伸方向,第一端部221和第二端部222相对设置于主体;第一端部221朝向主体的一端的宽度小于或等于主体的宽度、且第二端部222朝向主体的一端的宽度小于或等于主体的宽度。
如图4结构所示,多个连接端子22可以阵列分布于芯片2。多个连接端子22也可以沿芯片2的一个方向成直线排列在芯片2的一侧表面上,也可以将多个连接端子22分设在芯片2的一侧表面的多个区域;尤其当多个连接端子22包括输入端子和输出端子时,输入端子和输出端子可以相对设置在芯片2一侧表面的两个区域,也可以相邻设置;当多个连接端子22包括输入端子、输出端子和伪端子时,输入端子、输出端子和伪端子可以分别设置在芯片2的一侧表面的不同区域,也可以分别成行或成列设置,如,成三行或三列并行排列在芯片2的一侧表面;多个连接端子22也可以根据具体情况采用其它的分布形式进行设置,并不限于阵列分布。输入端子、输出端子以及伪端子的具体数量、分布形式可以根据实际需要进行设置。
如图5a结构所示,在制造过程中,每个连接端子22的长度L可以为80μm~120μm、且宽度W可以为5μm~15μm,如:长度可以为80μm、90μm、95μm、100μm、105μm、110μm、120μm,宽度可以为5μm、8μm、10μm、12μm、15μm。
在上述芯片2的各种实施例的基础上,在芯片2的实际设计和应用过程中,在同一个芯片2上的多个连接端子22中,可以部分或全部采用上述连接端子22,也可以根据应力分布的情况,对连接端子22、及其第一端部221和第二端部222的宽度等参数进行具体设计,即使同一个芯片2上的连接端子22均采用上述实施例中的结构,同一个芯片2上各连接端子22中的第一端部221和第二端部222的设计结构也可以不同、且不局限于上述各种实施例。
另外,本发明实施例还提供了一种柔性显示面板,如图1、图2、图3a、图3b以及图3c结构所示,该柔性显示面板包括阵列基板1,阵列基板1设置有多个接垫11,该柔性显示面板还包括如上述实施例提供的任意一种芯片2,多个连接端子22与多个接垫11一一对应连接,用于使芯片2安装于阵列基板1。如图2结构所示,阵列基板1设置有多个接垫11,接垫11可以用于连接芯片2和/或电路板3,多个接垫11至少能够与芯片2的连接端子22一一对应,当然,还可以设置有能够与柔性电路板等电路板3一一对应连接的接垫11。
在将芯片2安装于阵列基板1时,芯片2可以通过热压工艺安装于阵列基板1,以使相互对应的连接端子22和接垫11电连接,以使阵列基板1与芯片2和电路板3之间能够进行通信。
为了提高连接强度以及保护连接端子22和接垫11,在相互对应的连接端子22和接垫11之间可以设置有导电粒子胶。
通过设置在连接端子22和接垫11之间的导电粒子胶既可以提高阵列基板1与芯片2之间的连接强度,还可以将连接端子22和接垫11密封在导电粒子胶内,能够保护连接端子22和接垫11防止被损坏或水汽侵蚀,进而保护阵列基板1和芯片2,提高柔性显示面板的使用寿命。
如图3a、图3b和图3c结构所示,每个接垫11与对应的连接端子22相对的表面的外轮廓形状可以为平行四边形,且图3a中结构所示的接垫11的外轮廓形状为矩形,同理,为了防止应力集中的现象发生,同样可以对接垫11的直角边进行倒圆角处理,倒圆角处理后的接垫11外轮廓形状如图3b所示。
为了提高芯片2与阵列基板1之间的连接可靠性,如图6结构所示,在相互对应的接垫11和连接端子22中,连接端子22在阵列基板1上的投影全部位于接垫11在阵列基板1上的投影中。
由于连接端子22在阵列基板1上的投影全部位于接垫11在阵列基板1上的投影中,当将芯片2的连接端子22安装于阵列基板1的接垫11上时,能够使连接端子22容易地与接垫11对位,能够缩短连接端子22与接垫11之间的对位时间,提高芯片2的安装效率。
在实际生产、制造过程中,连接端子22在阵列基板1上的投影也可以部分位于接垫11在阵列基板1上的投影中。
本发明实施例还提供了一种显示装置,该显示装置包括如上述实施例提供的任意一种柔性显示面板。该显示装置可以为柔性显示装置,可以用于显示器、手机、平板电脑、电子书等领域。
显然,本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (16)
1.一种芯片,包括本体以及设置于所述本体的一侧表面的多个连接端子,其特征在于,每个连接端子设置有用于防止产生应力集中现象的防应力集中结构;
每个所述连接端子具有沿其长度延伸方向相对设置的第一端部和第二端部,所述防应力集中结构设置于所述第一端部和所述第二端部;
每个所述连接端子在所述本体的一侧表面的投影为平行四边形,所述防应力集中结构为设置于所述平行四边形的至少一个角的倒圆角。
2.根据权利要求1所述的芯片,其特征在于,所述平行四边形为矩形。
3.根据权利要求1所述的芯片,其特征在于,沿从所述第一端部朝向所述第二端部的方向,所述第一端部的宽度逐渐增大、且所述第二端部的宽度逐渐减小。
4.根据权利要求3所述的芯片,其特征在于,所述第一端部在所述本体的一侧表面的投影的外轮廓为梯形、多边形或阶梯形,且所述第二端部在所述本体的一侧表面的投影的外轮廓为梯形、多边形或阶梯形。
5.根据权利要求4所述的芯片,其特征在于,每个所述连接端子包括主体,沿所述主体的长度延伸方向,所述第一端部和所述第二端部相对设置于所述主体;所述第一端部朝向所述主体的一端的宽度小于或等于所述主体的宽度、且所述第二端部朝向所述主体的一端的宽度小于或等于所述主体的宽度。
6.根据权利要求1-5任一项所述的芯片,其特征在于,所述多个连接端子阵列分布于所述芯片。
7.根据权利要求6所述的芯片,其特征在于,所述芯片包括驱动电路。
8.根据权利要求1-7任一项所述的芯片,其特征在于,所述多个连接端子包括输入端子和输出端子。
9.根据权利要求8所述的芯片,其特征在于,所述多个连接端子还包括伪端子。
10.根据权利要求1-9任一项所述的芯片,其特征在于,每个连接端子的长度为80μm~120μm、且宽度为5μm~15μm。
11.一种柔性显示面板,包括阵列基板,所述阵列基板设置有多个接垫,其特征在于,还包括如权利要求1-10任一项所述的芯片,所述多个连接端子与所述多个接垫一一对应连接,用于使所述芯片安装于所述阵列基板。
12.根据权利要求11所述的柔性显示面板,其特征在于,所述芯片通过热压工艺安装于所述阵列基板,以使相互对应的连接端子和接垫电连接。
13.根据权利要求12所述的柔性显示面板,其特征在于,相互对应的所述连接端子和所述接垫之间设置有导电粒子胶。
14.根据权利要求11所述的柔性显示面板,其特征在于,每个接垫与对应的连接端子相对的表面的外轮廓形状为平行四边形。
15.根据权利要求14所述的柔性显示面板,其特征在于,在相互对应的接垫和连接端子中,所述连接端子在所述阵列基板上的投影全部位于所述接垫在所述阵列基板上的投影中。
16.一种显示装置,其特征在于,包括如权利要求11-15任一项所述的柔性显示面板。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201711138114.2A CN107833524B (zh) | 2017-11-16 | 2017-11-16 | 一种芯片、柔性显示面板及显示装置 |
US16/122,035 US10651141B2 (en) | 2017-11-16 | 2018-09-05 | Chip, flexible display panel and display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201711138114.2A CN107833524B (zh) | 2017-11-16 | 2017-11-16 | 一种芯片、柔性显示面板及显示装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107833524A CN107833524A (zh) | 2018-03-23 |
CN107833524B true CN107833524B (zh) | 2023-11-14 |
Family
ID=61651714
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201711138114.2A Active CN107833524B (zh) | 2017-11-16 | 2017-11-16 | 一种芯片、柔性显示面板及显示装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10651141B2 (zh) |
CN (1) | CN107833524B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112616244B (zh) * | 2020-12-22 | 2022-03-22 | 浙江清华柔性电子技术研究院 | 柔性电路板及柔性电路板制备方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10301503A (ja) * | 1997-04-23 | 1998-11-13 | Fujitsu Ltd | 平面表示装置及びその製造方法 |
CN101640318A (zh) * | 2008-07-31 | 2010-02-03 | 雅马哈发动机株式会社 | 电线端子连接器 |
JP2012133933A (ja) * | 2010-12-20 | 2012-07-12 | Panasonic Corp | フレキシブル基板、半導体装置、およびこれを用いた画像表示装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI414218B (zh) * | 2005-02-09 | 2013-11-01 | Ngk Spark Plug Co | 配線基板及配線基板內建用之電容器 |
JP5186344B2 (ja) * | 2008-12-01 | 2013-04-17 | パナソニック株式会社 | チップを有する半導体装置 |
JP2013175509A (ja) * | 2012-02-23 | 2013-09-05 | Renesas Electronics Corp | 半導体装置の製造方法 |
JP6715052B2 (ja) * | 2016-03-25 | 2020-07-01 | デクセリアルズ株式会社 | 接続構造体の製造方法 |
KR102638304B1 (ko) * | 2016-08-02 | 2024-02-20 | 삼성디스플레이 주식회사 | 표시장치 |
-
2017
- 2017-11-16 CN CN201711138114.2A patent/CN107833524B/zh active Active
-
2018
- 2018-09-05 US US16/122,035 patent/US10651141B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10301503A (ja) * | 1997-04-23 | 1998-11-13 | Fujitsu Ltd | 平面表示装置及びその製造方法 |
CN101640318A (zh) * | 2008-07-31 | 2010-02-03 | 雅马哈发动机株式会社 | 电线端子连接器 |
JP2012133933A (ja) * | 2010-12-20 | 2012-07-12 | Panasonic Corp | フレキシブル基板、半導体装置、およびこれを用いた画像表示装置 |
Also Published As
Publication number | Publication date |
---|---|
US10651141B2 (en) | 2020-05-12 |
CN107833524A (zh) | 2018-03-23 |
US20190148319A1 (en) | 2019-05-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN110579917B (zh) | 显示模组及显示装置 | |
WO2018176545A1 (zh) | 显示模组及终端 | |
CN107799561B (zh) | 显示装置 | |
US9713249B2 (en) | Chip on film flexible circuit board and display device | |
US7929101B2 (en) | Flexible display panel having particular anisotropic conductive film | |
CN110673409B (zh) | 液晶显示模组 | |
CN110596922B (zh) | 一种显示面板及显示装置 | |
CN108831299B (zh) | 一种显示面板、显示模组及电子装置 | |
CN108471671B (zh) | 柔性电路板的绑定结构及绑定方法与柔性器件 | |
KR102413480B1 (ko) | 표시 장치 및 이의 제조 방법 | |
CN108718481B (zh) | 一种引脚结构及显示面板的绑定结构 | |
US20230213815A1 (en) | Display module and manufacturing method thereof, and mobile terminal | |
KR101000455B1 (ko) | 구동 칩 및 이를 갖는 표시장치 | |
US10726753B2 (en) | Array substrate and array substrate testing structure | |
CN110636688B (zh) | 柔性显示装置 | |
KR20170005254A (ko) | 디스플레이 장치 | |
CN107833524B (zh) | 一种芯片、柔性显示面板及显示装置 | |
US11874568B2 (en) | Display panel and display device | |
US20160345436A1 (en) | Circuit board, manufacturing method thereof and display apparatus | |
CN207489366U (zh) | 一种芯片、柔性显示面板及显示装置 | |
US11947227B2 (en) | Display device | |
CN209911701U (zh) | 显示面板和显示设备 | |
CN112135467A (zh) | 焊接结构和显示模组 | |
KR20010012979A (ko) | 압착 접속 기판, 액정장치 및 전자기기 | |
CN101539690A (zh) | 基板电极结构及使用其与驱动元件的接合结构 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |