CN107818983A - A kind of marker graphic and forming method thereof - Google Patents
A kind of marker graphic and forming method thereof Download PDFInfo
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- CN107818983A CN107818983A CN201710740889.0A CN201710740889A CN107818983A CN 107818983 A CN107818983 A CN 107818983A CN 201710740889 A CN201710740889 A CN 201710740889A CN 107818983 A CN107818983 A CN 107818983A
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- marker graphic
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- 239000003550 marker Substances 0.000 title claims abstract description 76
- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000005530 etching Methods 0.000 claims abstract description 19
- 238000003475 lamination Methods 0.000 claims abstract description 14
- 230000002093 peripheral effect Effects 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 10
- 230000001360 synchronised effect Effects 0.000 claims description 4
- 238000002360 preparation method Methods 0.000 abstract description 10
- 230000008859 change Effects 0.000 abstract description 9
- 238000005516 engineering process Methods 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000005520 cutting process Methods 0.000 abstract description 2
- 230000015654 memory Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 238000012544 monitoring process Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 238000013461 design Methods 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
A kind of forming method of the marker graphic for 3D NAND steps is provided, it is characterised in that：Marker graphic is synchronously formed at N O laminations with top selection grid (TSG) figure by a mask etching, and the marker graphic formed is bulge-structure.The marker graphic is formed in peripheral stepped area, and is formed in TSG graphics pad corner regions.By the way that indicia patterns are incorporated into the preparation technology of TSG figures, the step of reducing whole step technique, reduce 3D NAND manufacturing cost, solve the problems, such as that big step cutting pattern change in size and alignment (overlay) can not be measured in step technique, while can reflect that big mesa sidewall pattern and inclination angle correspond to the change of different etching number indirectly.
Description
Technical field
The present invention relates to a kind of manufacture method of 3D nand memories, more particularly to the step of 3D nand memories to form
Marker graphic of monitoring and forming method thereof.
Background technology
3D nand memories are a kind of technologies for stacking data cell, can realize more than 32 layers, or even 72 numbers of plies at present
According to the stacking of unit.3D nand memories overcome the limitation of the true extension limit of plane nand flash memory, further increase
Memory capacity, the carrying cost of each data bit is reduced, reduces energy consumption.
The stepped area (Staircase) of 3D nand memories at present, by etching M N-O lamination shape to a peripheral step
Into one big step (wherein M is the natural number more than 1), now the part that is not etched at corresponding center is as a step pad
(Pad), then to the step pad using trim-etch techniques M step is formed.By multiple similar technique, and then form step
Structure.As shown in figure 1, is formed by 2 big steps, is formed respectively respectively by 2 etchings for the N-O laminations 200 on substrate 100
Step pad 1 and step pad 2, ultimately form ledge structure by 3 trim-etch techniques respectively.If Fig. 1 (a) is on substrate 100
N-O laminations 200 carry out big step etching for the first time, once etch 4 layers of N-O laminations, form step pad 1 (Pad 1), Ran Houtong
Cross first time trim-etch technique and form ledge structure 210；Big second step etching is being carried out, is forming (the Pad of step pad 20
2) ledge structure 220, is formed by second of trim-etch technique；Step-edge Junction is formed by third time trim-etch techniques again
Structure.
In the preparation of 3D nand memories technique, the accurately control of stepped area position is particularly important.First step
Scaled will influence the width of the high-rise step formed after trim, and grid and metal in the step array of part can be made when serious
The connection of contact is offset.With the increase of the 3D nand memory step numbers of plies, the monitoring of step size and position encounters
Challenge, major problem is that：(1) size of stepped area is mm ranks, and the yardstick that it is scaled is nm ranks, can not use CD
SEM boards enter good survey on line；(2) formation of part step spreads glue by thick photoresistance, is formed by trim-etch techniques, and thick
Photoresistance when causing the good survey of lithography step can not vernier focusing, produce and can not measure so as to have big skew (overlay)；
(3) during step is formed from high to low, the stepped area by photoresistance protection pattern and is not inclined during multiple etching
Angle can change, and the mechanism of this change lacks effective model and further investigation.
In order to solve the above problems, at present in 3D nand memories manufacturing process, after N-O thin film depositions terminate, step
Before prepared by structure, the little groove structure of symmetric arrays is first prepared on N-O films as indicia patterns 221.In the method,
The formation of its indicia patterns 222 needs an extra mask specifically created, the mask of the indicia patterns 222 as shown in Fig. 2 (a)
Figure.In Fig. 2 (a), dotted line frame represents the forming position of step pad in subsequent technique.By measuring SS Pad both sides and little groove
The distance between center line of indicia patterns 221 average value, can calculate pad critical size scaling size, such as Fig. 2 (b) institutes
Show, wherein SS Pad represent the step pad that the big step of any one in technical process is formed.This scheme can effective detection step
Scale value under the relatively different photoetching energy of pad and focal length, but the preparation of little groove needs an extra mask, Yi Jixiang
The photoetching answered, dry etching, wet-cleaning three step process, add production cost.In addition, in the trim works of multiple tracks stepped
In the debugging of skill, when big step edge and little groove Edge Distance are close, the anchor point of good survey is easy to malfunction.In addition, step
After the photo etching process optimization of pad, to small-sized groove structure, preparation technology is anti-rather than optimum value, therefore recessed
Inside has residue because N-O film etch rates are different during Slot shaping, so as to influence good survey precision.
The content of the invention
It is new by designing present applicant proposes a kind of forming method of the indicia patterns of optimization in order to solve the above problems
The small figure of type is incorporated into the preparation technology of first of step as indicia patterns, and by indicia patterns, and then is realized to every
One of step critical size and the monitoring of skew (overlay), while the big mesa sidewall of indirect monitoring is after multiple etching technique
Change.
Designed by new indicia patterns, the step of reducing whole step technique, reduce being manufactured into for 3D NAND
This, solves the problems, such as that big step cutting pattern can not measure skew (overlay).In addition, the indicia patterns of diverse location are in step
The number being etched in technique is different, is observed, can reflected indirectly with section by critical size (CD) monitoring to its own
Big mesa sidewall pattern and inclination angle correspond to the change of different etching number.
The purpose of the present invention is achieved through the following technical solutions.
A kind of forming method of the marker graphic for 3D NAND steps is provided, comprised the following steps：Substrate, tool are provided
There are N-O laminations disposed thereon, N-O laminations include being used for the external stairs for the central area and formation interconnection for forming raceway groove through hole
Region；A mask is provided, by once etching selection grid (TSG) graphics pad and marker graphic at the top of synchronous formed.
Wherein, marker graphic is bulge-structure.
Wherein, marker graphic is used for the step pad for monitoring TSG graphics pads and the step for forming external stairs region
Scaling and skew.
A kind of 3DNAND memory devices, including substrate, the N-O laminations formed on substrate are provided, the N-O laminations include using
In the central area for forming raceway groove through hole and for forming the external stairs region interconnected；Top selection grid (TSG) graphics pad, its
Cover central area；Marker graphic, formed in peripheral stepped area；It is characterized in that：The marker graphic is bulge-structure.
Further, the marker graphic is formed with TSG figures by the way that a mask is synchronous, and the mark near TSG step pads
Remember that figure and TSG step pads are contour.
Further, the sides aligned parallel of the edge of marker graphic and step pad.
Further, the indicia patterns are formed in the inside/outside side of the corner regions of each step pad.
Further, per the public group echo figure of two neighboring step pad.
Further, the corner of TSG graphics pads sets marker graphic.
Further, marker graphic arranges in horizontal or vertical direction in a row or column, or marker graphic edge is different
Step pad corner extension direction arranges.
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this area
Technical staff will be clear understanding.Accompanying drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention
Limitation.And in whole accompanying drawing, identical part is denoted by the same reference numerals.In the accompanying drawings：
Fig. 1 common process schematic diagrames that ledge structure etches in the prior art.
The layout design schematic diagram of Fig. 2 (a) indicia patterns in the prior art.
The schematic diagram that Fig. 2 (b) sizes that arbitrarily pad critical size scales in the prior art measure.
The schematic diagram for marker graphic and the TSG pad that Fig. 3 (a) technique according to the invention scheme is formed.
Fig. 3 (b) according to the present invention marker graphic mask design scheme schematic diagram.
Fig. 4 technique according to the invention schemes survey calculation pads scaling critical size and the schematic diagram of offset.
The schematic diagram of the design of Fig. 5 marker graphic masks according to an embodiment of the invention.
The schematic diagram of the design of Fig. 6 marker graphic masks in accordance with another embodiment of the present invention.
Embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although this public affairs is shown in accompanying drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.Conversely, there is provided these embodiments are to be able to be best understood from the disclosure, and can be by this public affairs
The scope opened completely is communicated to those skilled in the art.
According to the embodiment of the present invention, a kind of marker graphic forming method is proposed, N-O lamination knots are formed on substrate
Structure, the ledge structure of top is subsequently formed, the step of general top is referred to as top selection grid (TSG), what it was formed
Pad as TSG graphics pads (TSG Pad) 311.When forming TSG graphics pads 311, marker graphic 321 and TSG graphics pads 311 are synchronous
Formed, obtain the structure such as Fig. 3 (a).In the forming method of the marker graphic 321, by the mask graph 322 of marker graphic 321
Formed with TSG mask graphs 312 in former ledge structure technique in a mask, Fig. 3 (b) shows the mask artwork of mask
The schematic diagram of case.Preparation process with TSG steps terminates, and marker graphic 321 turns into the projection of the symmetric arrays on N-O substrates
Structure, as shown in Fig. 3 (a).
In Fig. 3 (b), in region 1 (Area 1), marker graphic mask 322 near TSG graphics pad masks will be formed with
The contour marker graphic 321 of TSG graphics pads 311, for monitoring scaling and the skew (overlay) of TSG graphics pads 311.In area
In domain 2 (Area 2), marker graphic 322 is symmetrically arranged amongst step pad 1 (Pad 1), step pad 2 (Pad 2), step pad 3 successively
Four corners on the outside of (Pad 3) and step pad 4 (Pad 4) step version.(the Pad of step pad 1 formed in Fig. 3 (b) using dotted line
1), step pad 2 (Pad 2), step pad 3 (Pad 3) and step pad 4 (Pad 4) step version are only used for as the position of marker graphic 322
Put and refer to, it represents the step version used in follow-up technical process, and has above-mentioned not on current domain
Rank pads 1-4 layout patterns.With reference to figure 2 (b), each step pad of difference (represents TSG Pad, Pad 1, Pad with SS Pad here
2nd, any one in Pad 3 and Pad 4) edge and the center line of raised marker graphic 321 distance, can monitor each
The scaling of the big step in road and skew (overlay).In addition, the marker graphic 322 in region 2 is arranged in one directly on x/y directions
On line, it is easy to during section observation while monitors the pattern of mark structure under different etching number.
The scaling that each big step etches the step pad to be formed can calculate acquisition by following method, with reference to shown in figure 4.
Designed in mask graph, i.e., in layout design, it is 2c to define the distance between two center lines of marker graphic 422, is tested
The length of any step pad (SS PAd) 412 be 2a, its to the distance between center line of marker graphic 422 or so be respectively L0, R0, mark
Note figure 422 is symmetrically distributed in the both sides of step pad 412, then there is L0=R0=c-a.Because mask plate error effects, grade are big
Critical size of the small step pad 412 after photoetching has nano level difference with layout design value.It is likewise, wide for micron order
The marker graphic 422 of degree, the critical size after photo etching process forms structure also have nano level scaling.In step
In technique, due to the high symmetry of figure, it is believed that two distances between center line of marker graphic 422 of the both sides of step pad 412
2c remains constant in step preparation technology.
To step preparation process, it will be assumed that the size and location migration model of step pad 412 is as follows：(1) marker graphic 422
Itself offsets x in a photolithographic process0；(2) pad offsets x in a photolithographic process1；(3) critical dimension reduction in a photolithographic process is padded
2a-2b.Then there is L=L0-x0+x1+a-b；R=R0+x0-x1+a-b.Comprehensive to understand, the critical size shrinkage value of pad is L+R-
(L0+R0)；The offset value x of pad1=(L-R)/2+x0.Because marker graphic 42 is hindered (about in figure preparation process using glimmer
750nm), skew can accomplish to be less than 20nm and accurate measurement in current semiconductor lithography process, therefore we can be with
Calculate change and the offset of pad of the critical size of pad indirectly in whole chip.
According to one embodiment of present invention, marker graphic and TSG graphics pads are synchronously formed, i.e. both mask graph shapes
On Cheng Yi masks, and marker graphic can be distributed in the inside/outside side of big step (step pad) corner regions to be measured.
The mask graph that marker graphic and TSG graphics pads are once formed may be designed as shown in Figure 5.Outside each big step
The outer layer of side, i.e. step pad 1-4, have for the independent marker graphic for measuring corresponding step pad, marker graphic edge and step
Pad corner edge is parallel, and marker graphic arranges along different step pad corner extension directions.Top edge such as step pad 1 is schemed with mark
Shape 522-1 sides aligned parallel, the right side edge of step pad 1 and marker graphic 522-2 sides aligned parallel；The top edge of step pad 2
With marker graphic 522-3 sides aligned parallel, the right side edge of step pad 2 and marker graphic 522-4 sides aligned parallel, with such
Push away.Dotted line is the center line of marker graphic in Fig. 5, by measuring the distance of step pad and marker graphic center line, can be extrapolated
The scaling of step critical size and skew.
On the other hand, the number that the marker graphic of different zones is etched in step technique is different.Step pad 1, step
Pad 2, step pad 3 and the marker graphic on the side of step pad 4 etch as the shaping of step pad experienced the different N-O films of number,
Marker graphic 522-1 and 522-2 such as the side of step pad 1 undergo 2 etchings, the marker graphic 522-3 and 522-4 on the side of step pad 2
3 etchings of experience, the marker graphic 522-5 and 522-6 on the side of step pad 3 undergo 4 etchings, etch the pattern form of mark as schemed
Shown in 5 (b), it is seen that as the increase of etching number, the angle of big mesa sidewall and horizontal plane are less and less.By to these marks
Remember pattern side wall detection and analysis, can prejudge in the preparation of high storehouse step afterwards, step edge multiple tracks etch to
Pattern and change of pitch angle during bottom extends, and for adjusting the value of step trim width critical sizes.
According to another embodiment of the invention, marker graphic and TSG graphics pads are synchronously formed, i.e. both mask graphs
Formed on a mask, and the public pair of marks figure of the big step of each two (step pad), and marker graphic is formed
The outer layer of the big step (step pad) of to be measured one and the inner side of next step.As shown in fig. 6, marker graphic 622-1 and
622-2 is that step pad 1 and step pad 2 are public, and it is located at the outside of step pad 1, the inner side of step pad 2；Marker graphic 622-3 and 622-
4 be that step pad 3 and step pad 4 are public, and it is located at the outside of step pad 3, the inner side of step pad 4.Marker graphic 622-1 and 622-3 into
One row arrangement, marker graphic 622-2 and 622-4 are arranged in a row.The program reduce in high storehouse step etching technics because
Damage of the multiple etching to marker graphic, it is adapted to 32 layers with up to 128 layers of staircase regime.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in,
It should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Enclose and be defined.
Claims (10)
1. a kind of forming method of marker graphic for 3D NAND steps, comprises the following steps：
Substrate is provided, there is N-O laminations disposed thereon, N-O laminations include being used for central area and the shape for forming raceway groove through hole
Into the external stairs region of interconnection；
A mask is provided, by once etching selection grid (TSG) graphics pad and marker graphic at the top of synchronous formed.
2. the forming method of the marker graphic as shown in claim 1, wherein marker graphic are bulge-structure.
3. the forming method of the marker graphic as shown in claim 1, marker graphic is used to monitor TSG graphics pads and for shape
Scaling and skew into the step pad of the step in external stairs region.
4. a kind of 3DNAND memory devices, including substrate, the N-O laminations formed on substrate, the N-O laminations include being used to be formed
The central area of raceway groove through hole and the external stairs region for forming interconnection；Top selection grid (TSG) graphics pad, during it is covered
Heart district domain；Marker graphic, formed in peripheral stepped area, it is characterised in that：The marker graphic is bulge-structure.
5. memory device as claimed in claim 3, it is characterised in that the marker graphic is same by a mask with TSG graphics pads
Step etching is formed, and the marker graphic near TSG step pads and TSG step pads are contour.
6. memory device as claimed in claim 3, it is characterised in that the edge of marker graphic and the sides aligned parallel of step pad.
7. memory device as claimed in claim 3, it is characterised in that the indicia patterns form the corner region in each step pad
The inside/outside side in domain.
8. memory device as claimed in claim 3, it is characterised in that a group echo figure is shared per two neighboring step pad.
9. memory device as claimed in claim 3, it is characterised in that the corner of TSG graphics pads is provided with marker graphic.
10. memory device as claimed in claim 3, it is characterised in that marker graphic is in a line or one in horizontal or vertical direction
Row arrangement, or marker graphic arrange along different step pad corner extension directions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710740889.0A CN107818983B (en) | 2017-08-25 | 2017-08-25 | Marking pattern and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710740889.0A CN107818983B (en) | 2017-08-25 | 2017-08-25 | Marking pattern and forming method thereof |
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| CN107818983A true CN107818983A (en) | 2018-03-20 |
| CN107818983B CN107818983B (en) | 2020-05-12 |
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| CN201710740889.0A Active CN107818983B (en) | 2017-08-25 | 2017-08-25 | Marking pattern and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109860201A (en) * | 2019-04-09 | 2019-06-07 | 长江存储科技有限责任公司 | A kind of nand memory, mask plate and production method |
| CN110494969A (en) * | 2019-06-27 | 2019-11-22 | 长江存储科技有限责任公司 | Indicia patterns in the hierarchic structure for forming three dimensional memory device |
| CN110501872A (en) * | 2019-08-13 | 2019-11-26 | 上海华虹宏力半导体制造有限公司 | For defining the mask of litho pattern sidewall profile |
| CN110783342A (en) * | 2019-11-05 | 2020-02-11 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
| CN111554688A (en) * | 2019-02-26 | 2020-08-18 | 长江存储科技有限责任公司 | Three-dimensional memory device and manufacturing method thereof |
| CN112331666A (en) * | 2020-10-29 | 2021-02-05 | 长江存储科技有限责任公司 | Three-dimensional memory and forming method thereof |
| CN112909008A (en) * | 2021-03-16 | 2021-06-04 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
| CN113035732A (en) * | 2019-06-11 | 2021-06-25 | 长江存储科技有限责任公司 | Three-dimensional memory and method for forming step area of three-dimensional memory |
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| US11545442B2 (en) | 2019-06-27 | 2023-01-03 | Yangtze Memory Technologies Co., Ltd. | Marking pattern in forming staircase structure of three-dimensional memory device |
| US11552025B2 (en) | 2019-06-27 | 2023-01-10 | Yangtze Memory Technologies Co., Ltd. | Marking pattern in forming staircase structure of three-dimensional memory device |
| US11594496B2 (en) | 2019-06-27 | 2023-02-28 | Yangtze Memory Technologies Co., Ltd. | Marking pattern in forming staircase structure of three-dimensional memory device |
| CN110494969A (en) * | 2019-06-27 | 2019-11-22 | 长江存储科技有限责任公司 | Indicia patterns in the hierarchic structure for forming three dimensional memory device |
| CN110501872A (en) * | 2019-08-13 | 2019-11-26 | 上海华虹宏力半导体制造有限公司 | For defining the mask of litho pattern sidewall profile |
| CN110783342A (en) * | 2019-11-05 | 2020-02-11 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
| CN110783342B (en) * | 2019-11-05 | 2022-08-09 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
| CN112331666A (en) * | 2020-10-29 | 2021-02-05 | 长江存储科技有限责任公司 | Three-dimensional memory and forming method thereof |
| CN112331666B (en) * | 2020-10-29 | 2021-08-31 | 长江存储科技有限责任公司 | Three-dimensional memory and forming method thereof |
| CN112909008A (en) * | 2021-03-16 | 2021-06-04 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
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