CN107808859A - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
- Publication number
- CN107808859A CN107808859A CN201610978663.XA CN201610978663A CN107808859A CN 107808859 A CN107808859 A CN 107808859A CN 201610978663 A CN201610978663 A CN 201610978663A CN 107808859 A CN107808859 A CN 107808859A
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- China
- Prior art keywords
- semiconductor structure
- insulating barrier
- line layer
- structure according
- via hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 3
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- 229910052782 aluminium Inorganic materials 0.000 claims description 3
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a semiconductor structure which comprises an insulating layer, a plurality of step-shaped through holes and a patterned circuit layer. The insulating layer includes an upper surface and a lower surface opposite to the upper surface. The stepped through holes are arranged on the insulating layer to electrically conduct the upper surface and the lower surface, wherein each stepped through hole comprises a top cover part and a connecting part connected with the top cover part. The top cover part is arranged on the upper surface, the top surface of the top cover part is coplanar with the upper surface, and the minimum diameter of the top cover part is larger than the maximum diameter of the connecting part. The patterned circuit layer is arranged on the upper surface and electrically connected with the stepped through hole. The semiconductor structure provided by the invention can improve the reliability of the semiconductor structure and effectively reduce the diameter of the through hole.
Description
Technical field
The invention relates to a kind of semiconductor structure, and in particular to a kind of partly leading with stepped via hole
Body structure.
Background technology
In recent years, with the rise with rapid changepl. never-ending changes and improvements and semiconductor industry of electronic technology so that more humane, function is more
Good electronic product is constantly weeded out the old and bring forth the new, and is designed towards light, thin, short, small trend.Due to current wafer, semiconductor
Element or circuit board are realized without the target not towards height aggregation, therefore the line width line between its internal IC
More become smaller away from then, or even arrived the grade of nanometer.However, while line width line-spacing diminishes, the size of via hole also can
It is restricted, is very big process challenge for this via hole deeper to depth.
Further, since the material of wire and via hole (such as：Copper) engagement between the dielectric material of low-k
Spend phenomenon that is less desirable, therefore producing delamination, destruction or fracture between wire and dielectric material sometimes.Also, by
Thermal coefficient of expansion (Coefficient of Thermal Expansion, CTE) between dielectric material and conductive material be present
Difference so that engagement between dielectric material and conductive material easily the destruction of thermally stressed (thermal stress) and make
Into the phenomenon of buckling deformation (warpage) or delamination (delamination), so reduce semiconductor structure reliability and
Service life.
The content of the invention
The present invention provides a kind of semiconductor structure, and it can lift the reliability of semiconductor structure and effectively reduce via hole
Diameter.
The semiconductor structure of the present invention includes the first insulating barrier, multiple first stepped via holes and the first patterned lines
Road floor.First insulating barrier includes the first lower surface of the first upper surface and relative first upper surface.First stepped via hole is set
The first insulating barrier is placed in the first upper surface and the first lower surface of electrically conducting, wherein each first stepped via hole includes top cover
Portion and the connecting portion for connecting top cover portion.Top cover portion is arranged at the first upper surface and the top surface of top cover portion is put down altogether with the first upper surface
Face, the minimum diameter of top cover portion are more than the maximum gauge of connecting portion.First patterned line layer be arranged at the first upper surface and with
First stepped via hole is electrically connected with.
In one embodiment of this invention, the bottom surface of the first above-mentioned patterned line layer is less than the first upper surface.
In one embodiment of this invention, the diameter of above-mentioned top cover portion forms vertical hole wall, connecting portion by machine drilling
Formed by laser technology.
In one embodiment of this invention, the first above-mentioned stepped via hole also includes sub- connecting portion, is connected to connection
Portion, and connecting portion is connected between top cover portion and sub- connecting portion, and the minimum diameter of connecting portion is more than the maximum of sub- connecting portion directly
Footpath.
In one embodiment of this invention, the first above-mentioned stepped via hole also includes base portion, is arranged under first
Surface, connecting portion are connected between top cover portion and base portion, and the minimum diameter of base portion is more than the maximum gauge of connecting portion.
In one embodiment of this invention, above-mentioned base portion forms vertical hole wall by machine drilling.
In one embodiment of this invention, the material of the first above-mentioned insulating barrier includes alternative galvanic insulation material, its
Including non-conductive metal composite or general usual insulation material.
In one embodiment of this invention, the material of the first above-mentioned insulating barrier includes epoxy resin, polyester, acrylic acid
Ester, fluorine element polymer, polyphenylene oxide, polyimides, phenolic resin, polysulfones, silicon element polymer, BT resins
(Bismaleimide-Triazine modified epoxy resin), cyanic acid polyester, polyethylene, polycarbonate resin, third
Alkene nitrile-BS, PET (PET), polybutylene terephthalate (PBT), liquid crystal
Macromolecule (liquid crystal polyester, LCP), polyamide (PA), nylon 6, kematal (POM), polyphenylene sulfide
Ether (PPS), polycarbonate (polycarbonate, PC), polymethyl methacrylate (polymethacrylate, PMMA),
ABS resin (Acrylonitrile Butadiene Styrene, ABS) or cyclic olefin copolymer (COC).
In one embodiment of this invention, the metal in above-mentioned non-conductive metal composite include zinc, copper, silver, gold,
Nickel, palladium, platinum, cobalt, rhodium, iridium, indium, iron, manganese, aluminium, chromium, tungsten, vanadium, tantalum, titanium or its any combination.
In one embodiment of this invention, above-mentioned semiconductor structure also includes the second insulating barrier, the second patterned circuit
Layer and multiple second stepped via holes.Second insulating barrier includes the second following table of the second upper surface and relative second upper surface
Face, the second insulating barrier are stacked on the first insulating barrier with the second lower surface.Second patterned line layer is arranged at the second upper surface.
Second stepped via hole is arranged at the second insulating barrier with the first patterned line layer and the second patterned line layer of electrically conducting.
In one embodiment of this invention, the material of the first above-mentioned insulating barrier includes silicon or glass.
In one embodiment of this invention, above-mentioned semiconductor structure also includes the first chip, including active surface and
The back side of confronting active-surface, the first insulating barrier cover the active surface and exposed backside of the first chip, the first stepped conducting
Hole is connected between the first upper surface and active surface, to be electrically connected with the first patterned line layer and the first chip.
In one embodiment of this invention, above-mentioned semiconductor structure also includes multiple soldered balls, is arranged at the first upper surface
And it is electrically connected with the first pattern lines layer.
In one embodiment of this invention, above-mentioned semiconductor structure also includes the first chip and the first redistribution circuit
Layer.First chip includes first back side of the first active surface and relative first active surface.First insulating barrier covering first
First back side of chip, and the first lower surface exposes the first active surface.First redistribution line layer is arranged at the first lower surface
And it is electrically connected with the first active surface.First stepped via hole through the first insulating barrier with connect the first patterned line layer with
First redistribution line layer.
In one embodiment of this invention, the first above-mentioned stepped via hole also includes base portion, is arranged under first
Surface, connecting portion are connected between top cover portion and base portion, and the minimum diameter of base portion is more than the maximum gauge of connecting portion.
In one embodiment of this invention, above-mentioned semiconductor structure also includes multiple soldered balls, is arranged at the first redistribution
To be electrically connected with the first chip on line layer.
In one embodiment of this invention, above-mentioned semiconductor structure also includes the second chip, the second insulating barrier, the second weight
Distribution lines layer and multiple soldered balls.Second chip includes second back side of the second active surface and relative second active surface.
Second insulating barrier includes the second lower surface of the second upper surface and relative second upper surface.Second insulating barrier covers the second chip
Second back side, and the second lower surface exposes the second active surface.Second redistribution line layer is arranged at the second lower surface and electrical
Connect the second active surface.Soldered ball is connected between the first insulating barrier and the second redistribution line layer, to be electrically connected with the first figure
Case line layer and the second redistribution line layer.
Added based on above-mentioned, of the invention semiconductor structure using laser technology at least twice or at least once machine drilling
On laser technology at least once, form stepped via hole to drill stage by stage, to reduce the depth of each laser drill, because
And the maximum gauge of stepped via hole can be reduced on the premise of the depth of stepped via hole is not reduced, and then half can be lifted
The closeness of the configuration of conductor structure.Further, since machine drilling has the advantages of quick and aperture is consistent, therefore use
Its advantage is combined with laser technology, be can reach and is saved the effect of cost is with control size.Also, the ladder that technique is formed according to this
Shape via hole has stair-stepping external form, and this stair-stepping external form can increase the engagement between stepped via hole and insulating barrier
Power, to prevent that the situation of delamination occurs between stepped via hole and insulating barrier, and then the reliability of semiconductor structure can be lifted.
For features described above of the invention and advantage can be become apparent, special embodiment below, and it is detailed to coordinate accompanying drawing to make
Carefully it is described as follows.
Brief description of the drawings
Fig. 1 is a kind of diagrammatic cross-section of semiconductor structure according to one embodiment of the invention.
Fig. 2 is a kind of diagrammatic cross-section of semiconductor structure according to one embodiment of the invention.
Fig. 3 is a kind of diagrammatic cross-section of semiconductor structure according to one embodiment of the invention.
Fig. 4 is a kind of diagrammatic cross-section of semiconductor structure according to one embodiment of the invention.
Fig. 5 is a kind of diagrammatic cross-section of semiconductor structure according to one embodiment of the invention.
Fig. 6 is a kind of diagrammatic cross-section of semiconductor structure according to one embodiment of the invention.
Drawing reference numeral explanation：
100th, 100a~e：Semiconductor structure；
110：First insulating barrier；
112：First upper surface；
114：First lower surface；
120：First stepped via hole；
122：Top cover portion；
124：Connecting portion；
126：Sub- connecting portion；
128：Base portion；
130：First patterned line layer；
140：Second insulating barrier；
142：Second upper surface；
144：Second lower surface；
150：Second stepped via hole；
160：Second patterned line layer；
170：First chip；
172、175a：Active surface；
174、175b：The back side；
175：Second chip；
180、185：Soldered ball；
190：First redistribution line layer；
195：Second redistribution line layer.
Embodiment
Fig. 1 is a kind of diagrammatic cross-section of semiconductor structure according to one embodiment of the invention.Fig. 1 is refer to, at this
In embodiment, semiconductor structure 100 includes the first insulating barrier 110, multiple first stepped via holes 120 and first pattern
Line layer 130.First insulating barrier 110 includes the first lower surface 114 of the first upper surface 112 and relative first upper surface 112.The
One stepped via hole 120 is arranged at the first insulating barrier 110 with the first upper surface 112 and the first lower surface 114 of electrically conducting.
In the present embodiment, the first stepped via hole 120 can be formed by laser drill or with reference to machine drilling with laser drill.
Generally, due to the limitation on laser technology, with the depth-width ratio (aspectratio) of laser-formed via hole
Can not be more than 3:1, in other words, the depth of via hole at most can only achieve three times of the maximum gauge of via hole；And power auger
Hole can not carry out too deep Drilling operation because intensity is size-limited.Therefore, when the depth of via hole is deeper, its maximum gauge
It will therewith increase, and then take the more space of semiconductor structure, this is just accumulated with current semiconductor element towards height circuit
The target of collectionization is disagreed.In view of this, in the present embodiment, the first stepped via hole 120 can be by laser at least twice
Bore process or at least once machine drilling are formed stage by stage plus laser technology at least once, to reduce each laser drill
Depth, thus the first stepped via hole 120 can be reduced on the premise of the depth of the first stepped via hole 120 is not shortened
Maximum gauge, and then lifted semiconductor structure 100 configuration closeness.
Therefore, the first stepped via hole 120 formed according to above-mentioned preparation method can be as shown in Figure 1 include top cover portion
122 and connect top cover portion 122 connecting portion 124.Top cover portion 122 be arranged at the first upper surface 112 of the first insulating barrier 110 and
The top surface of top cover portion 122 and the copline of the first upper surface 112.The maximum that the minimum diameter of top cover portion 122 is more than connecting portion 124 is straight
Footpath, that is to say, that top cover portion 122 and the diameter of connecting portion 124 make the first stepped via hole 120 with segment difference with ladder
The external form of shape.This stair-stepping external form can also increase the engagement between the first stepped insulating barrier 110 of via hole 120 and first
Power, to prevent that the situation of delamination occurs between the first stepped insulating barrier 110 of via hole 120 and first.
Specifically, in the present embodiment, the generation type of the first stepped via hole 120 may include first with machine drilling
Or laser is drilled into the depth of the bottom of top cover portion 122 by the first upper surface 112, then the bottom with laser by top cover portion 122 of continuing
Start drilling to the bottom (being the first lower surface 114 in the present embodiment) of connecting portion 124.Herein it should be noted that, with machinery
Drill the hole formed, and its hole wall is generally perpendicular, that is to say, that if forming top cover portion 122, its top cover with machine drilling
The top in portion 122 and the diameter of bottom can be identical, and the hole formed with laser drill is substantially in then infundibulate, that is to say, that
If the top of the top cover portion 122 and/or connecting portion 124 that are formed with laser drill, its top cover portion 122 and/or connecting portion 124
Diameter can be more than the diameter of its bottom.
In the present embodiment, the first patterned line layer 130 is arranged at the first upper surface 112 of the first insulating barrier 110, and
It is electrically connected with the first stepped via hole 120.Certainly, the first patterned line layer 130 can be arranged at the first insulating barrier simultaneously
110 the first upper surface 112 and the first lower surface 114, and the first stepped via hole 120 then can be used to two above and below electric connection
First patterned line layer 130 on surface 112,114.In the present embodiment, the material of the first insulating barrier 110 includes alternative
Galvanic insulation material or general usual insulation material, it includes non-conductive metal composite, in this way, the present embodiment is exhausted using first
The characteristic of the alternative plating of edge layer 110, directly in forming the first patterned lines as shown in Figure 1 on the first upper surface 112
Road floor 130.In the present embodiment, alternative galvanic insulation material may include epoxy resin, polyester, acrylate, fluorine element polymerization
Thing, polyphenylene oxide, polyimides, phenolic resin, polysulfones, silicon element polymer, BT resins (Bismaleimide-
Triazine modified epoxyresin), cyanic acid polyester, polyethylene, polycarbonate resin, acrylonitrile-butadiene-benzene second
Alkene copolymer, PET (PET), polybutylene terephthalate (PBT), liquid crystal polymer
(liquidcrystal polyester, LCP), polyamide (PA), nylon 6, kematal (POM), polyphenylene sulfide (PPS),
Polycarbonate (polycarbonate, PC), polymethyl methacrylate (polymethacrylate, PMMA), ABS resin
(Acrylonitrile Butadiene Styrene, ABS) or cyclic olefin copolymer (COC) etc..Non-conductive metal composite
Metal in thing then may include zinc, copper, silver, gold, nickel, palladium, platinum, cobalt, rhodium, iridium, indium, iron, manganese, aluminium, chromium, tungsten, vanadium, tantalum, titanium or
It is combined.
Specifically, optionally electroplated in the first upper surface 112 of the first insulating barrier 110 and form the first patterned lines
The step of road floor 130, may include：First pattern is formed along being intended to laser on the first upper surface 112 of the first insulating barrier 110
The path for changing line layer 130 carves the circuit groove of corresponding first patterned line layer 130, makes non-conductive in this circuit groove
Metal composite destroy and discharge to heavy metal nucleus of the reducing metalization with high activity, or by the surface coarsening in groove
It is brilliant to the kind in absorption plating solution, then, then selectivity is carried out with electroplating dielectric material to can be plated by selectivityization after laser
Plating, the first patterned line layer 130 is formed directly to change plating and plating on circuit groove.Therefore, according to above-mentioned technique institute
The first patterned line layer 130 formed can be embedded in the first upper surface 112 of the first insulating barrier 110, and the first insulating barrier 110
The first upper surface 112 expose the first patterned line layer 130 top surface.
Also, because the present embodiment is to be connected on the first upper surface 112 of the first insulating barrier 110 to carve pair using laser straight
The circuit groove of the first patterned line layer 130 is answered, directly changes plating and plating on circuit groove and forms the first patterning
Line layer 130, therefore, the bottom surface of the first patterned line layer 130 can be less than the first upper surface 112 of the first insulating barrier 110.And
And in this way directly in the lower surface of various first patterned line layers formed on the surface of the first insulating barrier 110 all
The surface of the first insulating barrier 110 can be less than.Certainly, the present embodiment is only not so limited to illustrate.
In addition, the first stepped via hole 120 also can first pass through laser twice and be formed stage by stage stair-stepping logical
Hole, recycle the first insulating barrier 110 can by selectivityization plate with plating characteristic and to this stair-stepping through hole directly change plate and
Plating, to form conduction material in stair-stepping through hole, and then complete the making of the first stepped via hole 120.Certainly, this reality
Example is applied only to for example, in other embodiments of the invention, the material of the first insulating barrier 110 is alternatively silicon or glass.
That is, the first insulating barrier 110 can be silicon substrate or glass substrate, its can for example as intermediate plate (interposer) it
With, and the first stepped via hole 120 can be then used as the via hole being for electrically connecting in silicon substrate or glass substrate.
Fig. 2 is a kind of diagrammatic cross-section of semiconductor structure according to one embodiment of the invention.In this mandatory declaration
It is that the semiconductor structure 100a and Fig. 1 of the present embodiment semiconductor structure 100 are similar, and therefore, the present embodiment continues to use foregoing implementation
The element numbers and partial content of example, wherein adopting the identical or approximate element that is denoted by the same reference numerals, and eliminate phase
With the explanation of technology contents.Explanation on clipped refers to previous embodiment, and it is no longer repeated for the present embodiment.It please join
According to Fig. 2, explained below for the difference of semiconductor structure 100a and Fig. 1 semiconductor structure 100.
In the present embodiment, in the case of the demand depth relatively depth of the first stepped via hole 120, first stepped leads
Through hole 120 may also include sub- connecting portion 126, and it is connected to connecting portion 124, and connecting portion 124 is connected to top cover portion 122 and connected with son
Between socket part 126, and the minimum diameter of connecting portion 124 is more than the maximum gauge of sub- connecting portion 126.That is, in the first rank
In the case of the demand depth relatively depth of scalariform via hole 120, the first stepped via hole 120 can be drilled by one-time mechanical adds two
Secondary laser drill or secondary mechanical drilling adds a laser drill or three times laser and forms stair-stepping through hole stage by stage.In detail
For, in the present embodiment, the generation type of the first stepped via hole 120 may include first with machine drilling or laser by first
Upper surface 122 is drilled into the depth of the bottom of top cover portion 122, then continues and drilled with laser by the bottom of top cover portion 122 to even
The bottom of socket part 124, then, then continue and drilled with laser by the bottom of connecting portion 124 to the bottom of sub- connecting portion 126
(being the first lower surface 114 in the present embodiment).Certainly, the present embodiment is only to for example, the present invention is not intended to limit sublevel
Section forms the Lase times of the first stepped via hole 120 with laser.
Fig. 3 is a kind of diagrammatic cross-section of semiconductor structure according to one embodiment of the invention.In this mandatory declaration
It is that the semiconductor structure 100b and Fig. 1 of the present embodiment semiconductor structure 100 are similar, and therefore, the present embodiment continues to use foregoing implementation
The element numbers and partial content of example, wherein adopting the identical or approximate element that is denoted by the same reference numerals, and eliminate phase
With the explanation of technology contents.Explanation on clipped refers to previous embodiment, and it is no longer repeated for the present embodiment.It please join
According to Fig. 3, explained below for the difference of semiconductor structure 100b and Fig. 1 semiconductor structure 100.
In the present embodiment, in the case of the demand depth relatively depth of the first stepped via hole 120, first stepped leads
Through hole 120 may also comprise base portion 128, and it is arranged at the first lower surface 114 of the first insulating barrier 110, and connecting portion 124 then connects
Between top cover portion 122 and base portion 128, wherein, the minimum diameter of base portion 128 is more than the maximum gauge of connecting portion.
That is, in the case of the demand depth relatively depth of the first stepped via hole 120, the present embodiment can utilize machine
Tool is drilled or laser is drilled from the first upper surface 112 and the first lower surface 114 toward the core direction of the first insulating barrier 110 respectively,
To form top cover portion 122 and base portion 128 respectively.Then, then continue and drilled with laser by the bottom of top cover portion 122 the bottom of to
Portions 128.In this way, the diameter of connecting portion 124 can be gradual toward one end away from top cover portion 122 from one end of connection top cover portion 122
Reduce.Or in other embodiments, laser can also be used drilling is started to top cover portion 122 come shape by the bottom of base portion 128
Into connecting portion, in this way, the diameter of connecting portion can gradually be subtracted from the one end in connect base portion 128 toward one end away from base portion 128
It is small.The present embodiment is only to for example, the present invention is not intended to limit, to form first stage by stage with machine drilling or laser stepped
The Lase times of via hole 120 and direction.
Fig. 4 is a kind of diagrammatic cross-section of semiconductor structure according to one embodiment of the invention.In this mandatory declaration
It is that the semiconductor structure 100c and Fig. 1 of the present embodiment semiconductor structure 100 are similar, and therefore, the present embodiment continues to use foregoing implementation
The element numbers and partial content of example, wherein adopting the identical or approximate element that is denoted by the same reference numerals, and eliminate phase
With the explanation of technology contents.Explanation on clipped refers to previous embodiment, and it is no longer repeated for the present embodiment.It please join
According to Fig. 4, explained below for the difference of semiconductor structure 100c and Fig. 1 semiconductor structure 100.
In the present embodiment, semiconductor structure 100c also include the second insulating barrier 140, the second patterned line layer 160 and
Multiple second stepped via holes 150.Second insulating barrier 140 includes the of the second upper surface 142 and relative second upper surface 142
Two lower surfaces 144, and the second insulating barrier 140 is to be stacked on its second lower surface 144 on the first insulating barrier 110, and the second figure
Case line layer 160 is then arranged at the second upper surface 142.Second stepped via hole 150 is arranged at the second insulating barrier 140 with electricity
Property conducting the first patterned line layer 130 and the second patterned line layer 160.That is, the semiconductor structure of the present embodiment
100c is Multilayer Structure.
Specifically, the second insulating barrier 140 can be identical with the material of the first insulating barrier 110, also includes general usual insulation
Material or alternative galvanic insulation material, wherein, alternative galvanic insulation material includes non-conductive metal composite.In this way, this
The characteristic that embodiment is electroplated using the alternative of the second insulating barrier 140, directly in formation such as Fig. 4 on the second upper surface 142
The second shown patterned line layer 160.Therefore, the second patterned line layer 160 formed according to above-mentioned technique can be embedded in
Second upper surface 142 of the second insulating barrier 140, and the second upper surface 142 of the second insulating barrier 140 exposes the second patterned circuit
The top surface of layer 160.Also, the bottom surface of the second patterned line layer 160 is less than the second upper surface 142 of the second insulating barrier 140.
In addition, the second stepped via hole 150 also can first pass through laser twice and be formed stage by stage stair-stepping logical
Hole, recycle the second insulating barrier 140 can by selectivityization plate with plating characteristic and to this stair-stepping through hole directly change plate and
Plating, to form conduction material in stair-stepping through hole, and then complete the making of the second stepped via hole 150.Therefore, second
The structure of stepped via hole 150 can be similar in appearance to Fig. 1 to Fig. 3 the first stepped via hole 120.
Fig. 5 is a kind of diagrammatic cross-section of semiconductor structure according to one embodiment of the invention.In this mandatory declaration
It is that the semiconductor structure 100d and Fig. 1 of the present embodiment semiconductor structure 100 are similar, and therefore, the present embodiment continues to use foregoing implementation
The element numbers and partial content of example, wherein adopting the identical or approximate element that is denoted by the same reference numerals, and eliminate phase
With the explanation of technology contents.Explanation on clipped refers to previous embodiment, and it is no longer repeated for the present embodiment.It please join
According to Fig. 5, explained below for the difference of semiconductor structure 100d and Fig. 1 semiconductor structure 100.
In the present embodiment, semiconductor structure 100d may also include the first chip 170 and multiple soldered balls 180.First chip
170 include the back side 174 of active surface 172 and confronting active-surface 172.First insulating barrier 110 covers the first chip 170
Active surface 172 and exposed backside 174, and the first stepped via hole 120 is then connected to the first upper surface 112 and the first chip
Between 170 active surface 172, to be electrically connected with the first patterned line layer 130 and the first core positioned at the first upper surface 112
Piece 170.Soldered ball is then arranged at the first upper surface 112 and is electrically connected with the first pattern lines layer 130.In this way, semiconductor structure
100d can be by soldered ball and externally connected electronic component, also, the first stepped via hole 120 is except can be used to electrically connect
Connect outside the first patterned line layer 130 and the first chip 170, its stair-stepping external form can more increase by the first chip 170, first
Adhesion between the stepped insulating barrier 110 of via hole 120 and first, and then lift semiconductor structure 100d reliability.
Fig. 6 is a kind of diagrammatic cross-section of semiconductor structure according to one embodiment of the invention.In this mandatory declaration
It is that the semiconductor structure 100e and Fig. 1 of the present embodiment semiconductor structure 100 are similar, and therefore, the present embodiment continues to use foregoing implementation
The element numbers and partial content of example, wherein adopting the identical or approximate element that is denoted by the same reference numerals, and eliminate phase
With the explanation of technology contents.Explanation on clipped refers to previous embodiment, and it is no longer repeated for the present embodiment.It please join
According to Fig. 6, explained below for the difference of semiconductor structure 100e and Fig. 1 semiconductor structure 100.
In the present embodiment, semiconductor structure 100e also includes the first chip 170 and the first redistribution line layer 190.The
One chip 170 includes the back side 174 of active surface 172 and confronting active-surface 172.First insulating barrier 110 covers the first core
The back side 174 of piece 170, and the first lower surface 114 exposure active surface 172 of the first insulating barrier 110.First redistribution line layer
190 are arranged at the first lower surface 114 and are electrically connected with the active surface 172 of the first chip 170.First stepped via hole 120
The first insulating barrier 110 can then be run through, to connect the first patterned line layer 130 and the first redistribution line layer 190.
In the present embodiment, the first stepped via hole 120 can also include base portion 128 similar in appearance to Fig. 3 embodiment,
It is arranged at the first lower surface 114, and connecting portion 124 is then connected between top cover portion 122 and base portion 128, and base portion 128
Minimum diameter is more than the maximum gauge of connecting portion 124.That is, whole first must be run through in the first stepped via hole 120
In the case of insulating barrier 110, the present embodiment can utilize machine drilling or laser respectively by the first upper surface 112 and the first lower surface
114 modes to be drilled toward the core direction of the first insulating barrier 110, to form top cover portion 122 and base portion 128 respectively.Then, then
Continue and the connecting portion 124 being connected between top cover portion 122 and base portion 128 is formed with laser drill.Certainly, the present embodiment is only used
With for example, the present invention is not intended to limit stage by stage with laser or the number of machine drilling the first stepped via hole 120 of formation
And direction.
In the present embodiment, semiconductor structure 100e may also include the second chip 175, the second insulating barrier 140, second divides again
Wiring topology layer 195 and multiple soldered balls 185.Second chip 175 includes the active surface 175a and confronting active-surface 175a back of the body
Face 175b.Second insulating barrier 140 includes the second lower surface 144 of the second upper surface 142 and relative second upper surface 142.Second
Insulating barrier 140 covers the back side 175b of the second chip 175, and the second lower surface 144 exposes the active surface of the second chip 175
175a.Second redistribution line layer 195 is arranged at the second lower surface 144 and is electrically connected with the active surface of the second chip 175
175a.Soldered ball 185 is connected between the first insulating barrier 110 and the second redistribution line layer 195, to be electrically connected with the first patterning
The redistribution line layer 195 of line layer 130 and second.In addition, semiconductor structure 100e may also include multiple soldered balls 180, it is set
In on the first redistribution line layer 190, to be electrically connected with the first chip 170.In this way, semiconductor structure 100e can pass through soldered ball
180 and be connected to another exterior electrical components.
In summary, semiconductor structure of the invention is added with laser technology at least twice or at least once machine drilling
Laser technology at least once, stepped via hole is formed to drill stage by stage, to reduce the depth of each laser drill, thus
The maximum gauge of stepped via hole can be reduced on the premise of the depth of stepped via hole is not shortened, and then can be lifted and partly led
The closeness of the configuration of body structure.Further, since machine drilling has the advantages of quick and aperture is consistent, therefore use it
Advantage is combined with laser technology, be can reach and is saved the effect of cost is with control size.Also, what technique was formed according to this is stepped
Via hole has stair-stepping external form, and this stair-stepping external form can increase the engagement between stepped via hole and insulating barrier
Power, to prevent that the situation of delamination occurs between stepped via hole and insulating barrier, and then the reliability of semiconductor structure can be lifted.
In addition, the insulating barrier of the semiconductor structure of the present invention includes general usual insulation material or alternative galvanic insulation
Material, it includes non-conductive metal composite, in this way, the semiconductor structure of the present invention can utilize the alternative plating of insulating barrier
Characteristic, directly in forming stepped via hole and patterned line layer on its surface, thus can effectively simplify semiconductor structure
Processing step and lifting design flexibility.
Although the present invention is disclosed as above with embodiment, so it is not limited to the present invention, any art
Middle tool usually intellectual, without departing from the spirit and scope of the present invention, when a little change and retouching can be made, thus it is of the invention
Protection domain be defined when depending on the scopes defined of appended claims.
Claims (16)
1. a kind of semiconductor structure, including：
First insulating barrier, including the first lower surface of the first upper surface and relatively described first upper surface；
Multiple first stepped via holes, first insulating barrier is arranged at first upper surface and described of electrically conducting
A lower surface, wherein each first stepped via hole includes the connecting portion of top cover portion and the connection top cover portion, it is described
Top cover portion is arranged at first upper surface and the top surface of the top cover portion and first upper surface copline, the top cover portion
Minimum diameter be more than the connecting portion maximum gauge；And
First patterned line layer, it is arranged at first upper surface and is electrically connected with the described first stepped via hole.
2. semiconductor structure according to claim 1, wherein the bottom surface of first patterned line layer is less than described the
One upper surface.
3. semiconductor structure according to claim 1, wherein the first stepped via hole also includes sub- connecting portion, even
The connecting portion is connected to, and the connecting portion is connected between the top cover portion and the sub- connecting portion, and the connecting portion
Minimum diameter is more than the maximum gauge of the sub- connecting portion.
4. semiconductor structure according to claim 1, wherein the first stepped via hole also includes base portion, set
In first lower surface, the connecting portion is connected between the top cover portion and the base portion, and the base portion is most
Minor diameter is more than the maximum gauge of the connecting portion.
5. semiconductor structure according to claim 1, wherein the material of first insulating barrier includes epoxy resin, gathered
Fat, acrylate, fluorine element polymer, polyphenylene oxide, polyimides, phenolic resin, polysulfones, silicon element polymer, BT trees
Fat (Bismaleimide-Triazine modified epoxy resin), cyanic acid polyester, polyethylene, polycarbonate resin,
Acrylonitrile-butadiene-styrene copolymer, PET (PET), polybutylene terephthalate (PBT), liquid
Polycrystalline macromolecule (liquid crystal polyester, LCP), polyamide (PA), nylon 6, kematal (POM), polyphenyl
Thioether (PPS), polycarbonate (polycarbonate, PC), polymethyl methacrylate (polymethacrylate, PMMA),
ABS resin (Acrylonitrile Butadiene Styrene, ABS) or cyclic olefin copolymer (COC).
6. semiconductor structure according to claim 1, wherein the material of first insulating barrier includes alternative electroplate
Insulation material, it includes non-conductive metal composite.
7. semiconductor structure according to claim 6, wherein the alternative galvanic insulation material includes epoxy resin, gathered
Fat, acrylate, fluorine element polymer, polyphenylene oxide, polyimides, phenolic resin, polysulfones, silicon element polymer, BT trees
Fat (Bismaleimide-Triazine modified epoxy resin), cyanic acid polyester, polyethylene, polycarbonate resin,
Acrylonitrile-butadiene-styrene copolymer, PET (PET), polybutylene terephthalate (PBT), liquid
Polycrystalline macromolecule (liquid crystal polyester, LCP), polyamide (PA), nylon 6, kematal (POM), polyphenyl
Thioether (PPS), polycarbonate (polycarbonate, PC), polymethyl methacrylate (polymethacrylate, PMMA),
ABS resin (Acrylonitrile Butadiene Styrene, ABS) or cyclic olefin copolymer (COC).
8. semiconductor structure according to claim 7, wherein the metal in the non-conductive metal composite include zinc,
Copper, silver, gold, nickel, palladium, platinum, cobalt, rhodium, iridium, indium, iron, manganese, aluminium, chromium, tungsten, vanadium, tantalum, titanium or its any combination.
9. semiconductor structure according to claim 1, in addition to：
Second insulating barrier, including the second lower surface of the second upper surface and relatively described second upper surface, second insulating barrier
Stacked on second lower surface on first insulating barrier；
Second patterned line layer, it is arranged at second upper surface；And
Multiple second stepped via holes, be arranged at second insulating barrier with electrically conduct first patterned line layer and
Second patterned line layer.
10. semiconductor structure according to claim 1, wherein the material of first insulating barrier includes silicon or glass.
11. semiconductor structure according to claim 1, in addition to the first chip, including active surface and relatively described
The back side of active surface, first insulating barrier cover the active surface of first chip and the exposure back side, institute
State the first stepped via hole to be connected between first upper surface and the active surface, to be electrically connected with first figure
Case line layer and first chip.
12. semiconductor structure according to claim 1, in addition to multiple soldered balls, it is arranged at first upper surface and electricity
Property connection the first pattern lines layer.
13. semiconductor structure according to claim 1, in addition to：
First chip, including first back side of the first active surface and relatively described first active surface, first insulation
Layer covers first back side of first chip, and first lower surface exposes first active surface；And
First redistribution line layer, it is arranged at first lower surface and is electrically connected with first active surface, described first
Stepped via hole runs through first insulating barrier to connect first patterned line layer and the first redistribution circuit
Layer.
14. semiconductor structure according to claim 13, wherein the first stepped via hole also includes base portion, if
First lower surface is placed in, the connecting portion is connected between the top cover portion and the base portion, and the base portion
Minimum diameter is more than the maximum gauge of the connecting portion.
15. semiconductor structure according to claim 13, in addition to multiple soldered balls, it is arranged at the first redistribution circuit
To be electrically connected with first chip on layer.
16. semiconductor structure according to claim 13, in addition to：
Second chip, including second back side of the second active surface and relatively described second active surface；
Second insulating barrier, including the second lower surface of the second upper surface and relatively described second upper surface, second insulating barrier
Second back side of second chip is covered, and second lower surface exposes second active surface；
Second redistribution line layer, it is arranged at second lower surface and is electrically connected with second active surface；And
Multiple soldered balls, it is connected between first insulating barrier and the second redistribution line layer, to be electrically connected with described
One patterned line layer and the second redistribution line layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105129233 | 2016-09-09 | ||
| TW105129233A TWI634636B (en) | 2016-09-09 | 2016-09-09 | Semiconductor structure |
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| CN107808859A true CN107808859A (en) | 2018-03-16 |
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| CN201610978663.XA Pending CN107808859A (en) | 2016-09-09 | 2016-11-08 | Semiconductor structure |
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| TW (1) | TWI634636B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110459509A (en) * | 2019-07-24 | 2019-11-15 | 浙江荷清柔性电子技术有限公司 | A kind of interconnection packaging method and interconnection package structure of chip |
| CN110473788A (en) * | 2018-05-10 | 2019-11-19 | 恒劲科技股份有限公司 | The preparation method and its structure of crystal-coated packing substrate plate |
| CN111627866A (en) * | 2019-02-27 | 2020-09-04 | 胜丽国际股份有限公司 | Chip-level sensor packaging structure |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1274256A (en) * | 1999-05-18 | 2000-11-22 | 三星电机株式会社 | Printed circuit board and its mfg. method |
| CN102026499A (en) * | 2009-09-14 | 2011-04-20 | 日月光半导体制造股份有限公司 | Structure of substrate, and manufacturing method thereof |
| CN102111954A (en) * | 2009-12-25 | 2011-06-29 | 欣兴电子股份有限公司 | Circuit board and manufacturing process thereof |
| CN102693911A (en) * | 2011-03-23 | 2012-09-26 | 上海华虹Nec电子有限公司 | Dry etching method |
| CN103857197A (en) * | 2012-12-04 | 2014-06-11 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board and manufacturing method of circuit board |
| CN104093279A (en) * | 2014-07-16 | 2014-10-08 | 电子科技大学 | Printed-circuit board manufacturing method based on laser groove machining technology |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090124398A (en) * | 2008-05-30 | 2009-12-03 | 주식회사 동부하이텍 | Method for manufacturing semiconductor element |
-
2016
- 2016-09-09 TW TW105129233A patent/TWI634636B/en not_active IP Right Cessation
- 2016-11-08 CN CN201610978663.XA patent/CN107808859A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1274256A (en) * | 1999-05-18 | 2000-11-22 | 三星电机株式会社 | Printed circuit board and its mfg. method |
| CN102026499A (en) * | 2009-09-14 | 2011-04-20 | 日月光半导体制造股份有限公司 | Structure of substrate, and manufacturing method thereof |
| CN102111954A (en) * | 2009-12-25 | 2011-06-29 | 欣兴电子股份有限公司 | Circuit board and manufacturing process thereof |
| CN102693911A (en) * | 2011-03-23 | 2012-09-26 | 上海华虹Nec电子有限公司 | Dry etching method |
| CN103857197A (en) * | 2012-12-04 | 2014-06-11 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board and manufacturing method of circuit board |
| CN104093279A (en) * | 2014-07-16 | 2014-10-08 | 电子科技大学 | Printed-circuit board manufacturing method based on laser groove machining technology |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110473788A (en) * | 2018-05-10 | 2019-11-19 | 恒劲科技股份有限公司 | The preparation method and its structure of crystal-coated packing substrate plate |
| CN111627866A (en) * | 2019-02-27 | 2020-09-04 | 胜丽国际股份有限公司 | Chip-level sensor packaging structure |
| CN111627866B (en) * | 2019-02-27 | 2022-03-04 | 胜丽国际股份有限公司 | Chip-level sensor packaging structure |
| CN110459509A (en) * | 2019-07-24 | 2019-11-15 | 浙江荷清柔性电子技术有限公司 | A kind of interconnection packaging method and interconnection package structure of chip |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI634636B (en) | 2018-09-01 |
| TW201810587A (en) | 2018-03-16 |
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Application publication date: 20180316 |