CN107808856A - 半导体封装结构及其制造方法 - Google Patents

半导体封装结构及其制造方法 Download PDF

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Publication number
CN107808856A
CN107808856A CN201710680392.4A CN201710680392A CN107808856A CN 107808856 A CN107808856 A CN 107808856A CN 201710680392 A CN201710680392 A CN 201710680392A CN 107808856 A CN107808856 A CN 107808856A
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semiconductor package
layer
encapsulated layer
encapsulating structure
rewiring
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CN201710680392.4A
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CN107808856B (zh
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徐宏欣
林南君
张简上煜
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Powertech Technology Inc
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Powertech Technology Inc
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Abstract

本发明提供半导体封装结构及其制造方法。半导体封装结构包括重布线结构、封装结构以及第二封装层。重布线结构具有彼此相对的第一与第二表面。封装结构位于第一表面上。封装结构包括管芯、第一封装层、重布线层以及多个第二导电端子。管芯具有位于其上的多个第一导电端子。第一封装层包覆管芯。第一封装层暴露出至少一部分的第一导电端子。重布线层位于第一封装层上。重布线层电性连接至暴露出的第一导电端子。多个第二导电端子电性连接于重布线层与重布线结构之间。第二封装层包覆封装结构。第二封装层暴露出至少一部分的第二导电端子。

Description

半导体封装结构及其制造方法
技术领域
本发明涉及一种半导体封装结构，尤其涉及一种扇出(fan-out)型半导体封装结构及其制造方法。
背景技术
近年来半导体封装技术不断进展，以发展出体积更小、重量更轻、积集度(integration level)更高且制造成本更低的产品。举例而言，目前已发展出晶片级扇入(fan-in)封装。扇入封装具有在连接于对应的管芯的区域内的输入/输出(input/output)端子。然而，由于输入/输出端子被限制在管芯的表面，此种封装类型被限制在仅需至多200至300的连接数目的低阶组件。
发明内容
本发明提供一种半导体封装结构及其制造方法，可相容于更高的输入/输出连接数目，且能够有效地降低制造成本。
本发明的半导体封装结构包括重布线结构、至少一封装结构以及第二封装层。重布线结构具有第一表面以及相对于第一表面的第二表面。至少一封装结构位于重布线结构的第一表面上。至少一封装结构包括至少一管芯、第一封装层、重布线层以及多个第二导电端子。至少一管芯具有位于至少一管芯上的多个第一导电端子。第一封装层包覆至少一管芯。第一封装层暴露出至少一部分的多个第一导电端子。重布线层位于第一封装层上。重布线层电性连接至被第一封装层暴露出的第一导电端子。多个第二导电端子电性连接于重布线层与重布线结构之间。第二封装层包覆至少一封装结构。第二封装层暴露出至少一部分的多个第二导电端子。
在本发明的一实施例中，重布线结构包括至少一介电层以及嵌入于至少一介电层中的多个导电单元。多个导电单元包括多个第一接合垫、多个第二接合垫以及多个互联结构。多个第一接合垫位于重布线结构的第一表面。多个第二导电端子经设置以对应于多个第一接合垫。多个第二接合垫位于重布线结构的第二表面。多个互联结构电性连接至少一部分的多个第一接合垫与至少一部分的多个第二接合垫。
在本发明的一实施例中，重布线结构包括印刷电路板或有机封装基板。
本发明的半导体封装结构的制造方法包括下列步骤。形成至少一封装结构。至少一封装结构包括至少一管芯、第一封装层、重布线层以及多个第二导电端子。至少一管芯具有位于其上的多个第一导电端子。第一封装层包覆至少一管芯且暴露出至少一部分的多个第一导电端子。重布线层位于第一封装层上且电性连接至被第一封装层暴露出的第一导电端子。多个第二导电端子位于重布线层上。将至少一封装结构耦合至重布线结构的第一表面。至少一封装结构的多个第二导电端子电性连接至重布线结构。以第二封装层包覆至少一封装结构。
在本发明的一实施例中，多个第二导电端子中的每一者包括导电柱、导电凸块或其组合。
在本发明的一实施例中，将重布线结构与至少一封装结构耦合的步骤在包覆至少一封装结构的步骤之前。
在本发明的一实施例中，将重布线结构与至少一封装结构耦合的步骤与包覆至少一封装结构的步骤包括下列子步骤。在载体上形成重布线结构。重布线结构包括至少一介电层与嵌入于至少一介电层中的多个导电单元，且至少一介电层暴露出至少一部分的多个导电单元。将至少一封装结构置于重布线结构的第一表面上。第二导电端子与被至少一介电层暴露出的导电单元电性连接。于重布线结构的第一表面上形成第二封装层。自重布线结构移除载体。
在本发明的一实施例中，将重布线结构与至少一封装结构耦合的步骤与包覆至少一封装结构的步骤包括下列子步骤。提供重布线结构。重布线结构包括至少一介电层以及嵌入于至少一介电层中的多个导电单元，且至少一介电层暴露出至少一部分的多个导电单元。将至少一封装结构置于重布线结构的第一表面上。第二导电端子与至少一介电层暴露出的导电单元电性连接。在重布线结构的第一表面上形成第二封装层。
在本发明的一实施例中，包覆至少一封装结构的步骤在将重布线结构与至少一封装结构耦合的步骤之前。
在本发明的一实施例中，包覆至少一封装结构的步骤以及将重布线结构与至少一封装结构耦合的步骤包括下列子步骤。提供载体。将至少一封装结构置于载体上。以第二封装层包覆至少一封装结构。移除至少一部分的第二封装层以暴露出至少一部分的多个第二导电端子。在第二封装层上形成重布线结构，以与被第二封装层暴露出的第二导电端子电性连接。自至少一封装结构以及第二封装层移除载体。
基于上述，封装结构的第一封装层在每一管芯的周围提供额外的空间，以使得在管芯上的第一导电端子可经由重布线层而被连接至此额外的空间。基于封装结构的扇出(fan-out)配置，此封装结构可相容于更高的输入/输出连接数目。此外，可改善封装结构的电性表现以及散热表现。相似地，由于将封装结构嵌入于第二封装层且将重布线结构与封装结构的第二导电端子耦合，半导体封装结构形成另一扇出封装结构。因此，可达到更高的输入/输出连接数目。此外，重布线结构可取代现有的硅穿孔(through silicon via，TSV)中介层，以降低制造成本。再者，重布线层与重布线结构分别在不同的扇出工艺中被形成。因此，可降低封装结构的翘曲程度(warpage level)。据此，半导体封装结构可包含具有较复杂设计的重布线结构。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A至图1G是依照本发明一实施例显示的封装结构的制造方法的剖视示意图；
图2A至图2F是依照本发明一实施例显示的半导体封装结构的制造方法的剖视示意图；
图3A至图3D是依照本发明一些实施例显示的半导体封装结构的剖视示意图；
图4A至图4D是依照本发明另一实施例显示的半导体封装结构的制造方法的剖视示意图；
图5A至图5C是依照本发明一些实施例显示的半导体封装结构的剖视示意图；
图6A至图6F是依照本发明又一实施例显示的半导体封装结构的制造方法的剖视示意图；
图7A至图7C是依照本发明一些实施例显示的半导体封装结构的剖视示意图。
具体实施方式
图1A至图1G是依照本发明一实施例显示的封装结构100的制造方法的剖视示意图。
请参照图1A，于载体108上形成多个管芯106。载体108可由玻璃、塑料或其他适合的材料构成。每一管芯106具有形成于其上的多个第一导电端子102。可经由以下的步骤制造管芯106。首先，提供具有多个垫102’的晶片(未显示)。多个垫102’形成于晶片上。随后，形成覆盖垫以及晶片的钝化层(未显示)。图案化钝化层以产生多个钝化图案104。举例而言，可经由光微影与蚀刻工艺以对钝化层进行图案化。钝化图案104暴露出至少一部分的垫102’。之后，在垫102’上形成第一导电端子102。可经由镀着工艺(plating process)形成第一导电端子102。举例而言，镀着工艺可为电镀、无电镀、浸镀(immersion plating)或其类似者。接着，由相对于第一导电端子102的背面研磨晶片，且切割晶片以得到多个管芯106。值得注意的是，每一管芯106的具有第一导电端子102形成于其上的表面称作管芯106的有源面(active surface)。
在一些实施例中，附着层110可设置于载体108与管芯106之间，以暂时地增进管芯106与载体108之间的附着性。附着层110可为光热转换(light to heat conversion，LTHC)附着层或其他适合的附着层。值得注意的是，在图1A中两个管芯106经形成于载体108上，然而本发明并不以此为限。在其他实施例中，单一管芯106或多于两个的管芯106可经设置于载体108上。
请参照图1B，在载体108上形成第一封装层112，以包覆管芯106。在一些实施例中，第一封装层112可包括经由封胶工艺(molding process)形成的封胶材料(moldingcompound)。在其他实施例中，第一封装层112可由绝缘材料所形成，绝缘材料例如是环氧树脂或其他适合的树脂。
请参照图1C，薄化第一封装层112直至第一导电端子102的顶面被暴露出来。如图1C所示，第一封装层112暴露出部分的第一导电端子102。在一些实施例中，在第一封装层112经薄化以暴露出第一导电端子102的顶面之后，更对第一导电端子102进行蚀刻工艺。举例而言，部分移除第一导电端子102以使得第一导电端子102的顶面些微地低于第一封装层112的顶面。在一些实施例中，第一导电端子102的顶面比第一封装层112的顶面低1μm至3μm。如此一来，第一封装层112与第一导电端子102的表面粗糙度提高，以使其对于后续形成于其上的膜层可具有较佳的附着性。举例而言，可通过机械研磨、化学机械研磨、蚀刻或其他适合的方法以达成薄化工艺。对于第一导电端子102进行的蚀刻工艺可包括非等向性蚀刻或等向性蚀刻。
请参照图1D，于第一封装层112上形成重布线层114，且将重布线层114电性连接至第一导电端子102。重布线路层114可包括至少一介电层116以及嵌入于介电层116的多个导电单元118。如图1D所示，重布线层114包括三层介电层116。然而，介电层116的数量可依据电路设计而调整，本发明并不以此为限。导电单元118可包括多个接合垫120、多个接合垫122以及多个互联结构124。接合垫120经设置以面对第一导电端子102。最底层的介电层116暴露出接合垫120，以使垫120与其他构件电性连接。举例而言，接合垫120可直接接触第一导电端子102以使管芯106与重布线层114之间形成电性连接。接合垫122经设置于重布线层114的相对于第一导电端子102的表面。最上层的介电层116暴露出接合垫122，以使接合垫122电性连接于后续工艺中所形成的构件。互联结构124经嵌入于介电层116中，且电性连接于至少一部分的接合垫120与至少一部分的接合垫122之间。可通过镀着工艺(platingprocess)形成导电单元118，且导电单元118可包括铜、铝、金、银、焊料或其组合。
请参照图1E，通过分离工艺(debonding process)将载体108自管芯106与第一封装层112分离。详而言之，可对附着层110施加热能或光能(例如是热或紫外光照射)。一旦受到热能或光能的影响，附着层110失去附着性且可轻易地自载体108、管芯106以及第一封装层112被剥离。
请参照图1F，于接合垫122上设置多个第二导电端子126，且使多个第二导电端子126电性连接至接合垫122。第二导电端子122可包括导电柱、导电凸块或其组合。举例而言，如图1F所示，第二导电端子126中的每一个包括导电柱128以及设置于导电柱128上的导电凸块130。
请参照图1G，进行单体化工艺(singulation process)。相邻的管芯106之间的第一封装层112经切开以形成多个封装结构100。举例而言，单体化工艺包括以旋切刀(rotating blade)或激光光束切割。
基于将管芯106嵌入于第一封装层112中且将重布线层114设置于第一封装层112上，两相邻的第一导电端子102之间的第一间距P1小于两相邻的第二导电端子126之间的第二间距P2。换言之，每一封装结构100形成扇出封装结构(fan-out package structure)。在扇出封装结构中，第一封装层112在管芯106的周围提供额外的空间，以使得第一导电端子102可经由重布线层114而被连接至此额外的空间。因此，可在封装结构100中达到更高的输入/输出连接数目(I/O connection number)。此外，可改善封装结构100的电性表现以及散热表现。
图2A至图2F是依照本发明一实施例显示的半导体封装结构200的制造方法的剖视示意图。
请参照图2A，在载体202上形成重布线结构204。载体202可由玻璃、塑料或其他适合的材料构成。在一些实施例中，可预先在载体202上沉积附着层203，以暂时地提高重布线结构204与载体202之间的附着性。附着层203可为光热转换附着层或其他适合的附着层。重布线结构204可包括至少一介电层206以及嵌入于介电层206中的多个导电单元208。导电单元208包括多个第一接合垫210、多个第二接合垫212以及多个互联结构214。第一接合垫210经设置于重布线结构204的相对于载体202的第一表面S1。最上层的介电层206暴露出第一接合垫210。第二接合垫212设置于重布线结构204的面对载体202的第二表面S2。最底层的介电层206暴露出第二接合垫212。互联结构214经嵌入于介电层206中且电性连接于至少一部分的第一接合垫210与至少一部分的第二接合垫212之间。
请参照图2B，通过覆晶接合(flip-chip bonding)将图1G所示的封装结构100耦合至或置于重布线结构204的第一表面S1上。封装结构100的第二导电端子126电性连接至重布线结构204的第一接合垫210。换言之，第二导电端子126电性连接于重布线层114与重布线结构204之间。値得注意的是，在图2B中有六个封装结构100被形成于载体202上。然而，本发明并不以此为限。在其他实施例中，可将单一封装结构100或多于/少于六个的封装结构100形成于载体202上。
请参照图2C，在重布线结构204的第一表面S1上形成第二封装层216，以包覆封装结构100。在一些实施例中，第二封装层216可包括由封胶工艺形成的封胶材料。在其他实施例中，第二封装层216可由绝缘材料所形成，绝缘材料例如是环氧树脂或其他适合的树脂。此外，在其他实施例中，第二封装层216可自顶表面被薄化以减低半导体封装结构200的整体厚度。举例而言，可通过机械研磨、化学机械研磨、蚀刻或其他适合的方法以达成薄化工艺。在其他实施例中，由于每一管芯106的有源面朝向下方，因此亦可将管芯106薄化至所需的厚度而不影响其电性。在本实施例中，将重布线结构204与封装结构100耦合的步骤在以第二封装层216包覆封装结构100的步骤之前。
请参照图2D，将载体202与附着层203自重布线结构204移除或分离。举例而言，可对附着层203施加热能或光能(例如是热或紫外光照射)。一旦受到热能或光能的影响，附着层203失去附着性且可轻易地自载体202与重布线结构204被剥离。
请参照图2E，于重布线结构204的第二表面S2上形成多个焊球218。焊球218电性连接至重布线结构204的第二接合垫212。举例而言，可通过植球工艺(ball placementprocess)以形成焊球218。
请参照图2F，进行单体化工艺。相邻的封装结构100之间的第二封装层216经切开以形成多个半导体封装结构200。举例而言，单体化工艺包括以旋切刀或激光光束切割。
请同时参照图1G与图2F，基于将封装结构100嵌入于第二封装层216中，且将重布线结构204设置于第二封装层216上，第二间距P2小于两相邻的焊球218之间的第三间距P3。换言之，每一半导体封装结构200形成具有另一封装结构(封装结构100)嵌入于其中的一封装结构。半导体封装结构200的第二封装层216更在每一封装结构100的周围提供额外的空间以作为布线(trace routing)用。因此，可达成更高的输入/输出连接数目。此外，重布线结构204可取代现有的硅穿孔(through silicon via，TSV)中介层，以降低制造成本。再者，在封装结构100中，重布线层114经形成于管芯106上。另一方面，重布线结构204经形成于载体202上。换言之，重布线层114与重布线结构204分别在不同的扇出工艺中被形成。因此，可降低封装结构100的翘曲程度(warpage level)。如此一来，半导体封装结构200的翘曲程度可小于两个重布线结构均直接形成于管芯/封装结构(非分别形成)的半导体封装结构的翘曲程度。据此，半导体封装结构200可包含具有较复杂设计的重布线结构204。
半导体封装结构200可相容于具有高阶组件的应用以及前端技术节点。上述高阶组件的应用与前端技术节点具有更高的输入/输出连接数，且每一管芯具有更窄的接垫间距。
图3A至图3D是依照本发明一些实施例显示的半导体封装结构300a、半导体封装结构300b、半导体封装结构300c以及半导体封装结构300d的剖视示意图。
请参照图3A，半导体封装结构300a相似于图2F所示的半导体封装结构200，故在此省略详细的说明。半导体封装结构300a与半导体封装结构200的差异在于半导体封装结构300a更包括封装结构100a。封装结构100a相似于图1G所示的封装结构100，封装结构100a包括两个管芯106。换言之，可将多个管芯整合于封装结构100a中。
请参照图3B，半导体封装结构300b相似于图2F所示的半导体封装结构200，故在此省略详细的说明。半导体封装结构300b与半导体封装结构200的差异在于半导体封装结构300b更包括至少一附加封装结构302。举例而言，附加封装结构302为晶片级芯片尺寸封装(wafer level chip scale package，WLCSP)。换言之，附加封装结构302为扇入封装结构。相较于显示于图1G的封装结构100(扇出封装结构)，附加封装结构302中的管芯106并未被封装层包覆。相似于封装结构100，附加封装结构302亦通过覆晶接合而被耦合至重布线结构204的第一表面S1。随后，进行如图2C至图2F所显示的步骤以得到半导体封装结构300b。如此一来，可轻易地整合不同类型的封装结构，以符合多芯片封装(multi-chip package，MCP)或***封装(system in package，SIP)的应用。
请参照图3C，半导体封装结构300c相似于图2F所示的半导体封装结构200，故在此省略详细的说明。半导体封装结构300c与半导体封装结构200的差异在于半导体封装结构300c更包括至少一无源组件304。举例而言，无源组件304为电阻、电容、电感、二级管或天线。相似于封装结构100，无源组件304亦被置于重布线结构204的第一表面S1上。随后，可进行图2C至图2F所示的步骤以得到半导体封装结构300c。如此一来，可轻易地整合封装结构与无源组件。
请参照图3D，半导体封装结构300d相似于图3B所示的半导体封装结构300b，故在此省略详细的说明。半导体封装结构300d与半导体封装结构300b的差异在于半导体封装结构300d的附加封装结构302a通过打线接合(wire bonding)而被耦合至重布线结构204的第一表面S1。因此，在形成附加封装结构302a的期间，可省略图1A至图1G所示的有关于第一封装层112、重布线层114以及第二导电端子126的步骤。依据半导体封装结构300d的配置，可轻易地整合不同类型的封装结构。
图4A至图4D是依照本发明另一实施例显示的半导体封装结构400的制造方法的剖视示意图。
请参照图4A，提供重布线结构402。在一些实施例中，重布线结构402可包括印刷电路板(printed circuit board，PCB)或有机封装基板。举例而言，有机封装基板可包括用以组装的现有有机基板，其例如是核心有机封装基板(举例而言，双马来酰亚胺-三氮杂苯树脂(Bismaleimide triazine resin)基板)或无核心有机封装基板。举例而言，可通过委外封测(outsourced semiconductor assembly and test，OSAT)与用于扇出封装的机台/工艺形成重布线结构402。在其他实施例中，重布线结构402可为基板供应商所提供的有机基板。重布线结构402包括多个导电单元404以及聚合物基板406。由于聚合物为介电材料，聚合物基板406可作为介电层。导电单元404嵌入于聚合物基板406中。导电单元404包括多个第一接合垫408、多个第二接合垫410以及多个互联结构(未显示)。第一接合垫408设置于重布线结构402的第一表面S1，且被聚合物基板406暴露出。第二接合垫410设置于重布线结构402的相对于第一表面S1的第二表面S2，且被聚合物基板406暴露出。互联结构(未显示)嵌入于聚合物基板406中，且电性连接于至少一部分的第一接合垫408与至少一部分的第二接合垫410之间。
之后，通过覆晶接合而将图1G所示的封装结构100耦合于或置于重布线结构402的第一表面S1上。封装结构100的第二导电端子126电性连接至重布线结构402的第一接合垫408。换言之，第二导电端子126电性连接于重布线层114与重布线结构402之间。
请参照图4B至图4D，图4B至图4D所示的步骤相似于图2C以及图2E至图2F所示的步骤，故在此省略详细的说明。于重布线结构402的第一表面S1上形成第二封装层412，以包覆封装结构100。在本实施例中，将重布线结构402与封装结构100耦合的步骤在以第二封装层412包覆封装结构100的步骤之前。于重布线结构402的第二表面S2上形成多个焊球414，以与重布线结构402的第二接合垫410电性连接。相邻的封装结构100之间的第二封装层412经切开以形成多个半导体封装结构400。
在本实施例中，扇出封装结构(封装结构100)耦合至用以组装的现有有机基板(重布线结构402)，以形成半导体封装结构400。因此，每一半导体封装结构400可视为包含扇出结构的类芯片尺寸覆晶封装(flip chip chip scale package，FCCSP)或类覆晶球格阵列(flip chip ball grid array，FCBGA)的封装结构。由于封装结构100耦合至用以组装的现有有机基板，扇出技术被应用于将具有较精细的集成电路接垫间距(例如是管芯106的接垫及走线的精细间距)的封装结构100电性连接至具有较大的焊球间距的有机基板(例如是重布线结构402)。因此，可降低每一封装结构100中的管芯106的集成电路接垫间距(精细间距)，且仍可相容于现有可用的有机基板(例如是重布线结构402)。此外，重布线层114形成于封装基板100中，而重布线结构402为另一预先制造的结构。换言之，重布线层114与重布线结构402在不同的扇出工艺中形成。因此，可降低半导体封装结构400的翘曲程度。如此一来，半导体封装结构400可包含具有较复杂设计的重布线结构402。
图5A至图5C是依照本发明一些实施例显示的半导体封装结构500a、半导体封装结构500b以及半导体封装结构500c的剖视示意图。
请参照图5A，半导体封装结构500a相似于图4D所示的半导体封装结构400，故在此省略详细的说明。半导体封装结构500a与半导体封装结构400的差异在于半导体封装结构500a更包括至少一附加封装结构302。本实施例的附加封装结构302相似于图3B的相关说明所讨论的附加封装结构302，故在此省略详细的说明。相似于封装结构100，附加封装结构302亦通过覆晶结合而耦合至重布线结构402的第一表面S1。随后，可进行图4B至图4D的步骤以得到半导体封装结构500a。如此一来，可轻易地整合不同类型的封装结构。
请参照图5B，半导体封装结构500b相似于图4D所示的半导体封装结构400，故在此省略详细的说明。半导体封装结构500b与半导体封装结构400的差异在于半导体封装结构500b更包括至少一无源组件304。本实施例的无源组件304相似于图3C的相关说明所讨论的无源组件304，故在此省略详细的说明。相似于封装结构100，无源组件304置于或设置于重布线结构402的第一表面S1上。随后，进行图4B至图4D所示的步骤以得到半导体封装结构500b。如此一来，可轻易地整合封装结构与无源组件。
请参照图5C，半导体封装结构500c相似于图5A所示的半导体封装结构500a，故在此省略详细的说明。半导体封装结构500c对于半导体封装结构500a的差异在于附加封装结构302a通过打线接合而耦合至重布线结构402的第一表面S1。因此，省略图1A至图1G所示的关于第一封装层112、重布线层114以及第二导电端子126的步骤。基于半导体封装结构500c的配置，可轻易地整合不同类型的封装结构。
图6A至图6F是依照本发明又一实施例显示的半导体封装结构600的制造方法的剖视示意图。
请参照图6A，图1G所示的封装结构100置于载体602上，以使得管芯106的有源面朝向上方。在一些实施例中，附着层604可设置于载体602与封装结构100之间以暂时地提高封装结构100与载体602之间的附着性。如图6A所示，第二导电端子126可为导电柱的形式。
请参照图6B，于载体602上形成第二封装层606，以包覆封装结构100。在一些实施例中，第二封装层606可包括经由封胶工艺形成的封胶材料。在其他实施例中，第二封装层606可由例如是环氧树脂或其他适合的树脂的绝缘材料形成。
请参照图6C，移除一部分的第二封装层606。详而言之，薄化第二封装层606直到暴露出封装结构100的第二导电端子126的顶面。在一些实施例中，在薄化第二封装层606以暴露出第二导电端子126的顶面之后，更可对第二导电端子126进行蚀刻工艺。举例而言，可部分地移除第二导电端子126以使第二导电端子126的顶面稍微低于第二封装层606的顶面。在一些实施例中，第二导电端子126的顶面低于第二封装层606的顶面1μm至3μm。如此一来，可提高第二封装层606与第二导电端子126的表面粗糙度，以提高其对于后续形成在上方的膜层的附着性。举例而言，可经由机械研磨、化学机械研磨、蚀刻或其他适合的方法达成薄化工艺。对于第二导电端子126的蚀刻工艺可包括非等向性蚀刻或等向性蚀刻。
请参照图6D，于封装结构100与第二封装层606上设置重布线结构608。重布线结构608包括至少一介电层610与嵌入于介电层610的多个导电单元612。导电单元612包括多个第一接合垫614、多个第二接合垫616以及多个互联结构618。第一接合垫614设置于重布线结构608的面对封装结构100的第一表面S1。最下方的介电层610暴露出第一接合垫614，使得第一接合垫614电性连接至第二导电端子126。换言之，重布线结构608的性连接至封装结构100的第二导电端子126。第二接合垫616设置于重布线结构608的相对于第一表面S1的第二表面S2。最上方的介电层610暴露出第二接合垫616以使其与在后续工艺中形成的构件电性连接。互联结构618电性连接于至少一部分的第一接合垫614与至少一部分的第二接合垫616之间。由于重布线结构608形成于封装结构100与第二封装层606两者上，而非整个形成于封装结构100上。因此，可降低封装结构100的翘曲程度。在本实施例中，包覆封装结构100的步骤在将重布线结构608与封装结构100耦合的步骤之前。
请参照图6E，于重布线结构608的第二表面S2上形成多个焊球620。焊球620电性连接至重布线结构608的第二接合垫616。举例而言，可通过植球工艺形成焊球620。
请参照图6F，将载体602与附着层604自封装结构100与第二封装层606移除或分离。举例而言，可对附着层604施加热能或光能(例如是热或紫外光照射)。一旦受到热能或光能的影响，附着层604失去附着性且可轻易地自载体602、封装结构100以及第二封装层606被剥离。値得注意的是，如图6E与图6F显示的内容，焊球620是在分离工艺之前形成。然而，本发明并不以此为限。在其他实施例中，可在形成焊球620于重布线结构608的第二表面S2上之前进行分离工艺。切开相邻的封装结构100之间的第二封装层606，以形成多个半导体封装结构600。举例而言，单体化工艺包括以旋切刀或激光光束切割。
每一半导体封装结构600形成具有另一封装结构(封装结构100)嵌入于其中的一封装结构。半导体封装结构600的第二封装层606更在每一封装结构100的周围提供额外的空间以作为布线用。因此，可达成更高的输入/输出连接数。此外，重布线结构608可取代现有的硅穿孔中介层，以降低制造成本。再者，由于重布线结构608形成于封装结构100与第二封装层606两者上，而非整个形成于封装结构100上。因此，可降低封装结构100的翘曲程度。据此，半导体封装结构600可包含具有较复杂设计的重布线结构608。
图7A至图7C是依照本发明一些实施例显示的半导体封装结构700a、半导体封装结构700b以及半导体封装结构700c的剖视示意图。
请参照图7A，半导体封装结构700a相似于图6F所示的半导体封装结构600，故在此省略详细的说明。半导体封装结构700a对于半导体封装结构600的差异在于半导体封装结构700a包括封装结构100a。本实施例的封装结构100a相似于图3A的相关说明所讨论的封装结构100a，故在此省略详细的说明。在本实施例中，可将多个管芯整合在封装结构100a中。
请参照图7B，半导体封装结构700b相似于图6F所示的半导体封装结构600，故在此省略详细的说明。半导体封装结构700b对于半导体封装结构600的差异在于半导体封装结构700b更包括至少一附加封装结构302。本实施例的附加封装结构302相似于图3B的相关说明所讨论的附加封装结构302，故在此省略详细的说明。相似于封装结构100，附加封装结构302置于载体602上。随后，可进行图6B至图6F所示的步骤以得到半导体封装结构700b。如此一来，可轻易地整合不同类型的封装结构，以符合多芯片封装或***封装的应用。
请参照图7C，半导体封装结构700c相似于图7B所示的半导体封装结构700b，故在此省略详细的说明。半导体封装结构700c对于半导体封装结构700b的差异在于半导体封装结构700c更包括设置于重布线结构608的第二表面S2上的至少一无源组件702。本实施例的无源组件702相似于图3C所示的无源组件304。无源组件702电性连接至重布线结构608的第二接合垫616。如此一来，可轻易地整合封装结构与无源组件。
综上所述，封装结构的第一封装层在每一管芯的周围提供额外的空间，以使得在管芯上的第一导电端子可经由重布线层而被连接至此额外的空间。基于封装结构的扇出配置，此封装结构可相容于更高的输入/输出连接数目。此外，可改善封装结构的电性表现以及散热表现。相似地，由于将封装结构嵌入于第二封装层且将重布线结构与封装结构的第二导电端子耦合，半导体封装结构形成另一扇出封装结构。因此，可达到更高的输入/输出连接数目。此外，重布线结构可取代现有的硅穿孔中介层，以降低制造成本。再者，重布线层与重布线结构分别在不同的扇出工艺中被形成。因此，可降低封装结构的翘曲程度。据此，半导体封装结构可包含具有较复杂设计的重布线结构。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的精神和范围内，当可作些许的更改与润饰，故本发明的保护范围当视权利要求书所界定的为准。

Claims (10)

1.一种半导体封装结构，其特征在于，包括：
重布线结构，具有第一表面以及相对于所述第一表面的第二表面；
至少一封装结构，位于所述重布线结构的所述第一表面上，其中所述至少一封装结构包括：
至少一管芯，具有位于所述至少一管芯上的多个第一导电端子；
第一封装层，包覆所述至少一管芯，其中所述第一封装层暴露出至少一部分的所述多个第一导电端子；
重布线层，位于所述第一封装层上，其中所述重布线层电性连接至被所述第一封装层暴露出的第一导电端子；以及
多个第二导电端子，电性连接于所述重布线层与所述重布线结构之间；以及
第二封装层，包覆所述至少一封装结构，其中所述第二封装层暴露出至少一部分的所述多个第二导电端子。
2.根据权利要求1所述的半导体封装结构，其特征在于，还包括位于所述重布线结构的所述第二表面上的多个焊球。
3.根据权利要求2所述的半导体封装结构，其特征在于，两相邻的第一导电端子之间的第一间距小于两相邻的第二导电端子之间的第二间距，且所述第二间距小于两相邻的焊球之间的第三间距。
4.根据权利要求1所述的半导体封装结构，其特征在于，所述多个第二导电端子中的每一个包括导电柱、导电凸块或其组合。
5.根据权利要求1所述的半导体封装结构，其特征在于，还包括至少一无源组件和/或至少一附加封装结构，设置于所述重布线结构的所述第一表面上。
6.根据权利要求1所述的半导体封装结构，其特征在于，还包括至少一无源组件，设置于所述重布线结构的所述第二表面上。
7.一种半导体封装结构的制造方法，其特征在于，包括：
形成至少一封装结构，其中所述至少一封装结构包括至少一管芯、第一封装层、重布线层以及多个第二导电端子，所述至少一管芯具有位于其上的多个第一导电端子，所述第一封装层包覆所述至少一管芯且暴露出至少一部分的所述多个第一导电端子，所述重布线层位于所述第一封装层上且电性连接至被所述第一封装层暴露出的第一导电端子，所述多个第二导电端子位于所述重布线层上；
将所述至少一封装结构耦合至所述重布线结构的第一表面，其中所述至少一封装结构的所述多个第二导电端子电性连接至所述重布线结构；以及
以第二封装层包覆所述至少一封装结构。
8.根据权利要求7所述的半导体封装结构的制造方法，其特征在于，还包括在所述重布线结构的相对于所述第一表面的第二表面上形成多个焊球，其中两相邻的第一导电端子之间的第一间距小于两相邻的第二导电端子之间的第二间距，且所述第二间距小于两相邻的焊球之间的第三间距。
9.根据权利要求7所述的半导体封装结构的制造方法，其特征在于，还包括在所述重布线结构的相对于所述第一表面的第二表面上形成至少一无源组件。
10.根据权利要求7所述的半导体封装结构的制造方法，其特征在于，还包括：
将至少一附加封装结构或至少一无源组件耦合至所述重布线结构的所述第一表面；以及
以所述第二封装层包覆所述至少一附加封装结构或所述至少一无源组件。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111128937A (zh) * 2018-10-30 2020-05-08 三星电子株式会社 半导体封装件
WO2021037233A1 (zh) * 2019-08-30 2021-03-04 天芯互联科技有限公司 封装体及其制备方法
TWI733039B (zh) * 2018-05-11 2021-07-11 日月光半導體製造股份有限公司 半導體基板及其製造方法
WO2022041159A1 (zh) * 2020-08-28 2022-03-03 华为技术有限公司 一种芯片封装结构、电子设备及芯片封装结构的制备方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201911508A (zh) * 2017-08-02 2019-03-16 矽品精密工業股份有限公司 電子封裝件
US10361158B2 (en) * 2017-08-29 2019-07-23 Micron Technology, Inc. Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch
US10665522B2 (en) * 2017-12-22 2020-05-26 Intel IP Corporation Package including an integrated routing layer and a molded routing layer
US10699980B2 (en) * 2018-03-28 2020-06-30 Intel IP Corporation Fan out package with integrated peripheral devices and methods
US11133282B2 (en) * 2019-05-31 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. COWOS structures and methods forming same
TWI734455B (zh) 2019-10-09 2021-07-21 財團法人工業技術研究院 多晶片封裝件及其製造方法
TWI785371B (zh) * 2020-08-25 2022-12-01 矽品精密工業股份有限公司 電子封裝件及其製法
US20220165648A1 (en) * 2020-11-11 2022-05-26 Nepes Co., Ltd. Semiconductor package and method for manufacturing the same
TWI751052B (zh) * 2021-03-16 2021-12-21 力成科技股份有限公司 半導體封裝結構及其製法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150084206A1 (en) * 2013-09-24 2015-03-26 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Dual Fan-Out Semiconductor Package
CN104752236A (zh) * 2013-12-30 2015-07-01 台湾积体电路制造股份有限公司 用于封装应用的两步模塑研磨
US20150255361A1 (en) * 2014-03-04 2015-09-10 Amkor Technology, Inc. Semiconductor device with thin redistribution layers

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3798597B2 (ja) * 1999-11-30 2006-07-19 富士通株式会社 半導体装置
US7550857B1 (en) 2006-11-16 2009-06-23 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package
US8421244B2 (en) * 2007-05-08 2013-04-16 Samsung Electronics Co., Ltd. Semiconductor package and method of forming the same
KR101486420B1 (ko) * 2008-07-25 2015-01-26 삼성전자주식회사 칩 패키지, 이를 이용한 적층형 패키지 및 그 제조 방법
US9064936B2 (en) * 2008-12-12 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US9082806B2 (en) * 2008-12-12 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US8754514B2 (en) * 2011-08-10 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip wafer level package
US9378982B2 (en) 2013-01-31 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
US9087832B2 (en) 2013-03-08 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage reduction and adhesion improvement of semiconductor die package
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9570421B2 (en) 2013-11-14 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure
JP2015135869A (ja) * 2014-01-16 2015-07-27 株式会社テラプローブ 半導体装置、及び半導体装置の製造方法
US9373604B2 (en) 2014-08-20 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for wafer level package and methods of forming same
TWI548043B (zh) * 2014-11-17 2016-09-01 矽品精密工業股份有限公司 封裝結構及其製法
US10068853B2 (en) * 2016-05-05 2018-09-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150084206A1 (en) * 2013-09-24 2015-03-26 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Dual Fan-Out Semiconductor Package
CN104752236A (zh) * 2013-12-30 2015-07-01 台湾积体电路制造股份有限公司 用于封装应用的两步模塑研磨
US20150255361A1 (en) * 2014-03-04 2015-09-10 Amkor Technology, Inc. Semiconductor device with thin redistribution layers

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI733039B (zh) * 2018-05-11 2021-07-11 日月光半導體製造股份有限公司 半導體基板及其製造方法
CN111128937A (zh) * 2018-10-30 2020-05-08 三星电子株式会社 半导体封装件
CN111128937B (zh) * 2018-10-30 2024-04-30 三星电子株式会社 半导体封装件
WO2021037233A1 (zh) * 2019-08-30 2021-03-04 天芯互联科技有限公司 封装体及其制备方法
WO2022041159A1 (zh) * 2020-08-28 2022-03-03 华为技术有限公司 一种芯片封装结构、电子设备及芯片封装结构的制备方法

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