CN107769777B - Frequency divider with selectable divisor and frequency dividing method thereof - Google Patents
Frequency divider with selectable divisor and frequency dividing method thereof Download PDFInfo
- Publication number
- CN107769777B CN107769777B CN201710888959.7A CN201710888959A CN107769777B CN 107769777 B CN107769777 B CN 107769777B CN 201710888959 A CN201710888959 A CN 201710888959A CN 107769777 B CN107769777 B CN 107769777B
- Authority
- CN
- China
- Prior art keywords
- divisor
- phase
- selection controller
- output
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The invention relates to the field of frequency dividers, in particular to a frequency divider with a selectable divisor and a frequency dividing method thereof, which comprise an input and output part and a control part, wherein the input and output part comprises a phase selector, a buffer and a frequency divider which are sequentially connected; the control part comprises a delta-sigma modulator, a divisor selection controller and a phase selection controller which are connected in sequence; the divider with the selectable divisor and the frequency dividing method thereof solve the problems of expandability and portability based on the phase rotation delta-sigma divider at present, and are particularly suitable for occasions needing to switch frequency dividing coefficients in real time and change output frequency.
Description
Technical Field
The invention relates to the technical field of frequency dividers, in particular to a frequency divider with a selectable divisor and a frequency dividing method thereof.
Background
Conventional phase-locked loops (PLLs) are largely classified into two major categories, the first category being Integer-type PLLs (Integer PLLs) and the second category being Fractional-N PLLs (Fractional-N PLLs). The integer PLL only outputs an integer multiple of the reference frequency by using an integer frequency divider, and if a more accurate frequency needs to be output, the reference input frequency needs to be reduced, and the resolution of the frequency needs to be improved. However, for the PLL, 1/10 of the reference frequency is generally designed as the loop bandwidth of the PLL, and if the reference frequency is lowered, the bandwidth of the PLL is lowered, which increases the phase noise of the Voltage Controlled Oscillator (VCO), and at the same time, requires a large capacitor in the loop filter, increasing the chip area. The fractional PLL controls the feedback frequency divider by using the delta-sigma modulator, so that the frequency divider generates a divisor between N and N +1, because the delta-sigma modulator pushes the quantization noise to a high frequency, and then the quantization noise is filtered by the loop filter, the fractional PLL can use a higher reference frequency, the loop bandwidth is not limited, but the modulation capability of the delta-sigma modulator is limited, and the filtering of the quantization noise still limits the further improvement of the loop bandwidth. The frequency divider includes: first and second divide-by-2 circuits (A; B), wherein the second divide-by-2 circuit (B) is coupled to an output of the first divide-by-2 circuit (A) and at least the second divide-by-2 circuit (B) includes four phase outputs each 90 DEG apart. Providing a Phase Selection Unit (PSU) for selecting one of the four phase outputs (Ip, In, Qp, Qn; INi, INni, INq, INnq) of the second divide-by-2 circuit (B); furthermore, a phase control unit (RTU) is provided for supplying control signals (C0, NC 0; C1, NC 1; C2, NC2) to the phase selection unit, wherein the Phase Selection Unit (PSU) performs the selection of the four phase outputs (Ip, In, Qp, Qn; INi, INni, INq, INnq) In dependence on the control signals (C0, NC 0; C1, NC 1; C2, NC 2); the Phase Selection Unit (PSU) is implemented according to control logic.
To improve the noise shaping effect of a conventional delta-sigma modulator, an effective method is to use a phase rotation (phase rotation) based modulator and increase the sampling frequency of the delta-sigma modulator. Therefore, the quantization noise can be pushed to a higher frequency while the quantization noise is greatly reduced, the limitation on the loop bandwidth can be further relaxed, and the quantization noise of the modulator, the phase noise of the VCO and the chip area have a relatively balanced result. However, the traditional delta-sigma modulator based on phase rotation is realized by adopting an analog mode, has poor expansibility and portability, and cannot adapt to a special PLL (phase locked loop) needing real-time accurate frequency hopping.
Disclosure of Invention
The invention aims to provide a frequency divider capable of randomly selecting a divisor and a frequency dividing method thereof, solves the problems of expandability and portability of the existing delta-sigma frequency divider based on phase rotation, and is particularly suitable for occasions needing to switch frequency dividing coefficients in real time and change output frequency.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a divider with selectable divisor, characterized by: the input and output part comprises a phase selector, a buffer and a frequency divider which are connected in sequence, and the input phase is input by the phase selector and output to the frequency divider through the buffer; the control part comprises a delta-sigma modulator, a divisor selection controller and a phase selection controller which are connected in sequence; the frequency divider provides the output clock signal and the reset signal to the delta-sigma modulator and the divisor selection controller respectively, the clock signal after passing through the buffer is provided to the phase selection controller and the divisor selection controller, and the phase selection controller sends a control signal to the phase selector.
The input of the delta-sigma modulator further comprises input points for a preset divisor setting K, M and PHSEL, and the output of the delta-sigma modulator further comprises a test signal output point.
A method of dividing a frequency by a selectable divisor, comprising:
the phase selector selects one from the input phases and outputs the selected phase to the buffer for buffering and shaping, and then the buffer outputs the buffering result to the frequency eliminator, the divisor selection controller and the phase selection controller;
the frequency eliminator divides the frequency of the buffering result and outputs the result, and provides a reset signal as a control signal to feed back to the divisor selection controller and a clock signal to the delta-sigma modulator;
the divisor selection controller outputs a control signal to the phase selection controller according to the control signal output by the delta-sigma modulator and the reset signal output by the frequency eliminator;
the phase selection controller outputs a phase selection control signal to the phase selector according to the control signal output by the divisor selection controller, and controls the phase selector to select a corresponding phase, so that the divisor frequency division is selected circularly.
The buffer outputs the buffering result to the divisor selection controller and the phase selection controller as the clock of the digital circuit of the divisor selection controller and the phase selection controller; the result of the buffering output by the buffer to the frequency divider is a buffered and shaped phase.
The output of the frequency eliminator after frequency elimination is the clock signal which is output finally; the frequency divider provides a clock signal to the delta-sigma modulator as a clock for the digital circuit; the frequency divider outputs a reset signal for resetting to the output selection controller.
The reset signal enables the divisor selection controller to repeat the previous actions when the divisor selection controller counts the corresponding value, and the function of circularly controlling phase selection is realized.
The delta-sigma modulator generates a signal DIV _ CTL for output to the divisor selection controller and a test signal SDMOUT for delta-sigma modulator test based on its preset divisor setting K, M and PHSEL value.
The invention has the following beneficial effects:
the invention provides a frequency divider with a selectable divisor, a plurality of input phases enter a phase selector, the phase selector is actually equivalent to a multi-input MUX (multiplexer) selection circuit, only one bit of a control pulse of the phase selector is high at any moment, and only one phase passes through the phase selector at any moment; the buffer shapes the phase information output by the phase selector to improve the driving capability; the frequency eliminator is a programmable frequency eliminator, the frequency eliminating coefficient of the frequency eliminator is directly controlled by an external register, the specific realization is realized in a counter form, after the actual frequency eliminating coefficient N.f is switched by phases, only the number of rising edges is counted here to complete the integer frequency elimination of N +1, the actual frequency eliminating coefficient of N.f is finally obtained, and the value of the counter needs to be output to a divisor selection controller module; the delta-sigma modulator adopts a single-loop architecture, the output range of the single-loop architecture is smaller, and the reliability of fractional frequency division operation of a phase rotation architecture is better.
Secondly, the divider with selectable divisor provided by the invention adopts a two-stage delta-sigma modulator, 2bit quantization bit width is adopted, the divisor 0.f of the decimal part of the actual divisor N.f is set by two inputs K and M of the delta-sigma modulator, the selection control range of the divisor is fixed within the range of (0.f-0.1) — (0.f +0.3) according to the size of 0.f, the selection of the control range of the divisor is set by PHSEL [3:0], because our delta-sigma modulator has only two bit quantized outputs, we only need to set the control range of the divisor within the range of 0-0.4, after K, M, PHSEL is set according to the actual divisor value n.f, the output of the delta-sigma modulator is the control signal for controlling the change of the divisor range from (n.f-0.1) to (n.f +0.3), and the average value of the changed divisor range is exactly equal to f.
Thirdly, the invention provides a divisor-selectable frequency dividing method, the input signal is a plurality of phases with equal intervals, the selection input signal of the phase selector is controlled by the phase selection controller, one phase output is selected, then the selected phase output enters a buffer, the phase is transmitted to the integer frequency divider, the divisor selection controller and the phase selection controller through the shaping of the buffer, the output of the buffer is sent to the divisor selection controller and the phase selection controller as the clock of the digital circuit, the phase of the integer frequency divider is the phase which needs to be divided finally, the output CKOUT after the frequency division of the integer frequency divider is the clock signal after the frequency division, and the clock signal is used as the clock of the digital circuit of the delta-sigma modulator, in addition, the integer frequency divider provides a reset signal COUNTER for the output selection controller, the reset signal is the action before the divisor selection controller repeats when the divisor selection controller counts to the corresponding value, the PH _ CTL is input to the phase selection controller, and after certain logic processing, a multi-bit control signal is output to the phase selector, so that correct phase selection is realized.
The present invention provides a divisor-selectable frequency division method, wherein K, M, PHSEL is a preset divisor setting value according to specific needs, and it generates two signals, one is DIV _ CTL, this control signal is used as an input signal of the divisor selection controller, and after logic processing, PH _ CTL is generated to the phase selection controller, and SDMOUT is used as a test signal to test the working state of the delta-sigma modulator.
The frequency division method with the selectable divisor provided by the invention is completely realized by adopting a verilog code mode, supports any divisor above 2, and adopts a phase-rotation mode consisting of ten phases to ensure that the divisor can be accurate to 0.1, so that the method is better than the quantization noise optimization of the traditional decimal frequency divider, reduces the requirement of the bandwidth of PLL, has a very wide application range and has very good portability.
Drawings
FIG. 1 is a schematic diagram of a preferred embodiment of the frequency divider of the present invention;
FIG. 2 is a schematic diagram of a preferred embodiment of the input phase of the present invention;
FIG. 3 is a schematic diagram of a phase selection controller in accordance with a preferred embodiment of the present invention;
FIG. 4 is a schematic phase diagram of a preferred embodiment of the present invention;
FIG. 5 is a schematic diagram of a preferred embodiment of the phase switching of the present invention;
FIG. 6 is a schematic diagram of another preferred embodiment of the phase switching of the present invention;
Detailed Description
The technical solutions for achieving the objects of the present invention are further illustrated by the following specific examples, which should be construed as including but not limited to the following examples.
Example 1
Referring to fig. 1, a divider with a selectable divisor comprises an input/output portion and a control portion, wherein the input/output portion comprises a phase selector, a buffer and a divider which are connected in sequence, an input phase is input by the phase selector, and is output to the divider through the buffer; the control part comprises a delta-sigma modulator, a divisor selection controller and a phase selection controller which are connected in sequence; and the frequency divider provides the output phase to the delta-sigma modulator and the divisor selection controller, the buffer provides its output result to the phase selection controller and the divisor selection controller, and the phase selection controller sends a control signal to the phase selector.
This is the most basic embodiment of a divider with a selectable divisor according to the present invention. A plurality of input phases enter a phase selector, the phase selector is actually equivalent to a multi-input MUX (multiplexer) selection circuit, and only one bit of a control pulse of the phase selector is high at any moment, so that only one phase passes through the phase selector at any moment; the buffer shapes the phase information output by the phase selector to improve the driving capability; the frequency eliminator is a programmable frequency eliminator, the frequency eliminating coefficient of the frequency eliminator is directly controlled by an external register, the specific realization is realized in a counter form, after the actual frequency eliminating coefficient N.f is switched by phases, only the number of rising edges is counted here to complete the integer frequency elimination of N +1, the actual frequency eliminating coefficient of N.f is finally obtained, and the value of the counter needs to be output to a divisor selection controller module; the delta-sigma modulator adopts a single-loop architecture, the output range of the single-loop architecture is smaller, and the reliability of fractional frequency division operation of a phase rotation architecture is better.
Example 2
Referring to fig. 1, a divider with a selectable divisor comprises an input/output portion and a control portion, wherein the input/output portion comprises a phase selector, a buffer and a divider which are connected in sequence, an input phase is input by the phase selector, and is output to the divider through the buffer; the control part comprises a delta-sigma modulator, a divisor selection controller and a phase selection controller which are connected in sequence; the frequency divider provides the output phase to the delta-sigma modulator and the divisor selection controller, the buffer provides the output result to the phase selection controller and the divisor selection controller, and the phase selection controller sends a control signal to the phase selector; the input of the delta-sigma modulator further comprises input points for a preset divisor setting K, M and PHSEL, and the output of the delta-sigma modulator further comprises a test signal output point.
This is a preferred embodiment of a divider with a selectable divisor according to the present invention. A plurality of input phases enter a phase selector, the phase selector is actually equivalent to a multi-input MUX (multiplexer) selection circuit, and only one bit of a control pulse of the phase selector is high at any moment, so that only one phase passes through the phase selector at any moment; the buffer shapes the phase information output by the phase selector to improve the driving capability; the frequency eliminator is a programmable frequency eliminator, the frequency eliminating coefficient of the frequency eliminator is directly controlled by an external register, the specific realization is realized in a counter form, after the actual frequency eliminating coefficient N.f is switched by phases, only the number of rising edges is counted here to complete the integer frequency elimination of N +1, the actual frequency eliminating coefficient of N.f is finally obtained, and the value of the counter needs to be output to a divisor selection controller module; the delta-sigma modulator adopts a single-loop architecture, the output range of the single-loop architecture is smaller, and the reliability of fractional frequency division operation of a phase rotation architecture is better; the method is characterized in that a two-stage delta-sigma modulator is adopted, 2-bit quantization bit width is adopted, the divisor 0.f of a decimal part of an actual divisor N.f is set by two inputs K and M of the delta-sigma modulator, the selection control range of the divisor is fixed within the range of (0.f-0.1) to (0.f +0.3) according to the size of 0.f, the selection of the control range of the divisor is set by PHSEL [3:0], because the delta-sigma modulator only has two-bit quantization output, the control range of the divisor is only required to be set within the range of 0-0.4, after K, M, PHSEL is set according to the actual divisor value N.f, the output of the delta-sigma modulator is a control signal for controlling the divisor range to change from (N.f-0.1) to (N.f +0.3), and the average value of the changed divisor range is just equal to f.
Example 3
Referring to fig. 1 to 6, a divisor-selectable frequency division method:
the phase selector selects one from the input phases and outputs the selected phase to the buffer for buffering and shaping, and then the buffer outputs the buffering result to the frequency eliminator, the divisor selection controller and the phase selection controller;
the frequency eliminator divides the frequency of the buffering result and outputs the result, and provides a reset signal as a control signal to feed back to the divisor selection controller and a clock signal to the delta-sigma modulator;
the divisor selection controller outputs a control signal to the phase selection controller according to the control signal output by the delta-sigma modulator and the reset signal output by the frequency eliminator;
the phase selection controller outputs a phase selection control signal to the phase selector according to the control signal output by the divisor selection controller, and controls the phase selector to select a corresponding phase, so that the divisor frequency division is selected circularly.
This is the most basic embodiment of the divide-by-number alternative divide-by-frequency method of the present invention. The input signal is a plurality of phases with equal intervals, the selection input signal of the phase selector is controlled by the phase selection controller to select one phase to be output, then the selected phase enters a buffer, the shaping of the buffer is used for retransmitting the phase to the integer frequency divider, the divisor selection controller and the phase selection controller, wherein the output of the buffer is sent to the divisor selection controller and the phase selection controller to be used as the clock of a digital circuit, the phase of the integer frequency divider is the phase which needs to be divided completely, the output CKOUT after the frequency division of the integer frequency divider is the clock signal after the frequency division, and the clock signal is used as the clock of the digital circuit of the delta-sigma modulator for use, in addition, the integer frequency divider provides a reset signal COUNTER for the output selection controller, and the reset signal is used for enabling the divisor selection controller to repeat the previous action when the divisor selection controller counts to the corresponding value, the PH _ CTL is input to the phase selection controller, and after certain logic processing, a multi-bit control signal is output to the phase selector, so that correct phase selection is realized.
Example 4
Referring to fig. 1 to 6, a divisor-selectable frequency division method:
the phase selector selects one from the input phases and outputs the selected phase to the buffer for buffering and shaping, and then the buffer outputs the buffering result to the frequency eliminator, the divisor selection controller and the phase selection controller;
the frequency eliminator divides the frequency of the buffering result and outputs the result, and provides a reset signal as a control signal to feed back to the divisor selection controller and a clock signal to the delta-sigma modulator;
the divisor selection controller outputs a control signal to the phase selection controller according to the control signal output by the delta-sigma modulator and the reset signal output by the frequency eliminator;
the phase selection controller outputs a phase selection control signal to the phase selector according to the control signal output by the divisor selection controller, and controls the phase selector to select a corresponding phase, so that the divisor frequency division is selected circularly;
the buffer outputs the buffering result to the divisor selection controller and the phase selection controller as the clock of the digital circuit of the divisor selection controller and the phase selection controller; the buffer result output to the frequency eliminator by the buffer is the phase after buffering and shaping;
the output of the frequency eliminator after frequency elimination is the clock signal which is output finally; the frequency divider provides a clock signal to the delta-sigma modulator as a clock for the digital circuit; the frequency divider outputs a reset signal for resetting to the output selection controller;
the reset signal enables the divisor selection controller to repeat the previous actions when the divisor selection controller counts the corresponding value, thereby realizing the function of circularly controlling phase selection;
the delta-sigma modulator generates a signal DIV _ CTL for output to the divisor selection controller and a test signal SDMOUT for delta-sigma modulator test based on its preset divisor setting K, M and PHSEL value.
This is a preferred embodiment of a divisor-selectable frequency division method of the present invention. The input signal is a plurality of phases with equal intervals, the selection input signal of the phase selector is controlled by the phase selection controller to select one phase to be output, then the selected phase enters a buffer, the shaping of the buffer is used for retransmitting the phase to the integer frequency divider, the divisor selection controller and the phase selection controller, wherein the output of the buffer is sent to the divisor selection controller and the phase selection controller to be used as the clock of the digital circuit, the phase of the integer frequency divider is the phase which needs to be divided completely, the output CKOUT after the frequency division of the integer frequency divider is the clock signal after the frequency division, and is used as the clock of the digital circuit of the delta-sigma modulator for use, in addition, the integer frequency divider provides a reset signal COUNTER for the output selection controller, and the reset signal is the action before the divisor selection controller repeats when the integer frequency division is counted to the corresponding value, the function of circularly controlling phase selection is realized, PH _ CTL is input to a phase selection controller, and after certain logic processing, a multi-bit control signal is output to a phase selector to realize correct phase selection; K. m, PHSEL is a preset divisor setting value according to the specific requirement, it generates two signals, one is DIV _ CTL, this control signal is used as the input signal of the divisor selection controller, through the logic processing, PH _ CTL is generated to the phase selection controller, SDMOUT is used as the test signal, the working state of the delta-sigma modulator is tested; the method is completely realized by adopting a verilog code mode, supports any divisor with more than 2, and adopts a phase-rotation mode consisting of ten phases to ensure that the divisor can be accurate to 0.1, so that the method is better than the quantization noise optimization of the traditional decimal frequency divider, reduces the requirement on the bandwidth of PLL, has a very wide application range and has very good portability.
Example 5
Referring to FIGS. 1 to 6, the input signal is 10 clocks CKIN [9:0] of equal interval phase, the input clock signal is controlled by PH _ SEL [9:0], one of the clocks is selected to be output, then enters a buffer, and is then transmitted to the integer frequency divider, the divisor selection controller and the phase selection controller through the shaping of the buffer, wherein the output of the buffer is sent to the divisor selection controller and the phase selection controller as the clock of the digital circuit, the clock of the integer frequency divider is the clock which needs to be divided at last, the output CKOUT after the integer frequency divider is the divided clock signal and is used as the clock of the digital circuit of the delta-sigma modulator, K, M, PHSEL are values set according to the specific required divisor register, which generates two signals, one is DIV _ CTL, and the control signal is used as the input signal of the divisor selection controller, the integer frequency divider provides a reset signal COUNTER to the output selection controller, the reset signal is to make the divisor selection controller repeat the previous action when counting to the corresponding value, so as to realize the function of circularly controlling phase selection, the PH _ CTL is input to the phase selection controller, and after certain logic processing, a 10-bit control signal is output to the phase selector, so as to realize correct phase selection.
The 10 phase input clock goes to the phase selector, which is effectively equivalent to a 10 input MUX select circuit, at any time PH _ SEL [9:0]]Only one bit is high, ensuring that only one phase passes through the phase selector at any time. The buffer shapes the phase information output from the phase selector to improve the drive (drive) capability. The integer frequency eliminator is a programmable integer frequency eliminator, the frequency eliminating coefficient of the integer frequency eliminator is directly controlled by an external register, the specific implementation is realized in a counter form, after the actual frequency eliminating coefficient N.f is switched by phase, only the number of rising edges is counted, the integer frequency elimination of N +1 is completed, the actual N.f frequency eliminating coefficient is finally obtained, and the value of the counter needs to be output to a divisor selection controller module. The delta-sigma modulator adopts a single-loop architecture, the output range of the single-loop architecture is smaller, and the delta-sigma modulator is used for fractional frequency division operation of a phase rotation architectureThe reliability is better, the two-stage delta-sigma modulator is adopted in the embodiment, the 2-bit quantization bit width is adopted, the divisor 0.f of the decimal part of the actual divisor N.f is set by two inputs K and M of the delta-sigma modulator, the selection control range of the divisor is fixed within the range of (0.f-0.1) to (0.f +0.3) according to the size of 0.f, and the selection of the control range of the divisor is PHSEL [3:0]]Setting is given, because the delta-sigma modulator only has two-bit quantized output, the control range of the divisor is only required to be set within the range of 0-0.4, after K, M, PHSEL is set according to the actual divisor value N.f, the output of the delta-sigma modulator is the control signal for controlling the divisor range to change from (N.f-0.1) to (N.f +0.3), and the average value of the changed divisor range is just equal to f.
| {PHSEL,SDMOUT} | DIV_CTL | DIV NUMBER |
| 000000~000011 | 1000~1011 | (N-2).8~(N-1).1 |
| 000100~000111 | 0111~1010 | (N-2).9~(N-1).2 |
| 001000~001011 | 0110~1001 | (N-1).0~(N-1).3 |
| 001100~001111 | 0101~1000 | (N-1).1~(N-1).4 |
| 010000~010011 | 0100~0111 | (N-1).2~(N-1).5 |
| 010100~010111 | 0011~0110 | (N-1).3~(N-1).6 |
| 011000~011011 | 0010~0101 | (N-1).4~(N-1).7 |
| 011100~011111 | 0001~0100 | (N-1).5~(N-1).8 |
| 100000~100011 | 0000~0011 | (N-1).6~(N-1).9 |
| 100100~100111 | 1100~0010 | (N-1).7~N.0 |
The control signals in the table correspond to actual divisors one by one, the second-order delta-sigma modulator outputs at most four control signals, the four control signals correspond to (n.f-0.1) to (n.f +0.3) four divisors, and N can be set correspondingly according to a required value. This is the case when the actual divisor decimal point is followed by more than 1 bit, and when the actual divisor decimal point is followed by less than or equal to 1 bit, such as N.0 or n.1-N.9, then the delta-sigma modulator does not need to work, and only needs to output the corresponding divisor control signal by judging PHSEL:
| PHSEL | DIV_CTL | DIV NUMBER |
| 0000 | 1011 | (N-2).8 |
| 0001 | 1010 | (N-2).9 |
| 0010 | 1001 | (N-1).0 |
| 0011 | 1000 | (N-1).1 |
| 0100 | 0111 | (N-1).2 |
| 0101 | 0110 | (N-1).3 |
| 0110 | 0101 | (N-1).4 |
| 0111 | 0100 | (N-1).5 |
| 1000 | 0011 | (N-1).6 |
| 1001 | 0010 | (N-1).7 |
| 1010 | 0001 | (N-1).8 |
| 1011 | 0000 | (N-1).9 |
| Other | 1100 | N.0 |
the output selection controller is a set of combinational logic circuits, and assigns a set of values given in advance to PH _ CTL directly according to the condition of the input set value, COUNTER is outputted from the integer frequency divider, is supplied to the divisor selection controller, generates a clock signal of the cyclic phase control signal, in a period from 1 counting to N +1 counting of COUNTER, the divisor selection controller outputs the corresponding N +1 sets of 2-bit phase control signals, the N +1 sets of two-bit phase control signals are output in a cycle following the cycle, the phase control signal in each cycle controlling the amount by which the phase in each cycle is shifted forward, then evenly distributing the phase positions to N +1 periods, and evenly distributing the advancing total amount of the phase positions can improve the working frequency of the circuit to the maximum extent and adapt to more high-speed occasions. PH _ SEL will output 6 groups of 2-bit control signals when N >5, then output 6 groups of 2-bit control signals in turn synchronously with the COUNTER value, and output corresponding N groups of 2-bit control signals when N < =5, and output N groups of 2-bit control signals in turn synchronously with the COUNTER value.
The specific conversion relationship is as follows:
| DIV_CTL | DIV NUMBER | PH_CTL |
| 1011 | (N-2).8 | 10→10→10→10→10→10 |
| 1010 | (N-2).9 | 01→10→10→10→10→10 |
| 1001 | (N-1).0 | 01→10→10→01→10→10 |
| 1000 | (N-1).1 | 01→01→10→01→10→10 |
| 0111 | (N-1).2 | 01→01→10→01→01→10 |
| 0110 | (N-1).3 | 01→01→01→01→01→10 |
| 0101 | (N-1).4 | 01→01→01→01→01→01 |
| 0100 | (N-1).5 | 00→01→01→01→01→01 |
| 0011 | (N-1).6 | 00→01→01→00→01→01 |
| 0010 | (N-1).7 | 00→00→01→00→01→01 |
| 0001 | (N-1).8 | 00→00→01→00→00→01 |
| 0000 | (N-1).9 | 00→00→00→00→00→01 |
| 1100 | N.0 | 00→00→00→00→00→00 |
N>PH _ CTL corresponds to the setting value of the corresponding divisor at 5
| DIV_CTL | DIV NUMBER | PH_CTL |
| 1011 | 3.8 | 10→00→00→00→01 |
| 1010 | 3.9 | 00→01→00→00→01 |
| 1001 | 4.0 | 00→01→00→01→01 |
| 1000 | 4.1 | 01→01→00→01→01 |
| 0111 | 4.2 | 01→01→01→01→01 |
| 0110 | 4.3 | 01→01→01→01→01 |
| 0101 | 4.4 | 01→01→01→01→10 |
| 0100 | 4.5 | 01→10→01→01→10 |
| 0011 | 4.6 | 01→10→01→10→10 |
| 0010 | 4.7 | 10→10→01→10→10 |
| 0001 | 4.8 | 10→10→10→10→10 |
| 0000 | 4.9 | 10→10→10→10→10 |
| 1100 | 5.0 | 00→00→00→00→00 |
Setting value of PH _ CTL corresponding to corresponding divisor when N =5
| DIV_CTL | DIV NUMBER | PH_CTL |
| 1011 | 2.8 | 11→11→11→11 |
| 1010 | 2.9 | 10→11→11→11 |
| 1001 | 3.0 | 10→11→10→11 |
| 1000 | 3.1 | 10→10→10→11 |
| 0111 | 3.2 | 10→10→10→10 |
| 0110 | 3.3 | 01→10→10→10 |
| 0101 | 3.4 | 01→10→01→10 |
| 0100 | 3.5 | 01→01→01→10 |
| 0011 | 3.6 | 01→01→01→01 |
| 0010 | 3.7 | 00→01→01→01 |
| 0001 | 3.8 | 00→01→00→01 |
| 0000 | 3.9 | 00→00→00→01 |
| 1100 | 4.0 | 00→00→00→00 |
Setting value of PH _ CTL corresponding to corresponding divisor when N =4
| DIV_CTL | DIV NUMBER | PH_CTL |
| 1011 | 1.8 | 00→00→01 |
| 1010 | 1.9 | 00→00→01 |
| 1001 | 2.0 | 00→01→01 |
| 1000 | 2.1 | 11→11→11 |
| 0111 | 2.2 | 11→10→11 |
| 0110 | 2.3 | 10→10→11 |
| 0101 | 2.4 | 10→10→10 |
| 0100 | 2.5 | 10→01→10 |
| 0011 | 2.6 | 01→01→10 |
| 0010 | 2.7 | 01→01→01 |
| 0001 | 2.8 | 01→00→01 |
| 0000 | 2.9 | 00→00→01 |
| 1100 | 3.0 | 00→00→00 |
Setting value of PH _ CTL corresponding to corresponding divisor when N =3
The phase selection controller is actually a 10-bit shift register, the initial value is 1000000000, the number of bits of backward movement of the high level position is controlled by an output signal PH _ CTL of the divisor selection controller, an EN signal of the DFF is judged by dividing a 12-bit control signal into 6 times, the EN initial voltage is low, 00 keeps enabling signals EN to be one clock cycle low, the position of the high level of PH _ SEL [9:0] keeps one cycle, 01 pulls up enabling signals EN for one clock cycle, one high level shift bit is enabled, 10 pulls up enabling signals EN for two clock cycles, two high level shift bits are enabled, 11 pulls up enabling signals EN for three cycles, three high level shift bits are enabled, the cycle of the high level in the 10-bit control signal appears, and only one bit is enabled to be high.
By directly controlling the MUX circuit with the value of the shift register shown in fig. 4, the corresponding phase component can be selected to pass through the MUX circuit, thereby implementing fractional frequency division based on phase rotation.
Claims (3)
1. A divider with selectable divisor, characterized by: the input and output part comprises a phase selector, a buffer and a frequency divider which are connected in sequence, and the input phase is input by the phase selector and output to the frequency divider through the buffer; the control part comprises a delta-sigma modulator, a divisor selection controller and a phase selection controller which are connected in sequence; the frequency divider provides output phase to the delta-sigma modulator and the divisor selection controller, the buffer provides output results to the phase selection controller and the divisor selection controller, the phase selection controller sends control signals to the phase selector, the input end of the delta-sigma modulator also comprises preset divisor set values K, M and input points of PHSEL, the divisor 0.f of the decimal part of the actual divisor N.f is set by two inputs K and M of the delta-sigma modulator, the selection control range of the divisor is fixed within the range of (0.f-0.1) ~ (0.f +0.3) according to the size of 0.f, the control range of the preset divisor set value PHSEL is set within the range of [3:0], the control range of the divisor is set within the range of 0-0.4, and after K, M, PHSEL is set according to the actual divisor value N.f, the output of the delta-sigma modulator is the control divisor range from (N.f-0.1) ~ (N.3 +0.3) A varying control signal, the average of this varying divisor range being exactly equal to f; the output of the delta-sigma modulator further comprises a test signal output point.
2. A method of dividing a frequency by a selectable divisor, comprising:
the phase selector selects one from the input phases and outputs the selected phase to the buffer for buffering and shaping, and then the buffer outputs the buffering result to the frequency eliminator, the divisor selection controller and the phase selection controller;
the frequency eliminator divides the frequency of the buffering result and outputs the result, and provides a reset signal as a control signal to feed back to the divisor selection controller and a clock signal to the delta-sigma modulator; the delta-sigma modulator generates a signal DIV _ CTL used for outputting to the divisor selection controller according to a preset divisor set value K, M and a PHSEL value, and a test signal SDMOUT used for testing the delta-sigma modulator, wherein the divisor 0.f of the decimal part of an actual divisor N.f is set by two inputs K and M of the delta-sigma modulator, the selection control range of the divisor is fixed within the range of (0.f-0.1) to (0.f +0.3) according to the size of 0.f, the control range of the preset divisor set value PHSEL is set within the range of [3:0], the control range of the divisor is set within the range of 0-0.4, after K, M, PHSEL is set according to the actual divisor value N.f, the output of the delta-sigma modulator is a control signal for controlling the divisor range to change from (N.f-0.1) to (N.f +0.3), the average of this varying divisor range is just equal to f;
the divisor selection controller outputs a control signal to the phase selection controller according to the control signal output by the delta-sigma modulator and the reset signal output by the frequency eliminator;
the phase selection controller outputs a phase selection control signal to the phase selector according to the control signal output by the divisor selection controller, and controls the phase selector to select a corresponding phase, so that the divisor frequency division is selected circularly;
the buffer outputs the buffering result to the divisor selection controller and the phase selection controller as the clock of the digital circuit of the divisor selection controller and the phase selection controller; the buffer result output to the frequency eliminator by the buffer is the phase after buffering and shaping;
the output of the frequency eliminator after frequency elimination is the clock signal which is output finally; the frequency divider provides a clock signal to the delta-sigma modulator as a clock for the digital circuit; the frequency divider outputs a reset signal for resetting to the output selection controller.
3. A method of dividing frequencies by a selectable divisor as claimed in claim 2, wherein: the reset signal enables the divisor selection controller to repeat the previous actions when the divisor selection controller counts the corresponding value, and the function of circularly controlling phase selection is realized.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710888959.7A CN107769777B (en) | 2017-09-27 | 2017-09-27 | Frequency divider with selectable divisor and frequency dividing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710888959.7A CN107769777B (en) | 2017-09-27 | 2017-09-27 | Frequency divider with selectable divisor and frequency dividing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107769777A CN107769777A (en) | 2018-03-06 |
| CN107769777B true CN107769777B (en) | 2021-09-24 |
Family
ID=61266754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710888959.7A Active CN107769777B (en) | 2017-09-27 | 2017-09-27 | Frequency divider with selectable divisor and frequency dividing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107769777B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104184461A (en) * | 2014-08-20 | 2014-12-03 | 上海交通大学 | Fractional frequency divider |
| CN106209093A (en) * | 2016-03-02 | 2016-12-07 | 北京大学 | A kind of digital fractional frequency-division phase-locked loop structure |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI371923B (en) * | 2009-01-21 | 2012-09-01 | Univ Nat Taiwan | Phase locked loop |
| US8587352B2 (en) * | 2011-09-16 | 2013-11-19 | Infineon Technologies Austria Ag | Fractional-N phase locked loop |
| TWI551054B (en) * | 2014-09-23 | 2016-09-21 | 智原科技股份有限公司 | Clock generating apparatus and fractional frequency divider thereof |
| EP3276832B1 (en) * | 2015-04-15 | 2019-03-13 | Mitsubishi Electric Corporation | Synthesizer |
| WO2017105349A1 (en) * | 2015-12-16 | 2017-06-22 | Agency For Science, Technology And Research | Frequency synthesizers and methods for synthesizing a frequency |
-
2017
- 2017-09-27 CN CN201710888959.7A patent/CN107769777B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104184461A (en) * | 2014-08-20 | 2014-12-03 | 上海交通大学 | Fractional frequency divider |
| CN106209093A (en) * | 2016-03-02 | 2016-12-07 | 北京大学 | A kind of digital fractional frequency-division phase-locked loop structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107769777A (en) | 2018-03-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101478308B (en) | Configurable frequency synthesizer circuit based on time-delay lock loop | |
| US8891725B2 (en) | Frequency divider with improved linearity for a fractional-N synthesizer using a multi-modulus prescaler | |
| CN112042125B (en) | Method and circuit for fine control of phase/frequency offset in a phase locked loop | |
| US9438257B1 (en) | Programmable frequency divider providing output with reduced duty-cycle variations over a range of divide ratios | |
| US20140306740A1 (en) | Time-interleaved multi-modulus frequency divider | |
| CN100568735C (en) | Frequency divider | |
| CN101908883B (en) | Programmable fractional frequency divider | |
| CN107888185B (en) | Fractional clock divider with direct frequency division | |
| GB2493026A (en) | Method of spreading a clock signal using a variable delay | |
| CN101378259A (en) | Phase selection programmable frequency divider | |
| CN101217277B (en) | A non-integer frequency difference eliminator and phase-lock loop that can product non-integer real-time clock signal | |
| KR20080018223A (en) | Prescaler for a fractional-n synthesizer | |
| CN107769777B (en) | Frequency divider with selectable divisor and frequency dividing method thereof | |
| CN107294531B (en) | Phase locked loop and frequency divider | |
| JP2017512446A (en) | Frequency synthesizer | |
| US10700669B2 (en) | Avoiding very low duty cycles in a divided clock generated by a frequency divider | |
| US6108393A (en) | Enhanced prescaler phase interface | |
| TWI569582B (en) | Apparatus and method for clock data recovery and phase detector | |
| EP1588488A2 (en) | Programmable dual-edge triggered counter | |
| CN104660222A (en) | Novel current-switching D-type flip-flop and five-frequency-dividing circuit | |
| US8693616B1 (en) | IC and a method for flexible integer and fractional divisions | |
| EP3235135A1 (en) | Frequency divider | |
| CN214675120U (en) | High-speed continuous integer frequency division circuit | |
| CN114095018B (en) | Decimal frequency dividing circuit | |
| CN111934681B (en) | Micro spread spectrum fractional frequency divider, phase-locked loop, chip and micro spread spectrum control method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |