CN107768428A - 一种横向双扩散金属氧化物半导体(ldmos)器件及其制造方法 - Google Patents

一种横向双扩散金属氧化物半导体(ldmos)器件及其制造方法 Download PDF

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CN107768428A
CN107768428A CN201710888508.3A CN201710888508A CN107768428A CN 107768428 A CN107768428 A CN 107768428A CN 201710888508 A CN201710888508 A CN 201710888508A CN 107768428 A CN107768428 A CN 107768428A
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艾瑞克·布劳恩
乔伊·迈克格雷格
郑志星
吉杨永
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

本发明提出了一种横向双扩散金属氧化物半导体(LDMOS)器件及其制造方法。所述横向双扩散金属氧化物半导体(LDMOS)器件在发生雪崩击穿时的最大场强位于器件表面下方的体区‑漂移区PN结处。所述横向双扩散金属氧化物半导体(LDMOS)器件包括P型体区和N型漂移区，其中P型体区由一系列的P型离子注入形成，N型漂移区由一系列的N型离子注入形成，在器件制造过程中，合理地调整P型体区和N型漂移区的离子注入浓度和深度可以实现器件的体区‑漂移区PN结处的最高浓度梯度位于器件表面下方，从而抑制热空穴在器件漏极‑门极之间的氧化层区域附近的注入和俘获，避免器件在发生击穿后的其它特性的改变。

Description

一种横向双扩散金属氧化物半导体(LDMOS)器件及其制造 方法
技术领域
本发明一般地涉及半导体器件，更具体地涉及横向双扩散金属氧化物半导体(LDMOS)器件。
背景技术
图1示出了一种传统的横向双扩散金属氧化物半导体(LDMOS)器件的横截面图。在高压应用中，当漏极D-源极S电压超过器件的雪崩击穿电压时，耗尽区的电场强度增大，可动载流子从电场中获得了足够的动能，与晶格原子的碰撞激发了电子从价带迁移到倒带，在半导体中，从电场中获得能量产生电子空穴对成为碰撞电离，由于碰撞电离产生的电子空穴对会被耗尽区的电场加速，进一步产生电子空穴，其中，电子往最高电势区 N+漏极接触区走，空穴往最低电势区P+体接触区走，如图1所示(雪崩时空穴路径11；雪崩时电子路径12)。
另外，在零电压和低门极G-源极S电压偏置时，一些由于雪崩而产生的热空穴会注入到栅氧中或者器件表面最大场强点附近的间隔(spacer)区；一些热空穴会被俘获从而导致表面最大场强的减弱和击穿电压的增大；这种现象称之为“walk-out”。除击穿电压的增大之外，“walk-out”现象通常也伴随着器件其它特性的改变，例如导通电阻的改变，而在现实应用中通常不希望出现这些器件其它特性的改变(例如导通电阻的改变)。
发明内容
针对现有技术中的一个或多个问题，本发明的一个目的是提供一种改进的横向双扩散金属氧化物半导体(LDMOS)器件。
根据本发明一实施例的一种横向双扩散金属氧化物半导体(LDMOS) 器件，包括：形成在半导体器件顶部表面的门极区；N型阱区，包括一个 N型漂移区和一个N型重掺杂漏极接触区，其中重掺杂漏极接触区位于门极区的一侧，漂移区自其顶部到底部包括具有不同掺杂浓度的上漂移区、中漂移区和下漂移区；以及P型体区，包括一个N型重掺杂源区和一个P 型重掺杂体接触区，其中P型重掺杂体接触区和大部分的N型重掺杂源区位于门极区的另一侧。
根据本发明一实施例的一种半导体器件制造方法，包括：通过一系列不同浓度的N型离子注入在半导体衬底上方的外延层中形成一个N型阱区，使得N型阱区具有变化的掺杂浓度；在外延层顶部表面形成一个门极区；在外延层中形成一个P型体区；以及在N型阱区中形成一个N型重掺杂漏极接触区，在P型体区中形成一个N型重掺杂源区和一个P型重掺杂体接触区，其中N型重掺杂漏极接触区位于门极区的一侧，P型重掺杂体接触区位于门极区的另一侧。
根据本发明一实施例的一种一种横向双扩散金属氧化物半导体 (LDMOS)器件，包括：形成在半导体器件顶部表面的门极区；N型漏区，包括一个N型漂移区和一个N型重掺杂漏极接触区，其中N型重掺杂漏极接触区位于门极区的一侧，N型漂移区由一系列不同浓度的N型离子注入形成，自N型漂移区顶部至底部具有不同浓度的离子掺杂浓度；以及P 型体区，包括一个N型重掺杂源区和一个P型重掺杂体接触区，其中P型重掺杂体接触区和大部分的N型重掺杂源区位于门极区的另一侧，N型重掺杂源区和P型重掺杂体接触区毗邻，P型体区由一系列不同浓度的P型离子注入形成，自P型体区顶部至底部具有不同浓度的离子掺杂浓度。
根据本发明提出的实施例，在不增大器件尺寸的同时，提高了器件的鲁棒性和雪崩击穿电压。
附图说明
结合附图，根据对示例性实施例的以下说明，本发明的总体构思的上述和/或其他方面将变得显而易见并更易于理解，在附图中，相同或相似的附图标记指示相同或相似的组成部分。其中：
图1示出了一种传统LDMOS器件的横截面图。
图2示出了根据本发明实施例的一种LDMOS器件100的横截面图。
图3示出了根据本发明实施例的一种LDMOS器件200的横截面图。
图4示出了图3所示LDMOS器件200的雪崩空穴路径21。
图5示出了如图3所示LDMOS器件200的掺杂浓度与深度关系图。
图6A示出了传统LDMOS器件在关断状态(当门极-漏极电压Vgs＝0) 下，器件发生雪崩击穿前后的电流-电压特性曲线Ids-Vds。
图6B示出了本发明提出的LDMOS器件在关断状态(当门极-漏极电压Vgs＝0)下，器件发生雪崩击穿前后的电流-电压特性曲线Ids-Vds。
图7A-7E示出了根据本发明实施例的一种LDMOS器件工艺制造过程中的一些横截面图。
图8示出了根据本发明实施例的一种LDMOS器件结构中通过最大场强发生点的一根分割线55。
图9示出了根据本发明实施例的沿着从器件顶部表面起始的切割线C1 上的P型体区105的掺杂浓度和深度关系图，沿着从器件顶部表面起始的切割线C2上的漂移区103的掺杂浓度和深度关系图，以及分割线55上的最大掺杂浓度所处的深度。
具体实施方式
下面将详细描述本发明的具体实施例，应当注意，这里描述的实施例只用于举例说明，并不用于限制本发明。在下面对本发明的详细描述中，为了更好地理解本发明，描述了大量的细节。然而，本领域技术人员将理解，没有这些具体细节，本发明同样可以实施。为了清晰明了地阐述本发明，本文简化了一些具体结构和功能的详细描述。此外，在一些实施例中已经详细描述过的类似的结构和功能，在其它实施例中不再赘述。尽管本发明的各项术语是结合具体的示范实施例来一一描述的，但这些术语不应理解为局限于这里阐述的示范实施方式。
图2示出了根据本发明实施例的一种LDMOS器件100的横截面图。如图2所示的LDMOS器件100包括门极区102、N型漏区和P型体区。其中门极区102形成于LDMOS器件100的表面，构成门极D；N型漏区包括漂移区103(打点的区域)和重掺杂漏极接触区104，其中重掺杂漏极接触区104位于门极区102的一侧，构成漏极D；P型体区105包括重掺杂N型源区106和重掺杂P型体接触区107，其中重掺杂P型体接触区107 和大部分的源区106位于门极区102的另一侧，构成源极S。如图2所示的实施例，漂移区103自顶部到底部包括具有不同掺杂浓度的上漂移区N1、中漂移区N2和下漂移区N3，其中中漂移区N2的掺杂浓度高于上漂移区 N1和下漂移区N3的掺杂浓度，从中漂移区N2到上漂移区N1的掺杂浓度呈递减状态，从中漂移区N2到下漂移区N3的掺杂浓度也呈递减状态。
如图2所示实施例，LDMOS器件100还包括衬底101、源极S和漏极 D，其中源极S与源区106和体接触区107接触，漏极D与漏极接触区104 接触。
图3示出了根据本发明实施例的一种LDMOS器件200的横截面图。如图3所示的LDMOS器件200与如图2所示的LDMOS器件100的不同之处在于：体区105自顶部到底部包括具有不同掺杂浓度的上体区P1、中体区P2和下体区P3；其中，中体区P2的掺杂浓度高于上体区P1和下体区P3的掺杂浓度，从中体区P2到上体区P1的掺杂浓度呈递减状态，从中体区P2到下体区P3的掺杂浓度也呈递减状态。
图4示出了图3所示LDMOS器件200的雪崩空穴路径21。由于漂移区103是由一系列不同掺杂浓度的N型区组成，体区105是由一系列不同掺杂浓度的P型区组成，并且中漂移区N2和中体区P2分别是漂移区103 和体区105中掺杂浓度最高的区域，所以雪崩空穴的产生点和路径就会远离器件的表面，从而抑制热空穴在漏极与门极之间的氧化层附近的注入和俘获，从而避免了器件其它特性的改变。
图5示出了如图3所示LDMOS器件200的掺杂浓度与深度关系图。点破折线51代表体区105的掺杂浓度(水平方向)与深度(垂直方向)的关系；点破折线52代表漂移区103的掺杂浓度(水平方向)与深度(垂直方向)的关系。通过合理地选择和调整体区105和漂移区103的离子注入浓度和深度可以使得沿着体区-漂移区PN结的最高浓度梯度转移到器件表面下方。
图6A示出了传统LDMOS器件在关断状态(当门极-漏极电压Vgs＝0) 下，器件发生雪崩击穿前后的电流-电压特性曲线Ids-Vds。图6B示出了本发明提出的LDMOS器件在关断状态(当门极-漏极电压Vgs＝0)下，器件发生雪崩击穿前后的电流-电压特性曲线Ids-Vds。从图中可以看出，本发明提出的LDMOS器件在发生雪崩击穿前后的电流特性曲线保持不变，器件性能没有因为雪崩击穿而变差。
图7A-7E示出了根据本发明实施例的一种LDMOS器件工艺制造过程中的一些横截面图。
如图7A所示，器件制造工艺在一块硅片120的表面完成，其中硅片 120可以是在衬底101上生长的外延层。在一个实施例中，外延层可以用淀积的方法形成，例如化学蒸汽沉积(CVD)法、等离子体增强化学汽相沉积(PECVD)法、原子层淀积(ALD)法、液相外延浮生法以及其它合理的淀积技术。在另一个实施例中，硅片120可以直接是单晶衬底101表面的一层。
如图7B所示，通过在硅片120上进行一系列的N型离子注入形成N 型阱区103，其中一系列N型离子注入的注入浓度和深度按照如下方法进行控制：在垂直方向设置靠近硅片120上表面的区域和靠近硅片120下表面的区域的注入浓度均低于硅片120中间区域的注入浓度。
如图7C所示，在硅片120表面生长一层栅氧和多晶硅，形成器件的门极区102。
如图7D所示，在硅片120上形成一个P型体区105。在一个实施例中， P型体区105既可以由热扩散形成也可以由离子注入形成。在一个实施例中，P型体区105由一系列的P型离子注入形成，其中一系列P型离子注入的浓度和深度按照如下方法进行控制：在垂直方向设置靠近体区105底部边缘和靠近器件表面位置的区域的注入浓度低于体区105中间区域的注入浓度。
如图7E所示，在N型阱区103中形成一个N型重掺杂漏极接触区104，在体区105中形成一个N型重掺杂源区106和一个P型重掺杂体接触区 107，其中漏极接触区104位于门极区102的一侧(例如实施例中所示的位于门极区102的右侧)，体接触区107和大部分的源区106位于门极区102 的另一侧(例如实施例中所示的位于门极区102的左侧)，小部分的源区106位于门极区102的下方。
需要说明的是，为了避免冗长叙述，工艺步骤中的例如形成漏极、源极、场氧和其它一些必要的步骤都没有在此讨论。
图8示出了根据本发明实施例的LDMOS器件结构中通过最大场强发生点的一根分割线55。如图8所示，分割线55的一端连接在中体区P2的最大掺杂浓度所在深度处(约0.15um深)，另一端连接在中漂移区N2的最大掺杂浓度所在深度处(约0.55um深)。图8还示出了P型体区105 中的切割线C1和漂移区103中的切割线C2。
图9示出了根据本发明实施例的沿着从器件顶部表面起始的切割线C1 上的P型体区105的掺杂浓度与深度关系图，沿着从器件顶部表面起始的切割线C2上的漂移区103的掺杂浓度与深度关系图，以及分割线55上的最大掺杂浓度所处的深度。如图9所示，在一个实施例中，在体区深度为 0.15um左右(中体区P2)处，最大掺杂浓度高于1×1018ions/cm-3，在漂移区深度约0.55um左右(中漂移区N2)处，最大掺杂浓度介于1×1017ions/cm-3到1×1018ions/cm-3之间。
与传统的LDMOS器件相比，本发明提出的LDMOS器件不存在“walk-out”现象。与传统LDMOS器件不同，本发明提出的LDMOS器件的N型漂移区由一系列不同掺杂浓度的N型区域组成，本发明提出的 LDMOS器件的P型体区由一系列不同掺杂浓度的P型区域组成，这样使体区-漂移区PN结上的最高浓度梯度位于器件表面的下方位置，从而抑制了热空穴向漏极和门极之间的氧化层区域的注入和俘获，避免了器件在发生击穿时其它特性的改变。
需要声明的是，“轻掺杂”或者“重掺杂”不限制于预定的掺杂等级。
需要声明的是，上述发明内容及具体实施方式意在证明本发明所提供技术方案的实际应用，不应解释为对本发明保护范围的限定。本领域技术人员在本发明的精神和原理内，当可作各种修改、等同替换、或改进。本发明的保护范围以所附权利要求书为准。

Claims (12)

1.一种横向双扩散金属氧化物半导体(LDMOS)器件，包括：
形成在半导体器件顶部表面的门极区；
N型阱区，包括一个N型漂移区和一个N型重掺杂漏极接触区，其中重掺杂漏极接触区位于门极区的一侧，漂移区自其顶部到底部包括具有不同掺杂浓度的上漂移区、中漂移区和下漂移区；以及
P型体区，包括一个N型重掺杂源区和一个P型重掺杂体接触区，其中P型重掺杂体接触区和大部分的N型重掺杂源区位于门极区的另一侧。
2.如权利要求1所述的横向双扩散金属氧化物半导体(LDMOS)器件，其中中漂移区的掺杂浓度高于上漂移区和下漂移区的掺杂浓度，并且从中漂移区到上漂移区的掺杂浓度呈递减状态，从中漂移区到下漂移区的掺杂浓度也呈递减状态。
3.如权利要求1所述的横向双扩散金属氧化物半导体(LDMOS)器件，其中P型体区自其顶部到底部包括具有不同掺杂浓度的上体区、中体区和下体区。
4.如权利要求3所述的横向双扩散金属氧化物半导体(LDMOS)器件，其中中体区的掺杂浓度高于上体区和下体区的掺杂浓度，并且从中体区到上体区的掺杂浓度呈递减状态，从中体区到下体区的掺杂浓度也呈递减状态。
5.如权利要求4所述的横向双扩散金属氧化物半导体(LDMOS)器件，其中中体区的最高掺杂浓度高于1×1018ions/cm-3，中漂移区的最高掺杂浓度介于1×1017ions/cm-3到1×1018ions/cm-3之间。
6.一种半导体器件制造方法，包括：
通过一系列不同浓度的N型离子注入在半导体衬底上方的外延层中形成一个N型阱区，使得N型阱区具有变化的掺杂浓度；
在外延层顶部表面形成一个门极区；
在外延层中形成一个P型体区；以及
在N型阱区中形成一个N型重掺杂漏极接触区，在P型体区中形成一个N型重掺杂源区和一个P型重掺杂体接触区，其中N型重掺杂漏极接触区位于门极区的一侧，P型重掺杂体接触区位于门极区的另一侧。
7.如权利要求6所述的一种半导体器件制造方法，其中一系列不同浓度的N型离子注入按照如下方式进行：
自N型阱区的顶部至底部，N型阱区的中间区域的掺杂浓度最高，靠近顶部区域的掺杂浓度和靠近底部区域的掺杂浓度均低于中间区域的掺杂浓度。
8.如权利要求6所述的一种半导体器件制造方法，其中P型体区由一系列不同浓度的P型离子注入形成：自P型体区的顶部至底部，P型体区的中间区域的掺杂浓度最高，靠近顶部区域的掺杂浓度和靠近底部区域的掺杂浓度均低于中间区域的掺杂浓度。
9.如权利要求8所述的一种半导体器件制造方法，其中P型体区的中间区域的最高掺杂浓度高于1×1018ions/cm-3，N型阱区的中间区域的最高掺杂浓度介于1×1017ions/cm-3到1×1018ions/cm-3之间。
10.一种横向双扩散金属氧化物半导体(LDMOS)器件，包括：
形成在半导体器件顶部表面的门极区；
N型漏区，包括一个N型漂移区和一个N型重掺杂漏极接触区，其中N型重掺杂漏极接触区位于门极区的一侧，N型漂移区由一系列不同浓度的N型离子注入形成，自N型漂移区顶部至底部具有不同浓度的离子掺杂浓度；以及
P型体区，包括一个N型重掺杂源区和一个P型重掺杂体接触区，其中P型重掺杂体接触区和大部分的N型重掺杂源区位于门极区的另一侧，N型重掺杂源区和P型重掺杂体接触区毗邻，P型体区由一系列不同浓度的P型离子注入形成，自P型体区顶部至底部具有不同浓度的离子掺杂浓度。
11.如权利要求10所述的一种横向双扩散金属氧化物半导体(LDOMS)器件，其中N型漂移区和P型体区由如下方法形成：
自N型漂移区的顶部至底部，N型漂移区的中间区域的掺杂浓度最高，靠近顶部区域的掺杂浓度和靠近底部区域的掺杂浓度均低于中间区域的掺杂浓度；以及
自P型体区的顶部至底部，P型体区的中间区域的掺杂浓度最高，靠近顶部区域的掺杂浓度和靠近底部区域的掺杂浓度均低于中间区域的掺杂浓度。
12.如权利要求11所述的一种横向双扩散金属氧化物半导体(LDOMS)器件，其中P型体区的中间区域的最高掺杂浓度高于1×1018ions/cm-3，N型漂移区的中间区域的最高掺杂浓度介于1×1017ions/cm-3到1×1018ions/cm-3之间。
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