CN107764431B - Chip core temperature detection circuit - Google Patents
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Abstract
The invention belongs to the technical field of detection circuits, and particularly relates to a chip core temperature detection circuit. The chip core temperature detection circuit comprises a reference generation module, a multi-path selection module, a first resistor, a comparison module and a processing module; the reference generation module comprises two output ends and is used for generating a temperature representation current proportional to temperature and a reference current which does not change with temperature; the multi-path selection module is electrically connected with the reference generation module; the first resistor is electrically connected between the reference generating module and the grounding end; the first input end of the comparison module is electrically connected with the first resistor, and the second input end of the comparison module is electrically connected with the multi-path selection module; the processing module is respectively and electrically connected with the multi-path selection module and the comparison module. The chip core temperature detection circuit has small occupied area, accurate detection and lower power consumption.
Description
Technical Field
The invention belongs to the technical field of detection circuits, and particularly relates to a chip core temperature detection circuit.
Background
Currently, important chips inside many communication devices (including computers), such as processor chips, data exchange chips, etc., have a core temperature detection function, so as to avoid burning out the chips caused by too high temperature. In the product development process, the core temperature of the important chips needs to be tested, if the temperature of the chips is increased due to external factors or chip abnormality, a temperature protection value needs to be set, and when the temperature is higher than a certain point, the power supply of the chips is disconnected. The temperature tester adopted by the existing chip core temperature acquisition scheme can only test the surface temperature of the chip, cannot test the core temperature, needs to indirectly calculate the chip core temperature according to the heating power and the thermal resistance of the chip through the surface temperature, and thus causes larger deviation between the calculated core temperature and the actual temperature.
Current methods typically employ diesReferring to fig. 1, fig. 1 is a temperature detection circuit of a conventional temperature sensor. The temperature sensor comprises a reference generation circuit, a signal amplification circuit and a digital-to-analog conversion circuit, and generates a third BE junction voltage V in dependence on temperature through a third three-stage transistor BE3 The inputs to the ADC circuits are V respectively BE3 And a reference voltage V which does not vary with temperature REF Digital-to-analog conversion is carried out by a digital-to-analog conversion circuit to generate a digital signal representing the ratio of two paths of comparison signals, so that the digital reading of temperature is realized, but V BE3 The resulting temperature change with non-linearity of curvature can lead to relatively large temperature deviations.
The chip core is a core circuit of the chip, and has the advantages of fastest frequency, maximum power consumption and highest temperature, and the temperature of the chip core needs to be detected in real time so as to prevent the chip from being damaged due to exceeding the using temperature of the chip. In order to accurately detect the core temperature of the chip, the temperature detection circuit needs to be arranged near the core of the chip, but the prior art uses an ADC circuit, which has the disadvantages of complex circuit, large occupied area, larger power consumption and lower detection accuracy.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a chip core temperature detection circuit.
Specifically, one embodiment of the present invention provides a chip core temperature detection circuit, including: a reference generation module 101, a multiplexing module 102, a first resistor R1, a comparison module 103 and a processing module 104; wherein,
the reference generation module 101 comprises two outputs for generating a temperature-dependent current I PTAT And a reference current I which does not vary with temperature REF ；
The multiplexing module 102 is electrically connected with the reference generating module 101 for generating the reference current I which does not change with temperature under the control of the processing module 104 REF Conversion to different reference voltages V REF ；
The first resistor R1 is electrically connected to the reference generating module 101 and the ground GNDA room for characterizing the temperature of the current I PTAT Conversion to a temperature-characterization voltage V PTAT ；
A first input terminal of the comparison module 103 is electrically connected to the first resistor R1, and a second input terminal thereof is electrically connected to the multiplexing module 102, and is respectively configured to receive the temperature characterization voltage V PTAT And the reference voltage V REF And compares the temperature characterization voltage V PTAT With the reference voltage V REF ；
The processing module 104 is electrically connected to the multiplexing module 102 and the comparing module 103, respectively, and is configured to output a chip temperature test result according to the comparison result of the comparing module 103, and control the working state of the multiplexing module 102.
In one embodiment of the present invention, the reference generation module 101 includes a reference voltage generation module 1011 and a reference current generation module 1012, wherein,
a first output terminal of the reference voltage generating module 1011 is electrically connected to the first resistor R1 for generating a temperature characterization current I proportional to temperature PTAT The method comprises the steps of carrying out a first treatment on the surface of the A second output terminal of the reference voltage generating module 1011 is electrically connected to an input terminal of the reference current generating module 1012 for generating a reference voltage V which does not vary with temperature BG The method comprises the steps of carrying out a first treatment on the surface of the The output end of the reference current generating module 1012 is electrically connected with the multiplexing module 102 for generating a reference current I which does not change with temperature REF 。
In one embodiment of the present invention, the reference current generating module 1012 includes an operational amplifier IC, a first switching tube M1, a second switching tube M2, a third switching tube M3, and a second resistor R2; wherein,
the second resistor R2, the third switching tube M3 and the first switching tube M1 are sequentially connected in series between the ground terminal GND and the power supply terminal VCC;
the positive input end of the operational amplifier IC is electrically connected to the second output end of the reference voltage generating module 1011, the negative input end thereof is electrically connected to a node formed by the second resistor R2 and the third switching tube M3 in series, and the output end thereof is electrically connected to the control end of the third switching tube M3;
the control end of the first switching tube M1 is electrically connected to a node formed by connecting the first switching tube M1 and the third switching tube M3 in series;
the second switching tube M2 is connected in series between the power supply terminal VCC and the multiplexing module 102, and its control terminal is electrically connected to the control terminal of the first switching tube M1.
In one embodiment of the invention, the multiplexing module 102 includes resistor network arrays RL and 2 n Select 1 the multiplexer I1, wherein,
the resistive network array RL includes 2 n A plurality of series resistors, one end of the resistor network array RL is electrically connected to the output end of the reference current generating module 1012, and the other end is electrically connected to the ground GND;
said 2 n 1-select multiplexer I1 has 2 n A plurality of input terminals, 2 n -1 input terminal is electrically connected to a node formed by the series connection of two adjacent series resistors, respectively, and 1 input terminal is electrically connected to a node formed by the series connection of the output terminal of the reference current generating module 1012 and the series resistor connected thereto; said 2 n The output end of the 1-selecting multiplexer I1 is electrically connected to the comparison module 103, the control end thereof is electrically connected to the processing module 104, wherein the 2 n The resistance value of the series resistors is adjustable.
In one embodiment of the invention, the method 2 n The series resistance includes 2 proximate to the reference current generating module 1012 n-1 A third resistor R3 and 2 near the ground GND n-1 And a fourth resistor R4, wherein the resistance value of the fourth resistor R4 is twice the resistance value of the third resistor R3.
In one embodiment of the present invention, the comparing module 103 is a comparator I2, wherein a negative input terminal of the comparator I2 is electrically connected to a node formed by the reference generating module 101 and the first resistor R1 in series, and a positive input terminal thereof is electrically connected to the multiplexing module 102.
In one embodiment of the present invention, a D flip-flop I3 is disposed between the comparator I2 and the processing module 104, where a clk terminal of the D flip-flop I3 inputs a clock signal clk, a D terminal thereof is electrically connected to an output terminal of the comparator I2, and a Q terminal thereof is electrically connected to the processing module 104.
In one embodiment of the invention, the processing module 104 includes an RS latch I4, a counter I5, a decoder I6, and an and gate I7, wherein,
the S end of the RS latch I4 is electrically connected with the comparison module 103, and the R end of the RS latch I is input with a zero clearing signal RST;
the first input end of the AND gate I7 inputs a clock signal clk, and the second input end thereof is electrically connected with the RS-latch I4An end;
the input end of the counter I5 is electrically connected with the output end of the AND gate I7, the control end of the counter I is input with a zero clearing signal RST, and the output end of the counter I is electrically connected with the decoder I6;
the output end of the decoder I6 is electrically connected to the multiplexing module 102, and is configured to decode the count signal generated by the counter I5 to form a control signal and send the control signal to the multiplexing module 102, so as to control the reference voltage V output by the multiplexing module 102 REF 。
In one embodiment of the present invention, the output terminal of the counter I5 is used as the output terminal of the chip core temperature detection circuit, and when the counter I5 is locked, the output count result of the counter I5 is used as the chip temperature detection result.
Compared with the prior art, the invention has the beneficial effects that:
1. the chip core temperature detection circuit adopts 2 n The 1-selecting multiplexer is used for selecting and comparing voltages, and the circuit is simple in design, small in occupied area and low in power consumption.
2. The chip core temperature detection circuit is provided with the D trigger between the comparison module and the processing module, and the D trigger only samples the stable output of the comparator and sends the stable output to the RS trigger, so that the error triggering of the RS trigger can be prevented.
3. The counter bit number in the chip core temperature detection circuit and the output number of the resistor network array RL are programmable, and programming can be performed according to different application environments so as to meet the application requirements of different temperature detection ranges and different detection precision. Reference voltage V BG The values of (2) are also programmable, whereby the range of reference voltages can be varied to meet the application requirements of different temperature detection ranges and different detection accuracies.
4. The chip core temperature detection circuit can adjust the resistance value of the series resistor in the resistor array RL according to different applications so as to define the resolution of temperature detection in a segmented way, thereby reducing the cost and ensuring the detection accuracy.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a prior art chip core temperature detection circuit;
FIG. 2 is a logic schematic diagram of a chip core temperature detection circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a chip core temperature detection circuit according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of a reference current generating module according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a multiplexing module according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a chip core temperature detection circuit according to an embodiment of the present invention;
FIG. 7 is a diagram showing a correspondence between binary codes and decimal codes of a counter according to an embodiment of the present invention;
FIG. 8 is a schematic illustration of an embodiment of the present inventionSeed 2 6 A working schematic diagram of the 1-selecting multiplexer;
fig. 9 is a schematic diagram of a comparison process of a comparator according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved more apparent, the following detailed description will be given with reference to the accompanying drawings and specific embodiments.
Embodiment one:
referring to fig. 2, fig. 2 is a logic schematic diagram of a chip core temperature detection circuit according to an embodiment of the invention. The chip core temperature detection circuit comprises a reference generation module 101, a multi-path selection module 102, a first resistor R1, a comparison module 103 and a processing module 104; wherein,
the reference generation module 101 comprises two outputs for generating a temperature-dependent current I PTAT And a reference current I which does not vary with temperature REF ；
The multiplexing module 102 is electrically connected with the reference generation module 101 for generating a reference current I which will not vary with temperature under the control of the processing module 104 REF Conversion to different reference voltages V REF ；
A first resistor R1 electrically connected between the reference generating module 101 and the ground GND for providing a temperature-indicative current I PTAT Conversion to a temperature-characterization voltage V PTAT ；
The first input end of the comparison module 103 is electrically connected to the first resistor R1, and the second input end thereof is electrically connected to the multiplexing module 102, for respectively receiving the temperature characterization voltage V PTAT And reference voltage V REF And comparing the temperature characterization voltage V PTAT With reference voltage V REF ；
The processing module 104 is electrically connected to the multiplexing module 102 and the comparing module 103, and is configured to output a chip temperature test result according to the comparison result of the comparing module 103, and control the working state of the multiplexing module 102.
Specifically, referring to fig. 3, the reference generation module 101 includes a reference voltage generation module 1011 and a reference current generation module 1012, wherein,
a first output terminal of the reference voltage generating module 1011 is electrically connected to a first resistor R1 for generating a temperature characterization current I proportional to temperature PTAT The method comprises the steps of carrying out a first treatment on the surface of the A second output terminal of the reference voltage generating module 1011 is electrically connected to an input terminal of the reference current generating module 1012 for generating a reference voltage V which does not vary with temperature BG The method comprises the steps of carrying out a first treatment on the surface of the The output end of the reference current generating module 1012 is electrically connected with the multiplexing module 102 for generating a reference current I which does not change with temperature REF 。
Further, the temperature is proportional to the temperature, which characterizes the current I PTAT A temperature characterization voltage V which is proportional to the temperature is output through a first resistor R1 PTAT Temperature characterization voltage V PTAT For characterizing the chip core temperature.
Compared with the existing temperature detection circuit, the temperature detection circuit for the chip core of the embodiment omits an ADC digital-to-analog conversion circuit, is simple in design and small in occupied area, and therefore the temperature detection circuit can be closer to the chip core and is higher in detection accuracy.
Embodiment two:
in order to facilitate understanding of the operation principle of the present invention, the present embodiment describes in detail the circuit structures of the reference current generating module 1012 and the multiplexing module 102 based on the above embodiments.
Specifically, referring to fig. 4, fig. 4 is a schematic circuit diagram of a reference current generating module according to an embodiment of the invention. The reference current generating module 1012 includes an operational amplifier IC, a first switching tube M1, a second switching tube M2, a third switching tube M3 and a second resistor R2,
the second resistor R2, the third switching tube M3 and the first switching tube M1 are sequentially connected in series between the ground end GND and the power end VCC;
the positive input end of the operational amplifier IC is electrically connected with the second output end of the reference voltage generating module 1011, the negative input end of the operational amplifier IC is electrically connected to a node formed by connecting the second resistor R2 and the third switching tube M3 in series, and the output end of the operational amplifier IC is electrically connected with the control end of the third switching tube M3;
the control end of the first switching tube M1 is electrically connected to a node formed by connecting the first switching tube M1 and the third switching tube M3 in series;
the second switching tube M2 is connected in series between the power supply terminal VCC and the multiplexing module 102, and its control terminal is electrically connected to the control terminal of the first switching tube M1.
Reference voltage V BG Generating a reference current I which does not vary with temperature through a reference current generating module 1012 REF 。
Further, referring to fig. 5, fig. 5 is a schematic structural diagram of a multiplexing module according to an embodiment of the invention. The multiplexing module 102 includes resistor network arrays RL and 2 n Select 1 the multiplexer I1, wherein,
the resistive network array RL includes 2 n One end of the resistor network array RL is electrically connected with the output end of the reference current generating module 1012, and the other end is connected with the grounding end GND;
2 n 1-select multiplexer I1 has 2 n A plurality of input terminals, 2 n -1 input terminals are respectively electrically connected to nodes formed by the series connection of two adjacent series resistors, 1 input terminal is electrically connected to nodes formed by the series connection of the output terminal of the reference current generating module 1012 and the series resistor connected thereto, 2 n The output end of the 1-selecting multiplexer I1 is electrically connected to the comparing module 103, and the control end thereof is electrically connected to the processing module 104, wherein the resistance value of each of the series resistors is adjustable.
In this embodiment, the chip core temperature detection circuit of the present invention employs 2 n The voltage selection is carried out by the 1-choice multiplexer, the circuit design is simple, the power consumption is small, and in addition, the resistance value of the resistor array RL can be adjusted according to different applications, so that the resolution of temperature detection is defined in a segmented mode.
Embodiment III:
referring to fig. 6, fig. 6 is a schematic structural diagram of a chip core temperature detection circuit according to an embodiment of the present invention. In this embodiment, the comparing module 103 is a comparator I2, the negative input terminal of the comparator I2 is electrically connected to the node formed by the reference generating module 101 and the first resistor R1 connected in series, and the positive input terminal of the comparator I2 is electrically connected to the multiple selecting module 102.
Further, a D flip-flop I3 is provided between the comparator I2 and the processing module 104. The clk terminal of the D flip-flop I3 inputs the clock signal clk, the D terminal thereof is electrically connected to the output terminal of the comparator I2, and the Q terminal thereof is electrically connected to the processing module 104.
Since the comparator I2 is comparing in real time, the output will change once the input changes. At 2 n When the selector 1 multiplexer I1 is switched, the reference voltage V is output to the positive input end of the comparator I2 REF A glitch may occur and the comparator I2 may generate an erroneous output, for which purpose a D flip-flop is added and its clock signal is at a different clock edge than the switching signal. In this embodiment, the switch is switched by a rising clock edge, the D flip-flop I3 is switched by a falling clock edge, and the comparator I2 has a half clock settling time before being sampled, so that the D flip-flop I3 can be input to the processing module 104 after sampling the settling output of the comparator I2, that is, the D flip-flop I3 only samples the settling output of the comparator, so that the addition of the D flip-flop can avoid sampling during the switch, thereby preventing erroneous comparison results from being output.
Further, the processing module 104 includes an RS latch I4, a counter I5, a decoder I6, and an and gate I7. The S terminal of the RS latch I4 is electrically connected to the comparison module 103, and the R terminal thereof receives the zero clearing signal RST. RS latch I4The end outputs a DONE signal marking whether the temperature detection is completed, the DONE signal is 0 when the temperature detection process is completed, and the DONE signal is 1 when the temperature detection process is not completed.
The first input end of the AND gate I7 inputs the clock signal clk, and the second input end thereof is electrically connected with the RS-latch I4And (3) an end.
The input end of the counter I5 is electrically connected with the output end of the AND gate I7, the control end of the counter I is input with a zero clearing signal RST, and the output end of the counter I is electrically connected with the decoder I6 for generating n-bit binary digital codes.The counter I5 is used for implementing a counting function, and starts counting when the clock signal clk is valid, and the code value of the counter is increased by 1 every time one clock is used. The output end of the decoder I6 is electrically connected with 2 n A 1-selecting multiplexer I1 for decoding the n-bit binary digital code value of the counter I5 and generating 2 n A control signal.
In this embodiment, the chip core temperature detection circuit of the present invention is provided with the D flip-flop between the comparator and the processing module, and the D flip-flop only samples the stable output of the comparator and transmits the stable output to the RS flip-flop, so as to avoid sampling the erroneous output of the comparator and prevent the erroneous triggering of the RS flip-flop, thereby ensuring the detection accuracy of the chip core temperature detection circuit.
Embodiment four:
in this embodiment, the multiplexing module 102 includes resistor network arrays RL and 2 6 The 1-choice multiplexer I1, wherein the resistor network array RL comprises 64 resistors in series.
In this embodiment, will be at 2 6 The selection 1 multiplexer is taken as an example to explain the working principle of the invention in detail.
Referring to fig. 7, fig. 7 is a diagram showing a correspondence between binary codes and decimal codes of a counter I5 according to an embodiment of the present invention. When the DONE signal is 1, the clock of the counter I5 is valid, and the code value of the counter is increased by 1; when the DONE signal is 0, the clock of the counter I5 is disabled, the counter is locked, and the temperature detection is completed.
Referring to fig. 8, fig. 8 is a diagram of a method 2 according to an embodiment of the invention 6 Schematic of the operation of the select 1 multiplexer I1. When temperature detection starts, the counter I5 starts counting from 0, outputs a first digital code, and sends the first digital code to the decoder I6 for decoding 6 1-selecting multiplexer I1,2 6 The 1-selecting multiplexer I1 selects and outputs a lowest voltage 1 as a reference voltage V REF To the positive input of the comparator I2, and the temperature characterization voltage V PTAT A comparison is made. If voltage 1 is lower than temperature characterization voltage V PTAT The output of comparator I2 is 0. The output of the RS trigger I4 is 1, the clock of the counter I5 is valid, and the counterThe code value is added with 1 to generate a second digital code, and then 2 6 Select 1 multiplexer output voltage 2 as reference voltage V REF And in a comparator I2 with a temperature characterization voltage V PTAT A comparison is made. If the output result of the comparator I2 is 0, the counter I5 is continuously increased by 1, and the process is repeated.
Referring to fig. 9, fig. 9 is a view of a V according to an embodiment of the present invention PTAT And V is equal to REF Is a schematic diagram of the comparison process. As can be seen from fig. 9, as the digital code value of the counter increases, V REF Rising in steps, when the digital code value of the counter reaches a certain value, the corresponding voltage N is higher than V PTAT The output of the comparator I2 is 1, at this time, the state of the RS latch I4 is turned over, the DONE signal is changed from 1 to 0, after the DONE signal and the clock signal clk are subjected to logical AND operation, the output is 0, at this time, the clock of the counter I5 is stopped, the counter I5 is locked, and the temperature detection is completed. At this time, the output end of the counter I5 is used as the output end of the chip core temperature detection circuit, and when the counter I5 is locked, the output end of the counter I5 outputs a counter code value, and the current counter code value is the digital code of the temperature at that time. The counter I5 may input a clear signal RST, and upon receiving the clear signal RST, clear the RS flip-flop and the counter to start the next detection.
In addition, referring to fig. 5, in the present embodiment, the number 2 6 The series resistors include 32 third resistors R3 near the reference current generating module 1012 and 32 fourth resistors R4 near the ground GND, wherein the resistance of the fourth resistors R4 is twice the resistance of the third resistors R3. The output of the counter I5 outputs a total of 64 code values, corresponding to a temperature range of-56 ℃ to 145 ℃, which covers the operating range of the FPGA chip. The design accuracy of the chip core temperature detection circuit can be divided into 2 sections through the change of the front section and the rear section of the series resistance value in the resistance network array RL, for example, the temperature is lower than 80 ℃ and is the safe temperature of the chip, and the resolution is designed to be 4 ℃; at above 80 ℃, the resolution is designed to be 2 ℃ in order to prevent damage from excessive chip temperature.
In this embodiment, the resolution of temperature detection can be defined in sections by adjusting the resistance value of each series resistor in the resistor array RL, so that the cost is reduced and the accuracy of detection is ensured.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (7)
1. A chip core temperature detection circuit, comprising: the device comprises a reference generation module (101), a multiplexing module (102), a first resistor (R1), a comparison module (103) and a processing module (104); wherein,
the reference generation module (101) comprises two outputs for generating a temperature-dependent current (I PTAT ) And a reference current (I) which does not vary with temperature REF )；
The multiplexing module (102) is electrically connected with the reference generation module (101) and is used for controlling the reference current (I) which does not change with the temperature under the control of the processing module (104) REF ) To a different reference voltage (V REF )；
The first resistor (R1) is electrically connected between the reference generating module (101) and the Ground (GND) for supplying the temperature-dependent current (I PTAT ) Is converted into a temperature representation voltage (V PTAT )；
The first input end of the comparison module (103) is electrically connected with the first resistor (R1), and the second input end thereof is electrically connected with the multiplexing module (102) and is respectively used for receiving the temperature representation voltage (V PTAT ) And the reference voltage (V REF ) And comparing the temperature-characterization voltage (V PTAT ) With the reference voltage (V REF )；
The processing module (104) is respectively and electrically connected with the multi-path selection module (102) and the comparison module (103) and is used for outputting a chip temperature test result according to the comparison result of the comparison module (103) and controlling the working state of the multi-path selection module (102);
the reference generation module (101) includes a reference voltage generation module (1011) and a reference current generation module (1012), wherein,
the first output end of the reference voltage generating module (1011) is electrically connected with the first resistor (R1) for generating a temperature characterization current (I PTAT ) The method comprises the steps of carrying out a first treatment on the surface of the The second output end of the reference voltage generating module (1011) is electrically connected with the input end of the reference current generating module (1012) for generating a reference voltage (V) which does not change with temperature BG ) The method comprises the steps of carrying out a first treatment on the surface of the The output end of the reference current generating module (1012) is electrically connected with the multiplexing module (102) for generating a reference current (I) which does not change with temperature REF )；
The multiplexing module (102) comprises an array of resistor networks (RL) and 2 n A 1-selecting multiplexer (I1), wherein,
the resistive network array (RL) comprises 2 n -a series resistor, one end of the resistor network array (RL) being electrically connected to the output of the reference current generating module (1012), the other end being electrically connected to a Ground (GND);
said 2 n 1-choice multiplexer (I1) has 2 n A plurality of input terminals, 2 n -1 input terminals are respectively electrically connected to nodes formed by the series connection of two adjacent series resistors, 1 input terminal is electrically connected to a node formed by the series connection of the output terminal of the reference current generating module (1012) and the series resistor connected with the output terminal; said 2 n The output end of the 1-selecting multiplexer (I1) is electrically connected to the comparison module (103), and the control end thereof is electrically connected to the processing module (2) n The resistance value of the series resistors is adjustable.
2. The chip core temperature detection circuit according to claim 1, wherein the reference current generation module (1012) includes an operational amplifier (IC), a first switching tube (M1), a second switching tube (M2), a third switching tube (M3), and a second resistor (R2); wherein,
the second resistor (R2), the third switching tube (M3) and the first switching tube (M1) are sequentially connected in series between a grounding end (GND) and a power supply end (VCC);
the positive input end of the operational amplifier (IC) is electrically connected with the second output end of the reference voltage generating module (1011), the negative input end of the operational amplifier (IC) is electrically connected to a node formed by the second resistor (R2) and the third switching tube (M3) in series, and the output end of the operational amplifier (IC) is electrically connected with the control end of the third switching tube (M3);
the control end of the first switching tube (M1) is electrically connected to a node formed by connecting the first switching tube (M1) and the third switching tube (M3) in series;
the second switching tube (M2) is connected in series between a power supply end (VCC) and the multiplexing module (102), and a control end of the second switching tube is electrically connected with a control end of the first switching tube (M1).
3. The chip core temperature detection circuit according to claim 2, wherein said 2 n The series resistance comprises 2 adjacent to the reference current generating module (1012) n-1 A third resistor (R3) and 2 near the Ground (GND) n-1 And a fourth resistor (R4), wherein the resistance of the fourth resistor (R4) is twice the resistance of the third resistor (R3).
4. The chip core temperature detection circuit according to claim 1, wherein the comparison module (103) is a comparator (I2), a negative input terminal of the comparator (I2) is electrically connected to a node formed by the reference generation module (101) and the first resistor (R1) in series, and a positive input terminal thereof is electrically connected to the multiplexing module (102).
5. The chip core temperature detection circuit according to claim 4, wherein a D flip-flop (I3) is disposed between the comparator (I2) and the processing module (104), wherein a clk terminal of the D flip-flop (I3) is input with a clock signal (clk), a D terminal thereof is electrically connected to an output terminal of the comparator (I2), and a Q terminal thereof is electrically connected to the processing module (104).
6. The chip core temperature detection circuit according to claim 1, wherein the processing module (104) comprises an RS latch (I4), a counter (I5), a decoder (I6), and an and gate (I7), wherein,
the S end of the RS latch (I4) is electrically connected with the comparison module (103), and the R end of the RS latch inputs a zero clearing signal (RST);
the first input end of the AND gate (I7) inputs a clock signal (clk), and the second input end of the AND gate is electrically connected with the Q end of the RS latch (I4);
the input end of the counter (I5) is electrically connected with the output end of the AND gate (I7), the control end of the counter is input with a zero clearing signal (RST), and the output end of the counter is electrically connected with the decoder (I6);
the output end of the decoder (I6) is electrically connected with the multiplexing module (102) and is used for decoding the counting signal generated by the counter (I5) to form a control signal and sending the control signal to the multiplexing module (102) so as to control the reference voltage (V) output by the multiplexing module (102) REF )。
7. The chip core temperature detection circuit according to claim 6, wherein an output terminal of the counter (I5) is used as an output terminal of the chip core temperature detection circuit, and when the counter (I5) is locked, an output count result of the counter (I5) is used as the chip temperature detection result.
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| CN113031672A (en) * | 2019-12-25 | 2021-06-25 | 中兴通讯股份有限公司 | Temperature control method, system and storage medium |
| CN111609943B (en) * | 2020-05-11 | 2022-04-12 | Oppo广东移动通信有限公司 | Temperature detection circuit |
| CN113945293B (en) * | 2020-06-30 | 2023-04-18 | 长鑫存储技术有限公司 | Semiconductor device with a plurality of semiconductor chips |
| CN112485645A (en) * | 2020-11-30 | 2021-03-12 | 海光信息技术股份有限公司 | Chip test temperature control method, control system, temperature control board card and test system |
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