CN212061135U - Device for improving randomness of output sequence - Google Patents

Abstract

The utility model provides a device for improving the randomness of an output sequence, which relates to the field of network information security and comprises a random number generator, wherein the random number generator comprises a charging tube and also comprises a delay unit and a finite state machine; the delay unit is connected with a G stage of a configuration tube, the finite state machine is respectively in communication connection with the delay unit and a charging tube, the charging tube is a configurable charging tube, and the delay unit is a configurable clock delay unit; the configurable charging pipe comprises a main charging pipe and n configuration pipes, and the main charging pipe is connected with the configuration pipes in parallel; the configurable clock delay unit comprises n configuration pipes which are connected in parallel, wherein n is greater than or equal to 1, the influence of various non-ideal factors on the randomness of an output sequence is eliminated through two-stage correction by using a configurable charging pipe, and the probability of continuous 0 or 1 situations is reduced by turning on or off one corresponding configuration pipe at a time through correction, so that the system is in a balanced state.

Description

Device for improving randomness of output sequence

Technical Field

The utility model relates to a network information security field especially relates to a device of improvement output sequence randomness.

Background

Currently, a single-core bayonet connector used in the industry generally adopts a split shell structure, as shown in fig. 1. The split type casing is with two casings of threaded connection, seals with O type sealing washer in the middle of two casing junctions, and the connector of this structure is sealed tight after the product assembly easily appears in the production assembly, and waterproof grade is unqualified and takes place the ageing scheduling problem that leads to leaking of sealing washer in the use.

With the explosion development of the internet and the generation of concepts such as cloud computing and cloud storage, network information security is more and more important.

The generation of the true random number is based on natural physical phenomena, and according to different implementation methods, a true random number generator can be divided into three types, namely a discrete chaotic TRNG, an oscillator sampling TRNG and a thermal noise TRNG, wherein the discrete chaotic TRNG is based on a chaos theory of a nonlinear system, a complex switch network circuit is used in design, and high speed and low power consumption cannot be taken into consideration. Oscillator sampling TRNG converts the noise source into phase jitter of a high frequency ring oscillator and uses a low frequency clock for sampling, which has the disadvantage of insufficient randomness, requiring the introduction of additional noise and disturbances to increase the randomness of the output sequence. The thermal noise TRNG directly amplifies resistance thermal noise or MOS transistor channel thermal noise as a random source, and is most widely applied. A typical approach is to amplify the thermal noise of a pair of large resistors using a high-gain high-bandwidth differential amplifier and quantize the resulting samples with an analog-to-digital converter. As the process size decreases, the design of high gain high bandwidth amplifiers becomes more difficult, and non-ideal factors such as amplifier offset, substrate coupled noise, etc. will affect the randomness of the system output.

The utility model mainly relates to a RNG-1's digital physics noise source circuit, RNG-1 is a style of digital physics noise source circuit for produce true random number sequence, be the essential basic component in information security and the password product, if: the generation of session keys, device keys, and the setting of random numbers and various initial vectors in security protocols, all require the use of true random sequences, which are also widely used in other fields such as communications, measurements, acoustics, and the like.

The RNG-1 physical noise source can form an application system together with a CPU and an E2 PROM. It is widely used for key management in information security, i.e., generating keys, storing keys, and updating keys. The sequence of the physical noise source output in the system has good randomness. The CPU in the system is used for generating control signals of a physical noise source and an E2PROM chip, and the E2PROM is used for storing a random sequence output by the physical noise source chip under the control of the CPU. The E2PROM has the performance of repeated erasing and writing, so that the system can conveniently perform repeated key generation and storage operations, thereby realizing the key updating function. The system can realize the key management of the one-time pad. The method can be used for key management of military information transmission and network information transmission, and can also be used for manufacturing coded locks and the like.

The product index and the electrical characteristic parameters are as follows: working voltage: 3.3V (+ -10%), 5V, 3.3V. Sampling frequency: less than or equal to 20 MHz. Output rate: less than or equal to 20 Mbps. Dynamic characteristics: CLK-DATA propagation delay: less than or equal to 15 ns; DATA output transition time: less than or equal to 15 ns; output allowed time: less than or equal to 10 ns; output prohibition time: less than or equal to 10 ns. Power consumption: the working current is less than or equal to 20 mA; the sleep current is less than or equal to 300 muA. Temperature range: working temperature range: -40 ℃ to 85 ℃; storage temperature range: -55 ℃ to 125 ℃. The chip pin distribution diagram is shown in fig. 1, and the pin description of each pin is shown in the following table:

TABLE 1 Pin description

Typical applications include, as shown in fig. 2, a series resistor connected to the positive power supply VDD terminal of the chip to protect the circuit during testing and application, and a bypass capacitor of about 0.1uf is proposed to decouple the power supply.

The core circuit of the true random number generator is a typical structure of a true random number generator based on thermal noise, as shown in fig. 3. The device mainly comprises a thermal noise source, an amplifier and a comparator. Due to the existence of non-ideal factors such as input offset, limited bandwidth, substrate coupling, power supply voltage disturbance and temperature variation of the amplifier, a feedback loop and a post-processing module are required to be added in an actual circuit to increase the randomness of an output sequence. Since the thermal noise has a small amplitude, a high-gain amplifier needs to be designed, which undoubtedly increases the difficulty of designing the circuit and occupies most of the power consumption of the system. To obtain a larger gain, a positive feedback structure may be used in addition to the high gain amplifier.

The working process is shown in FIG. 4, M1-M4 form positive feedback; m5 and M6 tubes are charging tubes; m7 and M8 tubes are reset tubes. Fig. 5 is a timing diagram of the Reset signal Reset and the clock signal CLK. The specific working process of the circuit is as follows: when the rising edge of the Reset signal Reset arrives, the Reset transistors M7 and M8 are turned on, and the output nodes c and d are Reset to the ground GND. At the same time, CLK is low, and the charging tubes M5, M6 are conductive. Since the switch transistor M9 is a PMOS transistor, it can conduct high level, so that the potentials of the nodes a and b are equal. When the Reset falling edge and the CLK rising edge come, M5-M8 are turned off. When the falling edge of CLK comes again, M5 and M6 are turned on simultaneously, and ID1 and ID2 charge node capacitors Ca and Cb, respectively. Due to channel thermal noise of M5 and M6 tubes, charging currents ID1 and ID2 are not strictly equal. This will cause one of the M3, M4 tubes to turn on first reaching the threshold voltage | vth.p |. Under the positive feedback effect of M1-M4 tubes, the voltage difference between the c node and the d node is increased rapidly and reaches a stable state. When CLK finally returns to high level, the voltages of the nodes c and d are output by the buffer unit to obtain a random sequence.

It should be noted that the above is performed under ideal conditions without occurrence of transistor mismatch, power supply voltage disturbance, and the like. Under non-ideal conditions, for example, the width-to-length ratios of the M5 and M6 tubes are not completely equal due to process limitations, there is an inherent error in the charging currents ID1 and ID2 of the M5 and M6 tubes. This error causes the output to be biased towards some fixed result. If the equivalent thermal noise current of the transistor is less dominant than the error caused by mismatch, the randomness of the output sequence will be greatly reduced. When the circuits on the left side and the right side are completely matched, the disturbance of the power supply voltage VDD exists in the form of common mode noise, the charging currents ID1 and ID2 are increased or decreased by the same value, no influence is caused on the output result, and the output is only influenced by differential mode noise. However, when the circuits on the two sides are not completely symmetrical, the power supply voltage disturbance is converted into differential mode noise through circuit conduction, and the randomness of an output sequence is influenced. This condition can be addressed by reducing the mismatch of the transistors in the left and right side circuits. Other factors that may introduce error are temperature variations and device aging. To take maximum advantage of the randomness of the thermal noise source, static and dynamic errors in the structure need to be eliminated. This requires the introduction of a corresponding adjustment mechanism such that the amplitude of the equivalent noise is much larger than the sum of the errors introduced by the various non-ideal factors.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a: aiming at the problems in the prior art, the influence of various non-ideal factors on the randomness of an output sequence is eliminated by adopting two-stage correction.

The utility model adopts the technical scheme as follows:

an apparatus for improving randomness of an output sequence comprises a random number generator, wherein the random number generator comprises a charging tube, a delay unit and a finite-state machine; the delay unit is connected with a G stage of a configuration tube, the finite state machine is respectively in communication connection with the delay unit and a charging tube, the charging tube is a configurable charging tube, and the delay unit is a configurable clock delay unit;

the configurable charging pipe comprises a main charging pipe and n configuration pipes, and the main charging pipe is connected with the configuration pipes in parallel;

the configurable clock delay unit comprises n configuration pipes which are connected in parallel,

and n is greater than or equal to 1.

Further, n is 4.

Furthermore, the configuration pipes of the configurable charging pipe and the configurable clock delay unit are configuration pipes with different weights.

Furthermore, the configuration tubes of the configurable charging tube are all connected in series with one MOS tube, and the G pole of each MOS tube is respectively connected with a corresponding control signal conf [ n ]; and the G poles of the main charging tube and the G poles of the configuration tube are both connected with a clock signal.

Furthermore, the configurable clock delay unit further comprises 5 MOS transistors PQ1, PQ2, PQ3, PQ4 and PQ5, wherein the PQ1 and the PQ3 are connected in series, the D poles of the PQs are connected with the G poles of PQ5, PQ2 and PQ4, and the S poles of the PQs 2 and the S poles of PQ4 are respectively connected with the S poles; the PQ5 is connected in parallel with the configuration tube of the configurable clock delay unit, the D pole of the PQ5 is connected with the D pole of the PQ2, and the S pole of the PQ5 is connected with the D pole of the PQ 4; the configuration pipes of the configurable clock delay units are respectively connected with control signals CLK [ n ].

Furthermore, the configurable clock delay unit and the configurable charging tube are both two, and the finite state machine is respectively connected with the configurable clock delay unit and the configurable charging tube in a communication mode.

Since the technical scheme is adopted, the beneficial effects of the utility model are that: the configurable charging tube is used for eliminating the influence of various non-ideal factors on the randomness of an output sequence through secondary correction, and a corresponding configuration tube is switched on or switched off through correction each time so as to reduce the probability of continuous 0 or 1 situations and enable the system to be in a balanced state; in addition, the correction strategy may also prevent overcorrection of the initial mismatch condition.

Drawings

FIG. 1 is a schematic diagram of the distribution of chip pins;

FIG. 2 is a schematic diagram of an application circuit of a random number generator;

FIG. 3 is a block diagram of a true random number generator based on thermal noise;

FIG. 4 is a circuit diagram of a prior art true random number generator;

FIG. 5 is a timing diagram of clock and reset signals;

FIG. 6 is a block diagram of the true random number generator of the present application;

FIG. 7 is a schematic diagram of a coarse-grained adjustment configurable structure according to the present application;

FIG. 8 is a graph of the coarse grain calibration randomness test of the present application;

FIG. 9 is a schematic diagram of a configurable clock delay unit of the present application;

fig. 10 is a flowchart of background correction.

Detailed Description

The present invention will be described in detail with reference to the accompanying drawings.

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

According to the analysis in the prior art, the randomness of the output sequence can be reduced by factors such as process, power supply voltage disturbance and the like. The circuit adopts two-stage correction to eliminate the influence of various non-ideal factors on the randomness of an output sequence, the overall structure is shown in figure 6, the circuit comprises a random number generator, the random number generator comprises a charging tube, a delay unit and a finite state machine, the delay unit is connected with a G stage of a configuration tube, the finite state machine is respectively in communication connection with the delay unit and the charging tube, the charging tube is a configurable charging tube, the delay unit is a configurable clock delay unit, and the working flow is as follows:

step 1: performing coarse grain correction on the random source by adopting a configurable charging tube;

step 2: fine-grained correction is carried out on the random source by adopting a configurable clock delay unit;

and step 3: generating an output sequence, detecting the output sequence by using a finite state machine to judge whether a system is in a balanced state or not in order to ensure that the correction mode provided by the circuit has self-adaptability;

and 4, step 4: if the system is in a balanced state, the configuration signal is kept unchanged, otherwise, the steps 1-3 are repeated, and corresponding coarse adjustment or fine adjustment is carried out on the random source according to the output sequence.

Coarse grain correction is performed by using a configurable charging tube, and due to mismatch between M5 and M6, the charging tubes M5 and M6 in FIG. 4 are replaced by the configurable structure shown in FIG. 7. The system is composed of a main charging tube and four configuration tubes with different weights in parallel connection, wherein the configuration tubes of the configurable charging tubes are all connected with an MOS tube in series, and G poles of the MOS tubes are respectively connected with corresponding control signals conf [ n ]; and the G poles of the main charging tube and the G poles of the configuration tube are both connected with a clock signal. The 4bit control signals conf _ M5[3:0] and conf _ M6[3:0] respectively control the on and off of the configuration tubes connected with M5 and M6 in parallel, so that the magnitude of the charging current on two sides is adjusted. If ID1 > ID2, without considering channel thermal noise, ID2 can be achieved by turning off several configuration tubes in parallel with M5 tubes or turning on several configuration tubes in parallel with M6 tubes. With the structure shown in fig. 7, the correctable mismatch range is up to ± 16%, and the correction step size is 1%. Mismatch range is 0% -5%, step length is 0.1%. Fig. 8 shows the results of the randomness test of the output sequence after coarse grain correction (measured in fig. 8 using only the frequency detection of NIST). The 6P value peaks in fig. 8 verify that the coarse grain correction has a correction step size of about 1%. However, it was readily found that there were regions between the peaks that failed the NIST test (P-value < 1%). To pass the NIST test over the entire mismatch range, a fine-grained second-order correction needs to be introduced. The residual error after coarse grain correction is corrected by adding a configurable clock delay unit to the structure of fig. 4.

The adaptivity of the true random number generator is implemented by a finite state machine guarantee. As shown in FIG. 6, the 4-bit shift register is used herein to detect the continuous 4-bit output and determine whether the output sequence is biased to 0 or 1. If the number of 0 s in the continuous 4-bit output is more than 2, the output is considered to be inclined to 0, and a 2-bit flag signal flag is set to 10; if the number of 0 is less than 2, the output is considered to be 1, and flag is set to 01; if the number of 0 is just equal to 2, the system is considered to be in a balanced state, and flag is set to 00. When the system is in an unbalanced state, adjusting one of the 4 configuration signals conf _ M5[3:0], conf _ M6[3:0], CLK0[3:0] and CLK1[3:0] every four clock cycles brings the system to a balanced state; when the system is in a balanced state, the configuration signal remains unchanged. It is noted that this way of correction does not lead to the situation where consecutive multi-bit 0 s or multi-bit 1 s are not available, but only slightly reduces the probability of this occurring.

The state transition diagram of a finite state machine is shown in fig. 10. Coarse grain correction is first performed when the chip is powered on. Depending on the detected output, one of the coarse-grain correction control signals conf _ M5[3:0] and conf _ M6[3:0] is subjected to a corresponding plus 1 or minus 1 operation every four clock cycles until a 10-01 or 01-10 inversion of the flag signal flag occurs. For example, at power-up, due to device mismatch, the outputs are all 0, and the flag signal flag is 10. Calibration is first performed by turning on the configuration tube of M5 until conf _ M5 is 0000. If flag is still equal to 10 at this time, the finite state machine performs correction by turning off the configuration pipe of M6 until the flag signal flips. The correction strategy may prevent overcorrection of the initial mismatch condition. To this end, the finite state machine enters a second stage of correction, fine grain correction. The clock delay unit comprises a first clock delay unit and a second clock delay unit, wherein the first clock delay unit and the second clock delay unit respectively comprise 4 configuration pipes with different weights, the configuration pipes are connected in parallel, as shown in fig. 9, the configurable clock delay unit further comprises 5 MOS pipes PQ1, PQ2, PQ3, PQ4 and PQ5, the PQ1 and the PQ3 are connected in series, the D poles of the PQ pipes are connected with the G poles of PQ5, PQ2 and PQ4, and the S poles of the PQ pipes are respectively connected with the S poles of PQ2 and the S poles of PQ 4; the PQ5 is connected in parallel with the configuration tube of the configurable clock delay unit, the D pole of the PQ5 is connected with the D pole of the PQ2, and the S pole of the PQ5 is connected with the D pole of the PQ 4; the configuration pipes of the configurable clock delay units are respectively connected with control signals CLK [ n ]. The random source is always biased in the high entropy region by constant adjustment of the configuration signals CLK0[3:0] and CLK1[3:0] of the first and second clock delay cells, respectively, to obtain high randomness of thermal noise. When the output sequence is inclined to 0, increasing the conduction of the first clock unit and the corresponding configuration tube or reducing the conduction of the second clock unit and the corresponding configuration tube; when the output sequence is inclined to 1, the conduction of the first clock unit and the corresponding configuration tube is reduced or the conduction of the second clock unit and the corresponding configuration tube is increased. Similarly, if the output sequence is biased to 0, the correction can be performed by turning on the configuration pipe in the left clock delay unit, and if CLK0 reaches the maximum value (1111), the control signal CLK1 is decremented by 1. Similarly, the output sequence tends to be 1, which can be eliminated by adding 1 to CLK1 or subtracting 1 from CLK 0.

Further, assume that there is only a mismatch between M5 and M6. Mismatches between M1 and M2, M3 and M4 also reduce the randomness of the output. Their mismatch causes the c, d nodes to produce a fixed difference when reset, thereby affecting the output result. The influence of M1 and M2 on randomness is smaller than the mismatch of M3-M5. The matching errors of M1-M4 can be normalized to the matching errors of M5 and M6, namely, the mismatch of M1-M4 is equivalent to the mismatch of M5 and M6 under the same output condition, so that other correction modes are not needed.

And (3) simulating the whole true random number generator system consisting of the analog circuit part and the digital correction algorithm by adopting a Cadence spectrum-verilog hybrid simulator, wherein the working frequency of the system is 125 MHz. The simulation process adopts a 0.18 mu m CMOS process, and the working voltage is 1.8V. Artificially introducing 2% mismatch for the M1, M3, and M5 tubes, the initial output of the system is a sequence of all 1's. After the correction of the dynamic correction algorithm, the system enters a high-entropy area to obtain a required random number sequence. The NIST test results for the output sequences obtained with the M1, M3, and M5 tubes all introducing a mismatch error of 2% are given in table 2. The device of the utility model passes through all the test functions.

TABLE 2 NIST test results

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims (6)

1. An apparatus for improving randomness of an output sequence, comprising a random number generator, said random number generator comprising a charge tube, wherein: the random number generator further comprises a delay unit and a finite state machine; the delay unit is connected with a G stage of a configuration tube, the finite state machine is respectively in communication connection with the delay unit and a charging tube, the charging tube is a configurable charging tube, and the delay unit is a configurable clock delay unit;

the configurable charging pipe comprises a main charging pipe and n configuration pipes, and the main charging pipe is connected with the configuration pipes in parallel;

the configurable clock delay unit comprises n configuration pipes which are connected in parallel,

and n is greater than or equal to 1.

2. The apparatus for improving randomness of an output sequence according to claim 1, wherein: and n is 4.

3. The apparatus for improving randomness of an output sequence according to claim 1, wherein: the configurable charging tube and the configurable tube of the configurable clock delay unit are all configured tubes with different weights.

4. The apparatus for improving randomness of an output sequence according to claim 1, wherein: the configuration tubes of the configurable charging tube are all connected with an MOS tube in series, and the G pole of each MOS tube is respectively connected with a corresponding control signal conf [ n ]; and the G poles of the main charging tube and the G poles of the configuration tube are both connected with a clock signal.

5. The apparatus for improving randomness of an output sequence according to claim 1, wherein: the configurable clock delay unit further comprises 5 MOS tubes PQ1, PQ2, PQ3, PQ4 and PQ5, wherein the PQ1 and the PQ3 are connected in series, the D poles of the PQ1 and the PQ3 are connected with the G poles of PQ5, PQ2 and PQ4, and the S poles of the PQ2 and the S poles of the PQ4 are respectively connected; the PQ5 is connected in parallel with the configuration tube of the configurable clock delay unit, the D pole of the PQ5 is connected with the D pole of the PQ2, and the S pole of the PQ5 is connected with the D pole of the PQ 4; the configuration pipes of the configurable clock delay units are respectively connected with control signals CLK [ n ].

6. The apparatus for improving randomness of an output sequence according to claim 1, wherein: the configurable clock delay unit and the configurable charging tube are two, and the finite state machine is respectively in communication connection with each configurable clock delay unit and the configurable charging tube.

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