CN107342296A - 半导体装置和包括该半导体装置的显示装置 - Google Patents
半导体装置和包括该半导体装置的显示装置 Download PDFInfo
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- CN107342296A CN107342296A CN201710301139.3A CN201710301139A CN107342296A CN 107342296 A CN107342296 A CN 107342296A CN 201710301139 A CN201710301139 A CN 201710301139A CN 107342296 A CN107342296 A CN 107342296A
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Classifications
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Abstract
公开了一种半导体装置和一种包括该半导体装置的显示装置。该半导体装置包括半导体层、第一栅电极和第二栅电极。半导体层包括从沟道区延伸的第一源区、第一漏区、第二源区和第二漏区。第一栅电极设置在半导体层下方。第一栅电极通过第一栅极绝缘层与半导体层绝缘。第一栅电极与共用的沟道区至少部分地叠置。第二栅电极设置在半导体层上方。第二栅电极通过第二栅极绝缘层与半导体层绝缘。第二栅电极与共用的沟道区至少部分地叠置。
Description
本申请要求于2016年5月2日提交到韩国知识产权局的第10-2016-0054105号韩国专利申请的权益,该专利申请的公开内容通过引用全部包含于此。
技术领域
本发明涉及一种半导体装置和一种包括该半导体装置的显示装置。
背景技术
显示装置是显示图像的设备。显示装置的变化形式包括液晶显示器(LCD)、电泳显示器、有机发光显示器(OLED)、无机发光显示器、场发射显示器、表面传导电子发射显示器、等离子体显示器和阴极射线显示器。
显示装置可以包括显示元件、薄膜晶体管、电容器和布线。布线将显示元件、薄膜晶体管和电容器彼此连接。为了提供显示装置的高分辨率,会期望高性能的薄膜晶体管。
发明内容
本发明的示例性实施例提供了一种半导体装置。该半导体装置包括半导体层、第一栅电极和第二栅电极。半导体层包括从共用的沟道区延伸的第一源区、第一漏区、第二源区和第二漏区。第一栅电极设置在半导体层下方。第一栅电极通过第一栅极绝缘层与半导体层绝缘。第一栅电极与共用的沟道区至少部分地叠置。第二栅电极设置在半导体层上方。第二栅电极通过第二栅极绝缘层与半导体层绝缘。第二栅电极与共用的沟道区至少部分地叠置。
第一薄膜晶体管可以包括共用的沟道区、第一源区、第一漏区和第一栅电极。第二薄膜晶体管可以包括共用的沟道区、第二源区、第二漏区和第二栅电极。
第一栅极绝缘层的厚度可以与第二栅极绝缘层的厚度不同。
半导体装置还可以包括层间绝缘层。层间绝缘层可以设置在第二栅电极上方。半导体装置还可以包括设置在层间绝缘层上方的第一源电极、第一漏电极、第二源电极和第二漏电极。第一源电极、第一漏电极、第二源电极和第二漏电极可以经由接触孔分别连接到第一源区、第一漏区、第二源区和第二漏区。
半导体装置还可以包括电容器。电容器可以包括第一电极和第二电极。第一电极可以连接到第二栅电极。第二电极可以设置在第一电极上方。第二电极可以与第一电极绝缘。第二栅电极和第一电极可以在同一层中形成单个结构。
电容器可以包括第三栅极绝缘层。第三栅极绝缘层可以设置在第一电极与第二电极之间。
第一源区、第一漏区、第二源区和第二漏区可以彼此分隔开。
第一源区和第二源区可以形成单个区。第一漏区可以与第二漏区分隔开。
第一源区可以与第二源区分隔开。第一漏区和第二漏区可以形成单个区。
本发明的示例性实施例提供了一种显示装置。该显示装置包括所述半导体装置、平坦化层、像素电极、对电极和中间层。平坦化层覆盖半导体装置。像素电极设置在平坦化层上方。像素电极连接到第一源区、第一漏区、第二源区和第二漏区中的一个。对电极面对像素电极。中间层设置在像素电极与对电极之间。
第一薄膜晶体管可以包括共用的沟道区、第一源区、第一漏区和第一栅电极。第二薄膜晶体管可以包括共用的沟道区、第二源区、第二漏区和第二栅电极。
显示装置还可以包括被构造为传输栅极信号的栅极线、被构造为传输数据信号的数据线和被构造为传输驱动电压的驱动电压线。栅极线可以连接到第一栅电极,数据线可以连接到第一源区,驱动电压线可以连接到第二源区,像素电极可以连接到第二漏区。
第二栅极绝缘层的厚度可以比第一栅极绝缘层的厚度大。
显示装置还可以包括电容器。电容器可以包括第一电极和第二电极。第一电极可以连接到第二栅电极。第二电极可以设置在第一电极上方。第二电极可以与第一电极绝缘。第二栅电极和第一电极可以在同一层中形成单个结构。
电容器可以包括第三栅极绝缘层。第三栅极绝缘层可以设置在第一电极与第二电极之间。
显示装置还可以包括辅助电容器。辅助电容器可不与半导体装置叠置。
显示装置还可以包括像素限定层。像素限定层可以使像素电极的一部分暴露,覆盖像素电极的表面,并且限定像素。
中间层可以包括有机发射层。
本发明的示例性实施例提供了一种半导体装置。该半导体装置包括半导体层、第一栅电极和第二栅电极。半导体层包括沟道区。第一栅电极与沟道区至少部分地叠置。第二栅电极设置在半导体层上方。第二栅电极与沟道区至少部分地叠置。当从半导体层上方向着基底观察时,半导体层与第一栅电极叠置。
半导体层还可以包括第一源区、第一漏区、第二源区和第二漏区。
第一薄膜晶体管可以包括沟道区、第一源区、第一漏区和第一栅电极。第二薄膜晶体管可以包括沟道区、第二源区、第二漏区和第二栅电极。
第一栅电极可以通过第一栅极绝缘层与半导体层绝缘。第二栅电极可以通过第二栅极绝缘层与半导体层绝缘。
第一栅极绝缘层的厚度可以与第二栅极绝缘层的厚度不同。
附图说明
通过以下结合附图对示例性实施例进行描述,这些和/或其它特征将变得明显并且更容易理解,在附图中:
图1是示出根据本发明的示例性实施例的半导体装置的平面图;
图1A是示出根据本发明的示例性实施例的半导体装置的半导体层的平面图;
图1B是示出根据本发明的示例性实施例的半导体装置的半导体层的平面图;
图2是示出根据本发明的示例性实施例的图1的半导体装置沿线I-I'的剖视图;
图3是示出根据本发明的示例性实施例的半导体装置的平面图;
图4是根据本发明的示例性实施例的图3的半导体装置沿线II-II'的剖视图;
图5A是示出根据本发明的示例性实施例的半导体装置的平面图;
图5B是示出根据本发明的示例性实施例的半导体装置的平面图;
图6是示出根据本发明的示例性实施例的显示装置的一部分的平面图;
图7是示出根据本发明的示例性实施例的图6的显示装置的像素的等效电路图;
图8是示出根据本发明的示例性实施例的图6的显示装置的像素的平面图;以及
图9是根据本发明的示例性实施例的沿图8的线III-III'示出图6的显示装置的像素的剖视图。
具体实施方式
将在附图中示出并且在这里详细地描述本发明构思的示例性实施例。当参照参考附图描述的示例性实施例时,发明构思的效果和特征以及实现其的方法将是明显的。然而,发明构思可以以许多不同的形式实施,并且不应该解释为限于在这里阐述的示例性实施例。
在下文中,将参照示出发明构思的示例性实施例的附图来更充分地描述发明构思。当参照附图进行描述时,在附图中同样的附图标记表示同样的或相应的元件,并且可以省略对其重复的描述。
如这里使用的,术语“和/或”包括一个或更多个相关所列项的任何和所有组合。
将理解的是,虽然术语“第一”、“第二”等可以在此用于描述各种组件,但这些组件不应受限于这些术语。这些组件仅用来将一个组件与另一组件区分。
为了便于说明,会夸大附图中的元件的尺寸。因此,因为为了便于说明而任意示出附图中的组件的尺寸和厚度,所以以下实施例不限于此。
图1是示出根据本发明的示例性实施例的半导体装置的平面图。图1A是示出根据本发明的示例性实施例的半导体装置的半导体层的平面图。图1B是示出根据本发明的示例性实施例的半导体装置的半导体层的平面图。图2是示出根据本发明的示例性实施例的图1的半导体装置沿线I-I'的剖视图。
参照图1和图2,半导体装置10可以包括第一薄膜晶体管TFT1和第二薄膜晶体管TFT2。第一薄膜晶体管TFT1和第二薄膜晶体管TFT2可以共用半导体层211(参见图9)的沟道区211c。第一薄膜晶体管TFT1可以与第二薄膜晶体管TFT2叠置。
半导体装置10可以包括半导体层211、第一栅电极G1和第二栅电极G2。半导体层211可以包括第一源区211s1、第一漏区211d1、第二源区211s2和第二漏区211d2。半导体层211可以从设置在基底100上方的沟道区211c延伸。第一栅电极G1可以设置在半导体层211下方。第二栅电极G2可以设置在半导体层211上方。第一栅电极G1和第二栅电极G2可以与沟道区211c部分地叠置。
半导体装置10还可以包括第一栅极绝缘层121。第一栅极绝缘层121可以使第一栅电极G1与半导体层211绝缘。半导体装置10还可以包括第二栅极绝缘层123。第二栅极绝缘层123可以使第二栅电极G2与半导体层211绝缘。
根据本发明的示例性实施例,半导体装置10可以包括第一薄膜晶体管TFT1和第二薄膜晶体管TFT2。第一薄膜晶体管TFT1可以包括沟道区211c、第一源区211s1、第一漏区211d1和第一栅电极G1。第二薄膜晶体管TFT2可以包括沟道区211c、第二源区211s2、第二漏区211d2和第二栅电极G2。
半导体装置10可以设置在基底100上方。半导体装置10还可以包括第一源电极S1、第一漏电极D1、第二源电极S2和第二漏电极D2。第一源电极S1、第一漏电极D1、第二源电极S2和第二漏电极D2可以分别连接到第一源区211s1、第一漏区211d1、第二源区211s2和第二漏区211d2。
基底100可以包括诸如玻璃、金属或塑料的各种材料;然而本发明的示例性实施例不限于此。根据本发明的示例性实施例,基底100可以包括柔性基底100。柔性基底100可以包括可以弯曲、折弯、折叠或卷曲的基底。基底100可以包括具有柔性或可折弯特性的各种材料。例如,基底100可以包括诸如聚醚砜(PES)、聚丙烯酸酯、聚醚酰亚胺(PEI)、聚萘二甲酸乙二醇酯(PEN)、聚对苯二甲酸乙二醇酯(PET)、聚苯硫醚(PPS)、聚芳酯(PAR)、聚酰亚胺(PI)、聚碳酸酯(PC)或醋酸丙酸纤维素(CAP)的聚合物树脂;然而,本发明的示例性实施例不限于此。
缓冲层110可以设置在基底100上方。缓冲层110可以减少或可以阻挡外来物质、湿气或外部空气从下方的基底100渗透。此外,缓冲层110可以在基底100上方提供平坦化的表面。缓冲层110可以包括诸如氧化物或氮化物的无机材料,或者有机材料,或者有机/无机复合材料;然而,本发明的示例性实施例不限于此。缓冲层110可以包括无机材料和/或有机材料的单层或多层。
半导体层211可以包括沟道区211c以及从沟道区211c延伸的第一源区211s1、第一漏区211d1、第二源区211s2和第二漏区211d2。当驱动第一薄膜晶体管TFT1和第二薄膜晶体管TFT2时,可以分别通过第一源区211s1与第一漏区211d1之间以及第二源区211s2与第二漏区211d2之间的距离来确定沟道的长度。为了确保长的沟道长度,第一源区211s1可以与第一漏区211d1充分远地分隔开,并且沟道区211c设置在第一源区211s1与第一漏区211d1之间。相似地,第二源区211s2可以与第二漏区211d2充分远地分隔开,并且沟道区211c设置在第二源区211s2与第二漏区211d2之间。如图1中所示,第一源区211s1和第二源区211s2可以设置在沟道区211c的第一端部上。第一漏区211d1和第二漏区211d2可以设置在沟道区211c的第二端部上。然而,本发明的示例性实施例不限于此。可以各种修改第一源区211s1、第二源区211s2、第一漏区211d1和第二漏区211d2的布置,而本发明的示例性实施例不限于此。例如,半导体层211可以设置为'+'形状。第一源区211s1、第二源区211s2、第一漏区211d1和第二漏区211d2可以分别设置在其边缘处。
可以各种修改沟道区211c的形状。如图1A和图1B中所示,沟道区211c可以具有弯曲形状。具有弯曲形状的沟道区211c可以确保沟道长度。如图1A中所示,沟道区211c可以具有形状。如图1B中所示,沟道区211c可以具有形状。可以各种修改沟道区211c的形状,而本发明的示例性实施例不限于此。
半导体层211可以包括非晶硅(α-Si)、多晶硅(poly-Si)、氧化物半导体或有机半导体材料;然而,本发明的示例性实施例不限于此。当半导体层211包括硅(Si)时,第一源区211s1、第二源区211s2、第一漏区211d1和第二漏区211d2可以通过使半导体层211掺杂有杂质来形成。当半导体层211包括氧化物半导体时,第一源区211s1、第二源区211s2、第一漏区211d1和第二漏区211d2可以通过增加氧化物半导体的载流子浓度来形成。因此,氧化物半导体可以通过等离子体工艺被制成导电的;然而,本发明的示例性实施例不限于此。
第一栅电极G1可以设置在沟道区211c下方。第一栅电极G1可以与沟道区211c部分地叠置。第一栅电极G1可以连接到布线。连接到布线的第一栅电极G1可以将ON/OFF信号施加到第一薄膜晶体管TFT1。第二栅电极G2可以设置在沟道区211c上方。第二栅电极G2可以与沟道区211c部分地叠置。第二栅电极G2可以连接到布线。连接到布线的第二栅电极G2可以将ON/OFF信号施加到第二薄膜晶体管TFT2。第一栅电极G1可以与第二栅电极G2叠置。
第一栅电极G1和第二栅电极G2可以包括低电阻金属。例如,第一栅电极G1和第二栅电极G2可以具有包括钼(Mo)、铝(Al)、铜(Cu)和/或钛(Ti)的导电材料;然而,本发明的示例性实施例不限于此。第一栅电极G1和第二栅电极G2可以包括单层或多层。
第一栅极绝缘层121可以包括诸如氧化硅、氮化硅和/或氮氧化硅的无机材料。第一栅极绝缘层121可以设置在半导体层211与第一栅电极G1之间。第一栅极绝缘层121可以被构造为使半导体层211与第一栅电极G1之间的区域绝缘。第二栅极绝缘层123可以包括诸如氧化硅、氮化硅和/或氮氧化硅的无机材料。第二栅极绝缘层123可以设置在半导体层211与第二栅电极G2之间。第二栅极绝缘层123可以被构造为使半导体层211与第二栅电极G2之间的区域绝缘。另外,层间绝缘层130可以设置在第二栅电极G2上方。层间绝缘层130可以包括诸如氧化硅、氮化硅和/或氮氧化硅的无机材料。第一源电极S1、第一漏电极D1、第二源电极S2和第二漏电极D2可以设置在层间绝缘层130上方。包括无机材料的层间绝缘层130可以通过化学气相沉积(CVD)或原子层沉积(ALD)来形成;然而,本发明的示例性实施例不限于此。
第一栅极绝缘层121的厚度t1和第二栅极绝缘层123的厚度t2可以不同。第一薄膜晶体管TFT1的驱动范围和第二薄膜晶体管TFT2的驱动范围可以分别通过调整第一栅极绝缘层121的厚度t1和第二栅极绝缘层123的厚度t2来调整。
第一源电极S1、第一漏电极D1、第二源电极S2和第二漏电极D2可以包括单层或多层。第一源电极S1、第一漏电极D1、第二源电极S2和第二漏电极D2可以包括具有高导电性的导电材料。第一源电极S1、第一漏电极D1、第二源电极S2和第二漏电极D2可以分别连接到半导体层211的第一源区211s1、第一漏区211d1、第二源区211s2和第二漏区211d2。例如,第一源电极S1、第一漏电极D1、第二源电极S2和第二漏电极D2可以包括具有铝(Al)、铜(Cu)和/或钛(Ti)的导电材料;然而,本发明的示例性实施例不限于此。第一源电极S1、第一漏电极D1、第二源电极S2和第二漏电极D2可以包括单层或多层。
第一源电极S1、第一漏电极D1、第二源电极S2和第二漏电极D2可以经由接触孔CNT连接到半导体层211。接触孔CNT可以穿过层间绝缘层130。接触孔CNT还可以穿过第二栅极绝缘层123。接触孔CNT可以通过基本同时蚀刻层间绝缘层130和第二栅极绝缘层123来形成。
第一薄膜晶体管TFT1和第二薄膜晶体管TFT2可以被单独地驱动。例如,当向第一薄膜晶体管TFT1的第一源区211s1、第一漏区211d1和第一栅电极G1施加驱动电压,而未向第二薄膜晶体管TFT2的第二源区211s2、第二漏区211d2和第二栅电极G2施加驱动电压时,可以驱动第一薄膜晶体管TFT1,而不会驱动第二薄膜晶体管TFT2。当向第一源区211s1、第一漏区211d1、第一栅电极G1、第二源区211s2、第二漏区211d2和第二栅电极G2施加驱动电压时,可以基本同时驱动第一薄膜晶体管TFT1和第二薄膜晶体管TFT2。
根据本发明的示例性实施例,因为半导体装置10可以具有其中堆叠有共用半导体层211的沟道区211c的第一薄膜晶体管TFT1和第二薄膜晶体管TFT2的结构,所以包括半导体装置10的显示装置可以允许高度集成。
图3是示出根据本发明的示例性实施例的半导体装置20的平面图。图4是示出根据本发明的示例性实施例的图3的半导体装置20沿线II-II'的剖视图。
参照图3和图4,半导体装置20还可以包括电容器CAP。电容器CAP可以包括第一电极C1。第一电极C1可以连接到第二栅电极G2。第一电极C1还可以与第二电极C2叠置。第二电极C2可以设置在第一电极C1上方。第二电极C2可以与第一电极C1绝缘。第二栅电极G2和第一电极C1可以整体地设置在同一层中。例如,第二栅电极G2可以被构造为第二薄膜晶体管TFT2的栅电极。第二栅电极G2可以基本同时被构造为电容器CAP的第一电极C1。
第三栅极绝缘层125可以设置在第二栅电极G2与第二电极C2之间。第三栅极绝缘层125可以包括诸如氧化硅、氮化硅和/或氮氧化硅的无机材料;然而,本发明的示例性实施例不限于此。第三栅极绝缘层125可以通过化学气相沉积(CVD)或原子层沉积(ALD)来形成。第三栅极绝缘层125可以被构造为使第二栅电极G2与第二电极C2之间的区域绝缘。
因为电容器CAP可以在半导体装置20中与第一薄膜晶体管TFT1和第二薄膜晶体管TFT2叠置,所以可以获得高度集成。
图5A和图5B是分别示出根据本发明的示例性实施例的半导体装置30和半导体装置40的平面图。
参照图5A,半导体装置30的第一薄膜晶体管TFT1和第二薄膜晶体管TFT2可以共用源区。例如,在半导体装置30中,第一源区和第二源区可以整体地设置为211s。第一漏区211d1可以与第二漏区211d2分隔开。因此,第一源电极和第二源电极可以整体地设置为S。
当将基本相同的电势供应到半导体装置30的第一薄膜晶体管TFT1的源区和第二薄膜晶体管TFT2的源区时,可以设置共用源区的结构。
参照图5B,半导体装置40的第一薄膜晶体管TFT1和第二薄膜晶体管TFT2可以共用漏区。如所示的,在半导体装置40中,第一源区211s1可以与第二源区211s2分隔开。第一漏区和第二漏区可以整体地设置为211d。因此,第一漏电极和第二漏电极可以整体地设置为D。
当将基本相同的电势供应到半导体装置40的第一薄膜晶体管TFT1的漏区和第二薄膜晶体管TFT2的漏区时,可以设置共用漏区的结构。
半导体装置10、20、30和40以及它们的修改可以应用于显示装置。
显示装置是显示图像的设备。显示装置可以是液晶显示器(LCD)、电泳显示器、有机发光显示器(OLED)、无机发光显示器、场发射显示器、表面传导电子发射显示器、等离子体显示器和阴极射线显示器;然而,本发明的示例性实施例不限于此。
虽然在这里描述了根据本发明的示例性实施例的有机发光显示(OLED)装置,但本发明的示例性实施例不限于此,可以使用各种类型的显示装置。
图6是示出根据本发明的示例性实施例的显示装置的一部分的平面图。如图6中所示,显示装置可以包括基底100。如图6中所示,显示装置的基底100可以包括显示区域DA。显示装置的基底100还可以包括***区域PA。***区域PA可以设置在显示区域DA外部。诸如有机发光二极管(OLED)的各种显示元件可以设置在基底100的显示区域DA上。各种布线可以设置在基底100的***区域PA上。各种布线可以传输电信号。各种布线的电信号可以施加到显示区域DA。
图7是示出根据本发明的示例性实施例的图6的显示装置的像素的等效电路图。图7示出了根据本发明的示例性实施例的包括有机发光二极管OLED的像素。
参照图7,每个像素PX可以包括像素电路PC。像素电路PC可以连接到扫描线SL。像素电路PC还可以连接到数据线DL。有机发光二极管OLED可以连接到像素电路PC。
像素电路PC可以包括第一薄膜晶体管TFT1、第二薄膜晶体管TFT2和电容器CAP。第一薄膜晶体管TFT1可以连接到扫描线SL。第一薄膜晶体管TFT1还可以连接到数据线DL。第一薄膜晶体管TFT1可以响应于经由扫描线SL输入的扫描信号Sn来将经由数据线DL输入的数据信号Dm传输到第二薄膜晶体管TFT2。
电容器CAP可以连接到第一薄膜晶体管TFT1。电容器CAP还可以连接到驱动电压线PL。电容器CAP可以存储电压。该电压可以与从第一薄膜晶体管TFT1接收的电压与供应给驱动电压线PL的驱动电压ELVDD之间的差对应。
第二薄膜晶体管TFT2可以连接到驱动电压线PL。第二薄膜晶体管TFT2还可以连接到电容器CAP。第二薄膜晶体管TFT2可以控制驱动电流。驱动电流可以响应于存储在电容器CAP中的电压值而从驱动电压线PL流经有机发光二极管OLED。有机发光二极管OLED可以发射光。通过有机发光二极管OLED发射的光可以通过使用驱动电流而具有预定亮度。
图8是示出根据本发明的示例性实施例的图6的显示装置的像素的平面图。图9是示出根据本发明的示例性实施例的图8的沿线III-III'的像素的剖视图。
参照图8和图9,除了如在图4中示出的半导体装置20之外,显示装置可以包括各种信号线和显示元件。各种信号线可以包括栅极线GL、数据线DL和驱动电压线PL。显示元件可以包括有机发光二极管(OLED)300。信号线可以被多个像素共用。
半导体装置可以包括第一薄膜晶体管TFT1和第二薄膜晶体管TFT2。有机发光二极管(OLED)300可以连接到第一薄膜晶体管TFT1。可选地,有机发光二极管(OLED)300可以连接到第二薄膜晶体管TFT2。如图9中所示,有机发光二极管(OLED)300可以连接到第二薄膜晶体管TFT2。因此,第二薄膜晶体管TFT2可以被构造为驱动薄膜晶体管。驱动薄膜晶体管可以驱动有机发光二极管(OLED)300。第一薄膜晶体管TFT1可以被构造为开关薄膜晶体管。
当第二薄膜晶体管TFT2被构造为驱动薄膜晶体管时,第二薄膜晶体管TFT2可能需要驱动。因此,可以提供比第一薄膜晶体管TFT1较精细的调整。因为可以通过第二栅极绝缘层123的厚度t2来调整驱动范围,所以可以通过比第一栅极绝缘层121的厚度t1大的第二栅极绝缘层123的厚度t2来获得较精细的调整。
显示装置还可以包括辅助电容器CAP1。辅助电容器CAP1可不与半导体装置叠置。辅助电容器CAP1可以包括第三电极C3。辅助电容器CAP1还可以包括第四电极C4。第四电极C4可以与第三电极C3叠置。绝缘层可以设置在第三电极C3与第四电极C4之间。绝缘层可以被构造为介电层。如图9中所示,第三栅极绝缘层125可以设置在第三电极C3与第四电极C4之间。还如图9中所示,第三电极C3可以与第二栅电极G2分隔开。第三电极C3可以包括与第二栅电极G2基本相同的材料。第三电极C3可以与第二栅电极G2设置在同一层中。第四电极C4可以与电容器CAP的第二电极C2分隔开。第四电极C4可以包括与第二电极C2基本相同的材料。第四电极C4可以与第二电极C2设置在同一层上。然而,本发明的示例性实施例不限于此。例如,层间绝缘层130可以设置在第三电极C3与第四电极C4之间。第三电极C3可以与第二电极C2设置在同一层上。第四电极C4可以与第一源电极S1设置在同一层上;然而,本发明的示例性实施例不限于此。辅助电容器CAP1可以连接到电容器CAP。辅助电容器CAP1可以被构造为存储电容器。
根据本发明的示例性实施例,因为电容器CAP可以与第一薄膜晶体管TFT1和第二薄膜晶体管TFT2叠置,所以显示装置可以确保用于形成辅助电容器CAP1的额外空间。
如图8中所示,栅极线GL可以连接到第一栅电极G1。数据线DL可以连接到第一源电极S1。驱动电压线PL可以连接到第二源电极S2;然而,本发明的示例性实施例不限于此,可以根据第一薄膜晶体管TFT1和第二薄膜晶体管TFT2的构造来提供各种修改。
平坦化层140可以设置在半导体装置上方。例如,当有机发光二极管(OLED)300如图9中所示设置在半导体装置上方时,平坦化层140可以大体上使覆盖半导体装置的保护层的上部平坦化。平坦化层140可以包括诸如亚克力、苯并环丁烯(BCB)或六甲基二硅醚(HMDSO)的有机材料;然而,本发明的示例性实施例不限于此。如图9中所示,平坦化层140可以包括单层。平坦化层140还可以包括多层。然而,本发明的示例性实施例不限于此,可以进行各种修改。
有机发光二极管(OLED)300可以设置在平坦化层140上方。有机发光二极管(OLED)300可以包括像素电极310、对电极330和中间层320。中间层320可以设置在像素电极310与对电极330之间。中间层320可以包括发射层。像素电极310可以连接到第一薄膜晶体管TFT1。可选地,像素电极310可以连接到第二薄膜晶体管TFT2。参照图8和图9,像素电极310可以经由平坦化层140中的开口通过接触第一源电极S1、第一漏电极D1、第二源电极S2和第二漏电极D2中的一个来连接到第一薄膜晶体管TFT1或第二薄膜晶体管TFT2。如图8和图9中所示,像素电极310可以连接到第二漏电极D2。
像素电极310可以设置为透明电极。可选地,像素电极310可以设置为反射电极。当像素电极310是透明电极时,像素电极310可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)或氧化铟(III)(In2O3)。当像素电极310是反射电极时,像素电极310可以包括反射层和透明层。反射层可以包括银(Ag)、镁(Mg)、铝(Al)、铂(Pt)、钯(Pd)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)或它们的混合物。透明层可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)或氧化铟(III)(In2O3)。根据本发明的示例性实施例,像素电极310可以具有氧化铟锡(ITO)/银(Ag)/氧化铟锡(ITO)的结构。
像素限定层150可以设置在平坦化层140上方。像素限定层150可以通过具有与各自子像素对应的开口来限定像素。如此,像素限定层150可以通过具有使像素电极310的至少中间部分暴露的开口来限定像素。如图9中所示,像素限定层150可以防止在像素电极310的边缘处发生电弧等。像素限定层150可以使像素电极310的边缘与设置在像素电极310上方的对电极330之间的距离增加。像素限定层150可以包括有机材料,诸如聚酰亚胺(PI)或六甲基二硅醚(HMDSO);然而,本发明的示例性实施例不限于此。
有机发光二极管(OLED)300的中间层320可以包括低分子材料或聚合物材料。当中间层320包括低分子材料时,中间层320可以具有如下结构:空穴注入层(HIL)、空穴传输层(HTL)、有机发射层(EML)、电子传输层(ETL)、电子注入层(EIL)以单一结构或复合结构堆叠。中间层320可以包括诸如铜酞菁(CuPc)、N,N'-二(萘-1-基)-N,N'-二苯基-联苯胺(NPB)和三-8-羟基喹啉铝(Alq3)的有机材料;然而,本发明的示例性实施例不限于此。中间层320的层可以通过使用真空沉积方法来形成。
当中间层320包括聚合物材料时,中间层320可以具有包括空穴传输层(HTL)和有机发射层(EML)的结构。空穴传输层(HTL)可以包括聚(3,4-乙撑二氧噻吩)(PEDOT)。有机发射层(EML)可以包括诸如聚苯撑乙烯撑(PPV)类材料和/或聚芴类材料的聚合物材料;然而,本发明的示例性实施例不限于此。中间层320可以通过使用丝网印刷、喷墨印刷方法或激光诱导热成像(LITI)来形成;然而,本发明的示例性实施例不限于此。
中间层320可以具有各种结构。中间层320可以包括整体地形成在多个像素电极310之上的层。中间层320也可以包括图案化为与多个像素电极310对应的层。
对电极330可以面朝像素电极310。中间层320可以设置在对电极330与像素电极310之间。对电极330可以整体地设置在多个有机发光二极管(OLED)300上。对电极330可以与多个像素电极310对应。例如,像素电极310可以在基本每个像素处被图案化。对电极330可以形成为使得共电压可以施加到基本所有像素。对电极330可以是透明电极。可选地,对电极330可以是反射电极。
从有机发光二极管(OLED)300的像素电极310和对电极330注入的空穴和电子可以在中间层320的发射层中结合,从而发射光。
因为有机发光二极管(OLED)300可能容易被外部湿气或氧等损坏,所以薄膜包封层400可以覆盖并且可以保护有机发光二极管(OLED)。薄膜包封层400可以包括至少一个有机包封层。薄膜包封层400还可以包括至少一个无机包封层。例如,薄膜包封层400可以包括第一无机包封层410、有机包封层420和第二无机包封层430,如图9中所示。
第一无机包封层410可以覆盖对电极330。第一无机包封层410可以包括氧化硅、氮化硅和/或氮氧化硅;然而,本发明的示例性实施例不限于此。诸如覆盖层的其它层可以设置在第一无机包封层410与对电极330之间。如图9中所示,因为第一无机包封层410可以沿设置在其下方的结构来设置,所以第一无机包封层410的上表面不会被平坦化。有机包封层420可以覆盖第一无机包封层410。与第一无机包封层410不同,有机包封层420的上表面可以被近似基本平坦化。有机包封层420可以包括聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、聚碳酸酯(PC)、聚酰亚胺(PI)、聚乙烯磺酸盐、聚甲醛(POM)、聚丙烯酸酯和六甲基二硅醚(HMDSO)中的至少一种;然而,本发明的示例性实施例不限于此。第二无机包封层430可以覆盖有机包封层420。第二无机包封层430可以包括氧化硅、氮化硅和/或氮氧化硅;然而,本发明的示例性实施例不限于此。
因为薄膜包封层400可以包括第一无机包封层410、有机包封层420和第二无机包封层430,所以当在包封层400内部出现裂缝时,由于多层结构而不会允许裂缝在第一无机包封层410与有机包封层420之间或有机包封层420与第二无机包封层430之间连接。因此,可以防止外部湿气或氧可能渗透到有机发光二极管(OLED)300中所经由的路径的形成或者可以使该路径的形成最小化。
参照图6和图9,可以用密封基底来代替薄膜包封层400。密封基底可以包括玻璃等。密封基底可以通过密封构件附着到基底100。密封构件可以围绕显示区域DA。另外,偏振板、滤色器或触摸面板等还可以设置在薄膜包封层400或密封基底上方。
根据本发明的示例性实施例,因为显示装置可以包括具有其中堆叠有共用半导体层的沟道区的第一薄膜晶体管TFT1和第二薄膜晶体管TFT2的结构的半导体装置10、20、30或40,所以可以实施高度集成。
虽然已经参照在附图中示出的示例性实施例描述了发明构思,但本领域普通技术人员将理解的是,在不脱离如权利要求所限定的发明构思的精神和范围的情况下,可以在这里做出形式和细节上的各种改变及其等同物。
Claims (10)
1.一种半导体装置,所述半导体装置包括:
半导体层,所述半导体层包括连接到沟道区的第一源区、第一漏区、第二源区和第二漏区;
第一栅电极,设置在所述半导体层下方,所述第一栅电极通过第一栅极绝缘层与所述半导体层绝缘并且与所述沟道区至少部分地叠置;以及
第二栅电极,设置在所述半导体层上方,所述第二栅电极通过第二栅极绝缘层与所述半导体层绝缘并且与所述沟道区至少部分地叠置。
2.一种显示装置,所述显示装置包括:
权利要求1所述的半导体装置;
平坦化层,覆盖所述半导体装置;
像素电极,设置在所述平坦化层上方,并且连接到所述第一源区、所述第一漏区、所述第二源区和所述第二漏区中的一个;
对电极,面对所述像素电极;以及
中间层,设置在所述像素电极与所述对电极之间。
3.根据权利要求2所述的显示装置,第一薄膜晶体管包括所述沟道区、所述第一源区、所述第一漏区和所述第一栅电极,
第二薄膜晶体管包括所述沟道区、所述第二源区、所述第二漏区和所述第二栅电极。
4.根据权利要求2所述的显示装置,所述显示装置还包括被构造为传输栅极信号的栅极线、被构造为传输数据信号的数据线以及被构造为传输驱动电压的驱动电压线,其中,所述栅极线连接到所述第一栅电极,所述数据线连接到所述第一源区,所述驱动电压线连接到所述第二源区,所述像素电极连接到所述第二漏区。
5.根据权利要求4所述的显示装置,其中,所述第二栅极绝缘层的厚度比所述第一栅极绝缘层的厚度大。
6.根据权利要求2所述的显示装置,所述显示装置还包括:
电容器,包括连接到所述第二栅电极的第一电极和设置在所述第一电极上方并且与所述第一电极绝缘的第二电极,
其中,所述第二栅电极和所述第一电极在同一层中形成单个结构。
7.根据权利要求6所述的显示装置,其中,所述电容器包括设置在所述第一电极与所述第二电极之间的第三栅极绝缘层。
8.根据权利要求2所述的显示装置,所述显示装置还包括辅助电容器,其中,所述辅助电容器不与所述半导体装置叠置。
9.根据权利要求2所述的显示装置,所述显示装置还包括像素限定层,其中,所述像素限定层使所述像素电极的一部分暴露,覆盖所述像素电极的表面,并且限定像素。
10.根据权利要求2所述的显示装置,其中,所述中间层包括有机发射层。
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CN111554736A (zh) * | 2019-02-11 | 2020-08-18 | 三星显示有限公司 | 显示装置 |
CN115244599A (zh) * | 2020-03-11 | 2022-10-25 | 夏普株式会社 | 显示装置 |
CN115244599B (zh) * | 2020-03-11 | 2023-08-01 | 夏普株式会社 | 显示装置 |
CN111785739A (zh) * | 2020-07-16 | 2020-10-16 | 昆山国显光电有限公司 | 互补薄膜晶体管及其制作方法、显示面板 |
CN111785739B (zh) * | 2020-07-16 | 2022-10-28 | 昆山国显光电有限公司 | 互补薄膜晶体管及其制作方法、显示面板 |
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CN107342296B (zh) | 2023-08-11 |
US10153336B2 (en) | 2018-12-11 |
US20170317159A1 (en) | 2017-11-02 |
KR20170124672A (ko) | 2017-11-13 |
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