CN107316819A - 芯片封装体及芯片封装制程 - Google Patents
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Abstract
本发明提供一种芯片封装体及芯片封装制程,其包括:一具有一导电柱的线路载板、一芯片、一封装胶体、一导电层以及多个外部端子。封装胶体配置在线路载板上,并包覆芯片及导电柱。导电柱顶面暴露于封装胶体外且配置在线路载板上。芯片配置在线路载板上,而线路载板通过至少一焊线与芯片电性连接。外部端子位于在线路载板上,与芯片位于线路载板不同侧,并通过线路载板与芯片电性连接。封装胶体上有一导电层,导电层与导电柱的顶面连接,使导电层通过导电柱与线路载板及芯片电性连接。综上所述,本发明技术方案可以提升芯片封装制程的封装良率。
Description
技术领域
本发明是有关于一种芯片封装体及芯片封装制程,且特别是有关于一种具有导电柱的芯片封装体及芯片封装制程。
背景技术
在半导体产业中,积体电路(Integrated Circuits,IC)的生产,主要分为三个阶段:晶圆(wafer)的制造、积体电路的制作以及芯片的封装(Package)等。其中,芯片系经由晶圆制作、电路设计、光罩制作、电路制作以及切割晶圆等步骤而完成,而每一颗由晶圆切割所形成的芯片,在经由芯片上的接点与外部信号电性连接后,可再以封装胶体材料将芯片包覆,其封装的目的在于防止芯片受到湿气、热量、噪声的影响,并提供芯片与外部电路之间电性连接的媒介,如此即完成积体电路的生产。
在通讯元件的制造过程中,在以封装胶体将通讯芯片包覆之后,须进一步制作外部天线,此外部天线的制作包括形成外部天线本身以及连接于外部天线与通讯芯片之间的接触导体。一般而言,前述的接触导体通常是在封装胶体制作完成之后以激光钻孔搭配导电材料的填入进行制作。
然而,因为封装胶体过厚且激光的能量不易控制,所以以激光钻孔方式于封装胶体中形成接触开口面临了制程裕度(process window)不足的问题。因此,外部天线与通讯芯片之间的电性连接有可能会出现开路或电气特性不佳等问题,进而导致通讯元件的封装良率无法有效被提升。因此,如何进一步提升通讯元件的封装良率,实已成目前亟欲解决的课题。
发明内容
本发明提供多种芯片封装体以及多种芯片封装制程。
本发明提供一种芯片封装制程,其包括下列步骤。提供线路载板,此线路载板上具有导电柱。将芯片置于线路载板上,其中芯片通过至少一焊线与线路载板电性连接。在线路载板上形成封装胶体,以包覆芯片及导电柱。移除部分的封装胶体,以暴露出导电柱的顶面。在封装胶体上形成与导电柱顶面连接的导电层,此导电层通过线路载板与芯片电性连接。在线路载板上形成多个外部端子,此外部端子与芯片在线路载板的不同侧的,且外部端子通过线路载板与芯片电性连接。
本发明提供一种芯片封装体,其包括线路载板、芯片、封装胶体、导电层以及多个外部端子。线路载板具有导电柱。芯片配置在线路载板上,并且通过至少一焊线与线路载板电性连接。封装胶体配置在线路载板上,其中封装胶体包覆芯片及导电柱,且导电柱的顶面暴露于封装胶体外。导电层配置在封装胶体上以与导电柱的顶面连接,其中导电层通过线路载板与芯片电性连接。外部端子与芯片位于线路载板的不同侧,且外部端子通过线路载板与芯片电性连接。
在本发明的一实施例中,移除部分的封装胶体的方法包括研磨。
在本发明的一实施例中,形成导电层的方法包括电镀。
在本发明的一实施例中,导电柱与芯片位于线路载板的同侧,且导电柱的高度大于芯片的厚度。
本发明提供另一种芯片封装制程,其包括下列步骤。提供线路载板,此线路载板上具有导电柱。将芯片置于线路载板,其中芯片通过至少一焊线与线路载板电性连接。在线路载板上形成封装胶体,以包覆芯片及导电柱。移除部分的封装胶体,以在封装胶体内形成开口,且此开口暴露出导电柱的顶面。在开口中填入接触导体。在封装胶体上形成与接触导体顶面连接的导电层,此导电层通过接触导体及线路载板与芯片电性连接。
本发明提供另一种芯片封装体,其包括线路载板、接触导体、芯片、封装胶体、导电层以及多个外部端子。线路载板具有导电柱。接触导体配置在导电柱上。芯片配置在线路载板上,并且与线路载板电性连接。封装胶体配置在线路载板上,其中封装胶体包覆芯片、导电柱及接触导体,且接触导体的顶面暴露在封装胶体外。导电层配置在封装胶体上以与接触导体的顶面连接,其中导电层通过接触导体及线路载板与芯片电性连接。外部端子与芯片位于线路载板的不同侧,且外部端子通过线路载板与芯片电性连接。
在本发明的另一实施例中,移除部分的封装胶体以在封装胶体内形成开口的方法包括激光钻孔。
在本发明的另一实施例中,形成导电层的方法包括电镀。
在本发明的另一实施例中,还包括于线路载板上形成多个外部端子,其中外部端子与芯片位于线路载板的不同侧,且外部端子通过线路载板与芯片电性连接。
在本发明的另一实施例中,导电柱、接触导体与芯片位于线路载板的同侧。
基于上述,本发明上述实施例在形成封装胶体之前先在线路载板上形成导电柱,此制程顺序可以提升芯片封装制程的封装良率。此外,由于导电柱的制作早于封装胶体的形成,因此封装胶体的厚度不会影响到导电柱的制作良率。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。
附图说明
图1A至图1D是依照本发明第一实施例的一种芯片封装体的制造流程示意图;
图1D是依照本发明第一实施例的芯片封装体的剖面示意图;
图2A至图2D是依照本发明第二实施例的一种芯片封装体的制造流程示意图;
图2D是依照本发明第二实施例的芯片封装体的剖面示意图。
附图标记说明:
200、200’:芯片封装体;
210:线路载板;
210a:第一表面;
210b:第二表面;
S1、S2:表面;
212a:第一接垫;
212b:第二接垫;
214a:第一防焊层;
214b:第二防焊层;
C:导体;
216:外部端子;
220、220’:导电柱;
H、H’:高度;
220a:顶面;
230:芯片;
240:焊线;
250、250’、251:封装胶体;
252:接触开口;
T1、T2、T3:厚度;
260:接触导体;
260a:顶面;
270:导电层。
具体实施方式
图1A至图1D是依照本发明第一实施例的一种芯片封装体的制造流程示意图。首先,请参照图1A,提供已形成有导电柱220的线路载板210,其中线路载板210具有第一表面210a以及第二表面210b,且导电柱220位于线路载板210的第一表面210a上。具体而言,线路载板210包括核心层212、导体C、第一接垫212a、第二接垫212b、第一防焊层214a以及第二防焊层214b,其中核心层212为硬质或可挠性的介电材料,第一接垫212a与第二接垫212b分别位于核心层212的二相对表面S1、S2上,且第一接垫212a分别与通过嵌于核心层212中的导体C与对应的第二接垫212b电性连接。第一防焊层214a与第二防焊层214b分别覆盖在核心层212的二相对表面S1、S2上,并暴露出第一接垫212a与第二接垫212b。在一实施例中,导电柱220位于线路载板210的核心层212的表面S1上,且导电柱220例如是嵌于第一防焊层214a中。然而,本发明不限定导电柱220必须嵌于第一防焊层214a中。换言之,在其他实施例中,导电柱220可以是配置在线路载板210(即第一防焊层214a)的第一表面210a上。或者,导电柱220除了可嵌于第一防焊层214a中,还可进一步嵌于或延伸至核心层212中。
在本实施例中,线路载板210例如是具有单层线路的印刷电路板或具有多层线路的印刷电路板。前述的线路载板210可为硬质线路载板或可挠性线路载板。第一接垫212a及第二接垫212b的材料例如是铜、镍、金、锡或上述的组合,第一防焊层214a以及第二防焊层214b的材料例如是环氧树酯或其他防焊材质,而导电柱220的材料例如是铜或铜合金。
接着,请参考图1B,将芯片230置于线路载板210的第一表面210a上,以使芯片230与导电柱220位于线路载板210的同一侧,接着,通过至少一焊线240使芯片230与线路载板210上的第一接垫212a电性连接。
如图1B所示,前述的导电柱220、芯片230及焊线240皆位于线路载板210的同一侧。在一实施例中,芯片230配置在防焊层214a的表面上。在完成芯片230与线路载板210的接合之后,芯片230会通过线路载板210内之导体C与导电柱220电性连接。
在完成芯片230与线路载板210的接合之后,接着,于线路载板210上形成封装胶体250,以包覆导电柱220及芯片230。具体而言,前述的封装胶体250除了包覆导电柱220及芯片230之外,可进一步包覆焊线240以及被防焊层214a所暴露的第一接垫212a。在本实施例中,芯片230例如通讯芯片,焊线240例如金线,而封装胶体250例如是以射出成型(mold injection)的方式制作,且芯片230的厚度及焊线240弧高决定了所欲形成的封装胶体250的厚度T1。此处,封装胶体250的厚度T1足以覆盖住导电柱220的顶面220a。
在完成封装胶体250的制作之后,本实施例可于线路载板210的第二表面210b上形成外部端子216,其中外部端子216与被防焊层214b所暴露出的第二接垫212b电性连接。举例而言,外部端子216可为焊球、凸块等,且芯片230可通过焊线240、第一接垫212a、导体C、第二接垫212b以及外部端子216与外部元件电性连接。
然后,请参考图1C,移除部分的封装胶体250,直到导电柱220的顶面220a被暴露。在本实施例中,封装胶体250可通过研磨制程、蚀刻制程或其他制程进行薄化,以形成封装胶体250’。值得注意的是,当厚度为T1的封装胶体250被薄化而成为封装胶体250’时,封装胶体250’的厚度为T2。。
请参考图1D,在形成封装胶体250’之后,接着于封装胶体250’上形成一导电层270,此导电层270与导电柱220的顶面220a连接,使导电层270通过导电柱220、线路载板210与芯片230电性连接。此外,在本实施例中,形成导电层270的方法例如是电镀、溅镀或其他适当的成膜制程,导电层270的材料例如是金属。在本实施例中,导电层270可作为天线层。
在本实施例中,如图1C与图1D所示,由于导电柱220可预先行制作并设置在线路载板210上,因此本实施例可精准地控制导电柱220的顶面220a的平整度,以使顶面220a与薄化后的封装胶体250’的顶面切齐(实质上共平面),进而使得后续形成的导电层270能够顺利地与导电柱220的顶面220a电性连接。在导电柱220的顶面220a的平整度获得良好控制的情况下,导电层270与导电柱220的顶面220a会形成良好的欧姆接触,使得整体的封装信赖性获得提升。
经过上述制程后即可大致上完成本实施例的芯片封装体200的制作。上述的芯片封装体200包括线路载板210、导电柱220、芯片230、焊线240、封装胶体250’、导电层270及外部端子216。线路载板210具有第一表面210a以及第二表面210b,且导电柱220、芯片230、焊线240、封装胶体250’及导电层270位于线路载板210的第一表面210a上,外部端子216位于线路载板210的第二表面210b上。在一实施例中,线路载板210包括核心层212、导体C、第一接垫212a、第二接垫212b、第一防焊层214a以及第二防焊层214b,第一接垫212a与第二接垫212b分别位于核心层212的二相对表面S1、S2上,且第一接垫212a分别与通过嵌于核心层212中的导体C与对应的第二接垫212b电性连接。芯片230通过至少一焊线240与被防焊层214a所暴露出的第一接垫212a电性连接。外部端子216与被防焊层214b所暴露出的第二接垫212b电性连接。因此,芯片230通过至少一焊线240、第一接垫212a、导体C、第二接垫212b以及外部端子216与外部元件电性连接。封装胶体250’配置于线路载板上,除了包覆芯片230及导电柱220,可进一步包覆焊线240以及被防焊层214a所暴露的第一接垫212a,并使导电柱220暴露出导电柱220的顶面220a。导电层270配置于封装胶体250’上,使导电层270接触导电柱220的顶面220a,且通过导电柱220、线路载板210与芯片230电性连接。
以下将以不同的实施例来说明芯片封装体的制造流程。在此必须说明的是,下述实施例延用前述实施例的元件标号与部分内容,其中采用相同的标号来表示相同或近似的元件,并且省略了相同技术内容的说明。关于省略部分的说明可以参考前述实施例,下述实施例不再重述。
图2A至图2D是依照本发明第二实施例的一种芯片封装体的制造流程示意图。首先,请参照图1A、图1B、图2A以及图2B,本实施例中具有导电柱220’的线路载板210与图1A及图1B中所示出的具有导电柱220的线路载板210相似,二者之间不同之处在于:本实施例(图2A及图2B)中形成于线路载板210上的导电柱220’较导电柱220(图1A与图1B)为短。
然后,请参考图2C,在完成封装胶体251的制作之后,在封装胶体251中形成接触开口252,此接触开口252暴露出导电柱220’的顶面220a。接着,在接触开口252中填入接触导体260,此处,接触导体260与导电柱220’电性连接。本实施例可通过蚀刻、研磨钻孔、激光钻孔或其他制程于封装胶体251中形成接触开口252。此外,接触导体260的材料例如是锡膏、银浆、或其他融点低于导电柱220’材料的导电物质。
在本实施例中,如图2B与图2C所示,由于导电柱220’可预先制作并设置于线路载板210上,因此本实施例在形成封装胶体251中的接触开口252时,将可有效减少封装胶体251中接触开孔252的深宽比(aspect ratio),使得制程时间缩短,进而增加产能。
请参考图2D,在填入接触导体260后,接着于封装胶体251上形成导电层270,以使导电层270通过接触导体260、导电柱220以及线路载板210而与芯片230电性连接。
在本实施例中,如图2C与图2D所示,前述的接触导体260于填入开口后,接触导体260会有顶面260a,其中顶面260a不会被封装胶体251所包覆,进而使得后续形成的导电层270能够顺利地与接触导体260的顶面260a电性连接。
经过上述制程后即可大致上完成本实施例的芯片封装体200’的制作。上述的芯片封装体200’包括线路载板210、导电柱220、芯片230、焊线240、封装胶体251、接触导体260、导电层270及外部端子216。线路载板210具有第一表面210a以及第二表面210b,且导电柱220、芯片230、焊线240、封装胶体251、接触导体260及导电层270位于线路载板210的第一表面210a上,外部端子216位于线路载板210的第二表面210b上。在一实施例中,线路载板210包括核心层212、导体C、第一接垫212a、第二接垫212b、第一防焊层214a以及第二防焊层214b,第一接垫212a与第二接垫212b分别位于核心层212的二相对表面S1、S2上,且第一接垫212a分别与通过嵌于核心层212中的导体C与对应的第二接垫212b电性连接。芯片230通过至少一焊线240与被防焊层214a所暴露出的第一接垫212a电性连接。外部端子216与被防焊层214b所暴露出的第二接垫212b电性连接。因此,芯片230通过至少一焊线240、第一接垫212a、导体C、第二接垫212b以及外部端子216与外部元件电性连接。封装胶体251配置于线路载板210上,除了包覆芯片230、接触导体260及导电柱220,可进一步包覆焊线240以及被防焊层214a所暴露的第一接垫212a,并使接触导体260暴露出接触导体260的顶面260a。导电层270配置在封装胶体251上,使导电层270接触接触导体260,且通过导电柱220、线路载板210与芯片230电性连接。
综上所述,本发明上述实施例在形成封装胶体之前先于线路载板上形成导电柱,此制程顺序可以提升芯片封装制程的封装良率。此外,由于导电柱的制作早于封装胶体的形成,因此封装胶体的厚度不会影响到导电柱的制作良率。
最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。
Claims (11)
1.一种芯片封装制程,包括:
提供线路载板,所述线路载板上具有导电柱;
将芯片置于线路载板,并使所述芯片通过至少一焊线与所述线路载板电性连接;
在所述线路载板上形成封装胶体以包覆所述芯片及所述导电柱;
移除部分的所述封装胶体以暴露出所述导电柱的顶面;以及
在所述封装胶体上形成与所述导电柱的所述顶面连接的导电层,其中所述导电层通过所述线路载板与所述芯片电性连接;
在所述线路载板上形成多个外部端子,其中所述多个外部端子与所述芯片位于所述线路载板的不同侧,且所述多个外部端子通过所述线路载板与所述芯片电性连接。
2.根据权利要求1所述的芯片封装制程,其中移除部分的所述封装胶体的方法包括研磨。
3.根据权利要求1所述的芯片封装制程,其中形成所述导电层的方法包括电镀。
4.一种芯片封装体,包括:
线路载板,所述线路载板具有导电柱;
芯片,配置在所述线路载板上,并且通过至少一焊线与所述线路载板电性连接;
封装胶体,配置在所述线路载板上,其中所述封装胶体包覆所述芯片及所述导电柱,且所述导电柱的顶面暴露于封装胶体外;
导电层,配置在所述封装胶体上以与所述导电柱的所述顶面连接,其中所述导电层通过所述线路载板与所述芯片电性连接;以及
多个外部端子,其中所述多个外部端子与所述芯片位于所述线路载板的不同侧,且所述多个外部端子通过所述线路载板与所述芯片电性连接。
5.根据权利要求4所述的芯片封装体,其中所述导电柱与所述芯片位于所述线路载板的同侧,且所述导电柱的高度大于所述芯片的厚度。
6.一种芯片封装制程,包括:
提供线路载板,所述线路载板上具有导电柱;
将芯片置于线路载板,并使所述芯片通过至少一焊线与所述线路载板电性连接;
在所述线路载板上形成封装胶体以包覆所述芯片及所述导电柱;
移除部分的所述封装胶体以于所述封装胶体内形成开口,其中所述开口暴露出所述导电柱的顶面;
在所述开口中填入接触导体;以及
在所述封装胶体上形成与所述接触导体的顶面连接的导电层,其中所述导电层通过所述接触导体及所述线路载板与所述芯片电性连接。
7.根据权利要求6所述的芯片封装制程,其中移除部分的所述封装胶体以在所述封装胶体内形成所述开口的方法包括激光钻孔。
8.根据权利要求6所述的芯片封装制程,其中形成所述导电层的方法包括电镀。
9.根据权利要求6所述的芯片封装制程,还包括在所述线路载板上形成多个外部端子,其中所述多个外部端子与所述芯片位于所述线路载板的不同侧,且所述多个外部端子通过所述线路载板与所述芯片电性连接。
10.一种芯片封装体,包括:
线路载板,所述线路载板具有导电柱;
接触导体,配置在所述导电柱上;
芯片,配置在所述线路载板上,并且与所述线路载板电性连接;
封装胶体,配置在所述线路载板上,其中所述封装胶体包覆所述芯片、所述导电柱及所述接触导体,且所述接触导体的顶面暴露在封装胶体外;
导电层,配置在所述封装胶体上以与所述接触导体的所述顶面连接,其中所述导电层通过所述接触导体及所述线路载板与所述芯片电性连接;以及
多个外部端子,其中所述多个外部端子与所述芯片位于所述线路载板的不同侧,且所述多个外部端子通过所述线路载板与所述芯片电性连接。
11.根据权利要求10所述的芯片封装体,其中所述导电柱、所述接触导体与所述芯片位于所述线路载板的同侧。
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TWI763056B (zh) * | 2020-06-10 | 2022-05-01 | 大陸商訊芯電子科技(中山)有限公司 | 半導體封裝裝置和半導體封裝裝置製造方法 |
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