CN107785373A - Semiconductor devices and preparation method thereof, electronic installation - Google Patents
Semiconductor devices and preparation method thereof, electronic installation Download PDFInfo
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- CN107785373A CN107785373A CN201610720027.7A CN201610720027A CN107785373A CN 107785373 A CN107785373 A CN 107785373A CN 201610720027 A CN201610720027 A CN 201610720027A CN 107785373 A CN107785373 A CN 107785373A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 104
- 238000002360 preparation method Methods 0.000 title claims abstract description 32
- 238000009434 installation Methods 0.000 title claims abstract description 12
- 238000002955 isolation Methods 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 238000005530 etching Methods 0.000 claims abstract description 48
- 239000006227 byproduct Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims description 38
- 230000008569 process Effects 0.000 claims description 23
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 14
- 239000007789 gas Substances 0.000 claims description 12
- 238000005516 engineering process Methods 0.000 claims description 9
- 229910052786 argon Inorganic materials 0.000 claims description 7
- 239000011469 building brick Substances 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 3
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- 230000009467 reduction Effects 0.000 abstract description 2
- 239000012212 insulator Substances 0.000 description 12
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 235000019994 cava Nutrition 0.000 description 7
- 238000000151 deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000007667 floating Methods 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 6
- 238000003860 storage Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 229910000673 Indium arsenide Inorganic materials 0.000 description 3
- 229910003811 SiGeC Inorganic materials 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000011068 loading method Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
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- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
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- 238000004458 analytical method Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- Semiconductor Memories (AREA)
- Element Separation (AREA)
Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, electronic installation, and the preparation method includes：For forming isolation structure in the semiconductor substrate, it comprises the steps：Semiconductor substrate is provided, forms the hard mask layer of the isolation structure on the semiconductor substrate；It is Semiconductor substrate described in mask etching to form the groove for forming isolation structure using the hard mask layer of the isolation structure, and the groove reaches target depth by setting the etch step of number, wherein, include operations described below in each etch step：Using the hard mask layer of the isolation structure as Semiconductor substrate set depth described in mask etching；The operation of by-product obturator is performed after the etching is completed.The preparation method can reduction partial-depth difference and line cave in problem.The semiconductor devices and the electronic installation partial-depth difference reduced because above-mentioned preparation method has and line cave in problem.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technology
With the development of manufacture of semiconductor technology, the faster flash of access speed has been developed in terms of storage device
Device (flash memory).Flash memory acts with can repeatedly enter deposit, reading and erasing of row information etc., and be stored in
The characteristic that information will not also disappear after a loss of power, therefore, flash memory has turned into PC and electronic equipment is adopted extensively
A kind of nonvolatile memory.And NAND (NAND gate) fast storages are due to large storage capacity and relatively high property
Can, it is widely used in the field that read/write requires higher.Recently, the capacity of NAND quick-flash memory chip has reached 2GB, and
Size increases sharply.The solid state hard disc of NAND quick-flash memory chip has been developed based on, and has been used as in pocket computer
Storage device.Therefore, in recent years, NAND quick-flash memory is widely used as the storage device in embedded system, also serves as individual
Storage device in computer system.
With the continuous diminution of the critical size of NAND quick-flash memory memory cell, STI (shallow trench isolation) structure
Depth-to-width ratio (aspect ratio) increases sharply.In the STI etching technics of high-aspect-ratio, easily there is serious micro-loading effect
(micro-loading) and line is answered to cave in (line collapse), as shown in FIG. 1A and 1B, which respectively show advanced wide
The line occurred in the STI etching technics of ratio caves in phenomenon and local depth difference (that is, micro loading effect).
It is, therefore, desirable to provide a kind of preparation method of new semiconductor devices, to solve the above problems at least in part.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In view of the shortcomings of the prior art, the present invention proposes a kind of preparation method of new semiconductor devices, can overcome
NAND quick-flash memory STI make in partial-depth difference and line cave in problem.
In order to overcome the problem of presently, there are, one aspect of the present invention provides a kind of preparation method of semiconductor devices, is used for
Isolation structure is formed in the semiconductor substrate, and it comprises the steps：Semiconductor substrate is provided, on the semiconductor substrate shape
Into the hard mask layer of the isolation structure；It is Semiconductor substrate described in mask etching with shape using the hard mask layer of the isolation structure
Into the groove for forming isolation structure, and the groove reaches target depth by setting the etch step of number, wherein,
Each etch step includes operations described below：Served as a contrast by semiconductor described in mask etching of the hard mask layer of the isolation structure
Bottom set depth；The operation of by-product obturator is performed after the etching is completed.
Exemplarily, the by-product obturator operation includes CFxOr N2Plasma-treating technology.
Exemplarily, the by-product obturator operation also includes argon plasma handling process.
Exemplarily, the reaction chamber bottom temp of the plasma-treating technology is set as 10~80 degree.
Exemplarily, the N2The substrate bias power of plasma-treating technology is 50~1000W, gas flow rate is 200~
400sccm, pressure are 50~200mT.
Exemplarily, the substrate bias power of the argon plasma handling process is 50~1200W, gas flow rate is 50~
1000sccm, pressure are 20~200mT.
Exemplarily, it is 5~20 etch steps that the etching of the groove, which includes,.
Exemplarily, the etching technics of the isolation structure and by-product obturator operation are completed in the same chamber.
Exemplarily, the isolation structure is fleet plough groove isolation structure.
Exemplarily, the set depth determines according to the target depth and etching number of the groove.
Exemplarily, gate stack, the grid are also formed between the Semiconductor substrate and the hard mask layer
Lamination includes tunnel oxide and floated to delete；Also include etching the grid before etching the Semiconductor substrate and forming the groove
The step of pole lamination.
The preparation method of semiconductor devices proposed by the present invention, by the way that the etching of isolation structure is divided into multiple processes,
The partial depth of isolation structure is etched during each, and that enters during each by-product obturator goes division operation, this
Sample can reduce or even avoid influence of the mask top barrier thing to etching process, be caved in so as to reduce partial-depth difference and line
Problem.
Another aspect of the invention provides a kind of semiconductor devices made using the above method, and the semiconductor devices includes：
Semiconductor substrate, formed with isolation structure in the Semiconductor substrate.
Problem that semiconductor devices proposed by the present invention has reduced partial-depth difference and line caves in.
Further aspect of the present invention provides a kind of electronic installation, it include semiconductor devices as described above and with it is described partly
The electronic building brick that conductor device is connected.
Electronic installation proposed by the present invention, due to above-mentioned semiconductor device, thus with it is similar the advantages of.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A shows that the line in NAND quick-flash memory STI etchings caves in problem；
Figure 1B shows the partial-depth difference problem in NAND quick-flash memory STI etchings；
Fig. 2 shows the step flow chart of the preparation method of semiconductor devices according to an embodiment of the present invention；
Fig. 3 A~Fig. 3 F show that the preparation method of semiconductor devices according to an embodiment of the present invention is implemented respectively successively
Step obtains the diagrammatic cross-section of semiconductor devices；
Fig. 4 shows the sectional view of semiconductor devices according to an embodiment of the present invention；
Fig. 5 shows the schematic diagram of electronic installation according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated phase from beginning to end
Identical element is represented with reference.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be element or layer between two parties.On the contrary, when element be referred to as " on directly existing ... ", " with ... direct neighbor ", " be directly connected to
To " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although art can be used
Language first, second, third, etc. describe various elements, part, area, floor and/or part, these elements, part, area, floor and/or portion
Dividing to be limited by these terms.These terms are used merely to distinguish an element, part, area, floor or part and another
Element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, part, area,
Floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with it is other
The relation of element or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of with
The different orientation of device in operation.For example, if the device upset in accompanying drawing, then, is described as " below other elements "
Or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
As it was previously stated, with the diminution of critical size, when making NAND type flash memory, in STI etching processes,
Easily there is partial-depth difference and line caves in problem, by analysis it is thought that because in etching process, easily in mask
By-product obturator (formation is accumulated or deposited to etch by-products at the top of mask), when critical dimension reduction, by-product are formed on top
The deposition of obturator can further increase depth-to-width ratio, and this caves in aggravation partial-depth difference and line problem.
The present invention be based on this, it is proposed that a kind of preparation method of semiconductor devices, for formed in the semiconductor substrate every
From structure, the preparation method comprises the steps：Served as a contrast by semiconductor described in mask etching of the hard mask layer of the isolation structure
Bottom is to form the groove for forming isolation structure, and the etch step by setting number forms the ditch with target depth
Groove, wherein, include operations described below in each etch step：Using the hard mask layer of the isolation structure as mask etching institute
State Semiconductor substrate set depth；The operation of by-product obturator is performed after the etching is completed.
The preparation method of semiconductor devices proposed by the present invention, by the way that the etching of isolation structure is divided into multiple processes,
The partial depth of isolation structure is etched during each, and carry out during each by-product obturator goes division operation,
Influence of the obturator to etching process at the top of mask so can be reduced or even avoided, is collapsed so as to reduce partial-depth difference and line
Collapse problem.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to explain this hair
The technical scheme of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention
There can also be other embodiment.
Embodiment one
The preparation method of the semiconductor devices of an embodiment of the present invention is done below with reference to Fig. 2 and Fig. 3 A~Fig. 3 D
It is described in detail.
First, step 201 is performed, there is provided Semiconductor substrate 300, formed in the Semiconductor substrate 300 patterned
Gate stack and active area hard mask layer 304, the gate stack include tunnel oxide 301 and floating boom 302, the knot formed
Structure is as shown in Figure 3A.
Wherein, Semiconductor substrate 300 can be at least one of following material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, in addition to sandwich construction of these semiconductors composition etc.
Or silicon (SSOI) is laminated for silicon-on-insulator (SOI), on insulator, is laminated SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.As an example, in the present embodiment, Semiconductor substrate 300
Constituent material select monocrystalline silicon.
Gate stack includes tunnel oxide 301 and floating boom 302, and it uses structure and forming method system commonly used in the art
Make.Such as tunnel oxide 301 is illustratively silicon oxide layer, it can be by the way that such as (physical vapor be sunk for thermal oxidation method, PVD
Product), CVD (chemical vapor deposition), ALD (ald) the methods of formed.Floating boom 301 exemplarily uses such as polysilicon
Deng semi-conducting material, and by selecting molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), low pressure chemical gas
A kind of mutually formation in deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG).
Active area mask layer 304 is made using material commonly used in the art and method, such as active area mask layer 304 can be with
Using hard mask material layers such as oxide, nitride or nitrogen oxides.And pass through PVD (physical vapour deposition (PVD)), CVD (chemistry
Vapour deposition), ALD (ald) the methods of formed.Exemplarily, in the present embodiment, active area mask layer 304 uses
Oxide, such as silica.
Further, in the present embodiment, etching stopping layer 303 is also formed with gate stack, it can be oxidation
Thing, nitride or nitrogen oxides etc..Exemplarily, in the present embodiment, etching stopping layer 303 uses silicon nitride, after it is used as
Stop-layer during continuous isolation structure CMP (chemical-mechanical planarization).
Further, gate stack and the graphical of active area mask layer pass through lithographic etch process shape commonly used in the art
Into the shape of gate stack is corresponding with memory cell, the shape and the shape pair of active area and isolation structure of active area mask layer
Should, i.e. active area mask layer masking Semiconductor substrate is used for the region for forming active area, and exposing semiconductor substrate is used to be formed
The region of isolation structure.
Then, step 202 is performed：It is mask with the active area hard mask layer 304, etches the Semiconductor substrate 300
Set depth, to form the groove 305 with the first depth h1, shown in the structure chart 3B formed.
As it was previously stated, the etching of the groove for forming isolation structure of the present embodiment is divided into multiple processes or multiple steps
Suddenly, the groove of set depth is etched during each, the groove of target depth or isolation structure are formed by multiple etching.
Exemplarily, such as the target depth of isolation structure or the groove for forming isolation structure isIsolation junction
The etching of structure is exemplarily divided into 5 processes, is etched during eachDepth, i.e., in each process
In increase gash depthUntill reaching target depth.
It is understood that the etching of isolation structure or groove can be carried out uniformly, non-homogeneous can also carry out.That is, exist
Each etch step or during set depth can be with identical, can also be different.
In this step, it is mask with the active area hard mask layer 304, passes through suitable wet method or dry etch process
Etch semiconductor substrates 300 are with the first depth h1 of formation groove 305.Exemplarily, in this example, using halogen gas
Plasma, such as chlorine (Cl2) plasma etching etch semiconductor substrates 300 are with ditch of the formation with the first depth h1
Groove.
Further, as it was previously stated, in etching process, because original is accumulated or deposited etc. to etch by-products at the top of mask
Because obturator can be formed at the top of mask, as 306 are schematically shown in Fig. 3 B.
Then, step 203 is performed, performs the operation of by-product obturator, the structure formed is as shown in Figure 3 C.
For depth-to-width ratio increase caused by reducing obturator 306 and thus caused partial-depth difference and line cave in and asked
Topic, the operation of by-product obturator is performed in step.Because obturator is mostly organic matter or polymer, therefore can be by such as
CFx (for example, mixed gas of the gas such as CF4, CF3 or these gases) or N2 (nitrogen) etc. corona treatment removes.
Exemplarily, it is preferable that in order to avoid other side effects, when carrying out the operation of by-product obturator, the plasma
The reaction chamber bottom temp of body handling process is set as 10~80 degree, preferably about 20 degree.
Exemplarily, when using N2During plasma-treating technology, its technological parameter is illustratively：Substrate bias power is 50
~1000W, gas flow rate are 200~400sccm, and pressure is 50~200mT (person of outstanding talent's support).
Remove obturator by performing and operate, thus can reduce or overcome caused by by-product obturator depth-to-width ratio increase with
And thus caused partial-depth difference and line cave in problem.
Further, in the present embodiment, by-product obturator operation also includes argon (Ar) plasma-treating technology, passes through
Argon (Ar) plasma-treating technology can change the polarity of crystal column surface, it is changed into hydrophily by hydrophobicity, so as to increase
Big wet clean process window.Exemplarily, when using argon plasma handling process, its technological parameter is exemplarily
For：Substrate bias power is 50~1200W, and gas flow rate is 50~1000sccm, and pressure is 20~200mT.
Further, after step, wet-cleaning operation can also be carried out, that is, passes through suitable solvent or liquid rinse
Semiconductor substrate, further to remove etch by-products etc., and clean wafer.
Then, step 204, repeat step 202 and step 203 are performed until the depth of the groove reaches target depth.
As it was previously stated, if the etching of groove is divided into dry etching step, such as can be divided into 5~20 etch steps, every
One etch step is performed both by step 203 operation similar with step 203, until gash depth reaches target depth.
Exemplarily, such as after execution of step 202 and 203, groove 305 of the formation with the first depth h1, after
The continuous operation for performing similar step 202 and 203, to form the groove 307 with the second depth h2, the second depth h2 is equal to first
The set depth of the depth h1+ steps.
Similarly, obturator can be also formed in the etching process of groove 307, therefore also performs similar by-product obturator
Operation, to reduce or overcome, depth-to-width ratio caused by obturator increases and thus caused partial-depth difference and line cave in and asked
Topic.
After multiple this etching operation, the depth of groove reaches target depth, and etching groove terminates, that is, forms
Terminate trench etch process after groove 308 with depth h.
So far, the processing step that method according to embodiments of the present invention is implemented is completed, it is to be understood that the present embodiment
Manufacturing method of semiconductor device not only includes above-mentioned steps, before above-mentioned steps, among or may also include other needs afterwards
The step of, after the groove with target depth is formed, include the step such as filling and planarization of groove.
The preparation method for the semiconductor devices that the present embodiment proposes, by the way that the etching of isolation structure is divided into multiple processes,
The partial depth of isolation structure is etched during each, and carry out during each obturator goes division operation, this
Sample can reduce or even avoid influence of the mask top barrier thing to etching process, be caved in so as to reduce partial-depth difference and line
Problem.
Although it is understood that in the present embodiment, illustrated by taking the sti structure for making NAND device as an example,
The preparation method for being the semiconductor devices of the present embodiment can also be applied in the etching of other big aspect ratio trench.
Embodiment two
The present invention also provides a kind of semiconductor devices made using the above method, as shown in figure 4, the semiconductor devices bag
Include：Semiconductor substrate 400, formed in the Semiconductor substrate 400 patterned gate stack and active area hard mask layer 404 with
And separating the isolation structure 405 of the gate stack, the gate stack includes tunnel oxide 401 and floating boom 402.
Wherein, Semiconductor substrate 400 can be at least one of following material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, in addition to sandwich construction of these semiconductors composition etc.
Or silicon (SSOI) is laminated for silicon-on-insulator (SOI), on insulator, is laminated SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.As an example, in the present embodiment, Semiconductor substrate 400
Constituent material select monocrystalline silicon.
Gate stack includes tunnel oxide 401 and floating boom 402, and it uses structure and forming method system commonly used in the art
Make.Such as tunnel oxide 401 is illustratively silicon oxide layer, it can be by the way that such as (physical vapor be sunk for thermal oxidation method, PVD
Product), CVD (chemical vapor deposition), ALD (ald) the methods of formed.Floating boom 401 exemplarily uses such as polysilicon
Deng semi-conducting material, and by selecting molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), low pressure chemical gas
A kind of mutually formation in deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG).
Active area mask layer 404 is made using material commonly used in the art and method, such as active area mask layer 404 can be with
Using hard mask material layers such as oxide, nitride or nitrogen oxides.And pass through PVD (physical vapour deposition (PVD)), CVD (chemistry
Vapour deposition), ALD (ald) the methods of formed.Exemplarily, in the present embodiment, active area mask layer 304 uses
Oxide, such as silica.
Further, in the present embodiment, etching stopping layer 303 is also formed with gate stack, it can be oxidation
Thing, nitride or nitrogen oxides etc..Exemplarily, in the present embodiment, etching stopping layer 403 uses silicon nitride, after it is used as
Stop-layer during continuous isolation structure CMP (chemical-mechanical planarization).
Further, gate stack and the graphical of active area mask layer pass through lithographic etch process shape commonly used in the art
Into the shape of gate stack is corresponding with memory cell, the shape and the shape pair of active area and isolation structure of active area mask layer
Should, i.e. active area mask layer masking Semiconductor substrate is used for the region for forming active area, and exposing semiconductor substrate is used to be formed
The region of isolation structure.
Isolation structure 405 can be various suitable isolation structures, such as fleet plough groove isolation structure (STI), and it can lead to
Above-mentioned preparation method provided by the invention is crossed to be formed.Exemplarily, the isolated material filled in isolation structure 405 is oxide.
Problem that the semiconductor devices of the present embodiment has reduced partial-depth difference and line caves in.
Embodiment three
Yet another embodiment of the present invention provides a kind of electronic installation, including semiconductor devices and with the semiconductor device
The connected electronic building brick of part.Wherein, the semiconductor devices includes：Semiconductor substrate, formed with grid in the Semiconductor substrate
Lamination and the isolation structure for separating the gate stack.
Wherein Semiconductor substrate can be at least one of following material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, in addition to sandwich construction of these semiconductors composition etc.
Or silicon (SSOI) is laminated for silicon-on-insulator (SOI), on insulator, is laminated SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.Device, such as NMOS are could be formed with Semiconductor substrate
And/or PMOS etc..Equally, in Semiconductor substrate can also formed with conductive member, conductive member can be transistor grid,
Source electrode or drain electrode or the metal interconnection structure that is electrically connected with transistor, etc..In addition, may be used also in the semiconductor substrate
So that formed with isolation structure, the isolation structure is that shallow trench isolates (STI) structure or selective oxidation silicon (LOCOS) isolation junction
Structure.As an example, in the present embodiment, the constituent material of Semiconductor substrate selects monocrystalline silicon.
Wherein, the electronic building brick, can be any electronic building bricks such as discrete device, integrated circuit.
The electronic installation of the present embodiment, can be mobile phone, tablet personal computer, notebook computer, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, or
Any intermediate products including the semiconductor devices.
Wherein, Fig. 5 shows the example of mobile phone.The outside of mobile phone 500 is provided with the display portion being included in shell 501
502nd, operation button 503, external connection port 504, loudspeaker 505, microphone 506 etc..
The electronic installation of the embodiment of the present invention, by the semiconductor devices included have reduced partial-depth difference and
Line caves in problem, thus has more preferable yield and performance.Therefore the electronic installation equally has the advantages of similar.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (13)
- A kind of 1. preparation method of semiconductor devices, for forming isolation structure in the semiconductor substrate, it is characterised in that including Following step：Semiconductor substrate is provided, forms the hard mask layer of the isolation structure on the semiconductor substrate；Using the hard mask layer of the isolation structure as Semiconductor substrate described in mask etching to be formed for forming isolation structure Groove, and the groove reaches target depth by setting the etch step of number,Wherein, operations described below is included in each etch step：Using the hard mask layer of the isolation structure as Semiconductor substrate set depth described in mask etching；The operation of by-product obturator is performed after the etching is completed.
- 2. the preparation method of semiconductor devices according to claim 1, it is characterised in that the by-product obturator operation bag Include CFxOr N2Plasma-treating technology.
- 3. the preparation method of semiconductor devices according to claim 2, it is characterised in that the by-product obturator operation is also Including argon plasma handling process.
- 4. the preparation method of the semiconductor devices according to Claims 2 or 3, it is characterised in that the corona treatment The reaction chamber bottom temp of technique is set as 10~80 degree.
- 5. the preparation method of semiconductor devices according to claim 2, it is characterised in that the N2Corona treatment work The substrate bias power of skill is 50~1000W, and gas flow rate is 200~400sccm, and pressure is 50~200mT.
- 6. the preparation method of semiconductor devices according to claim 3, it is characterised in that the argon plasma handles work The substrate bias power of skill is 50~1200W, and gas flow rate is 50~1000sccm, and pressure is 20~200mT.
- 7. the preparation method of semiconductor devices according to claim 1, it is characterised in that the etching of the groove is including being 5~20 etch steps.
- 8. the preparation method of semiconductor devices according to claim 1, it is characterised in that the etching work of the isolation structure Skill and by-product obturator operation are completed in the same chamber.
- 9. the preparation method of semiconductor devices according to claim 1, it is characterised in that the isolation structure is shallow trench Isolation structure.
- 10. the preparation method of semiconductor devices according to claim 1, it is characterised in that the set depth is according to institute The target depth and etching number for stating groove determine.
- 11. the preparation method of semiconductor devices according to claim 1, it is characterised in that in the Semiconductor substrate and Gate stack is also formed between the hard mask layer, the gate stack includes tunnel oxide and floated to delete；The step of also including etching the gate stack before etching the Semiconductor substrate and forming the groove.
- 12. the semiconductor devices that a kind of preparation method using as described in any one in claim 1-11 makes, it is special Sign is, including：Semiconductor substrate, formed with isolation structure in the Semiconductor substrate.
- 13. a kind of electronic installation, it is characterised in that partly led including semiconductor devices as claimed in claim 12 and with described The electronic building brick that body device is connected.
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| CN109273408A (en) * | 2017-07-18 | 2019-01-25 | 格芯公司 | For patterning the technology of the active area of transistor unit in post manufacturing phase |
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| WO2016074581A1 (en) * | 2014-11-13 | 2016-05-19 | 北京北方微电子基地设备工艺研究中心有限责任公司 | High aspect ratio shallow trench isolation etching method |
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