CN107210299B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN107210299B
CN107210299B CN201680005866.9A CN201680005866A CN107210299B CN 107210299 B CN107210299 B CN 107210299B CN 201680005866 A CN201680005866 A CN 201680005866A CN 107210299 B CN107210299 B CN 107210299B
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fwd
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CN107210299A (zh
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住友正清
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Denso Corp
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Denso Corp
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Abstract

半导体装置具备：半导体基板(10)，具有漂移层(11)；所述漂移层上的基极层(12)；集电极层(23)及阴极层(24)，形成在所述漂移层的与所述基极层侧相反的一侧；多个沟槽(13)，贯通所述基极层到达所述漂移层，沿着一个方向形成；栅电极(19)，在所述沟槽内经由栅极绝缘膜(18)形成；以及发射极区域(14)，形成在所述基极层的表层部，与所述沟槽相接。所述半导体基板具有IGBT区域(1a)和FWD区域(1b)，所述IGBT区域(1a)具有所述发射极区域，所述FWD区域(1b)在所述基极层的表层部沿着所述一个方向交替地形成有注入抑制区域(16)和接触区域(17)。

Description

半导体装置
本申请以2015年1月16日提交的日本专利申请号2015-7006号及2015年12月24日提交的日本专利申请号2015-252136号为基础，在此援引其记载内容。
技术领域
本发明涉及半导体装置，该半导体装置中，具有绝缘栅极构造的绝缘栅双极晶体管元件(以下称作IGBT元件)和续流二极管元件(以下称作FWD元件)形成在同一半导体基板上。
背景技术
以往，作为例如逆变器等使用的开关元件，提出了具有形成IGBT元件的IGBT区域和形成FWD元件的FWD区域的半导体装置(例如参照专利文献1)。
具体地说，在该半导体装置中，在构成N-型的漂移层的半导体基板的表层部形成基极层，以贯通基极层的方式形成多个沟槽。并且，在各沟槽中以覆盖壁面的方式形成栅极绝缘膜，并且在栅极绝缘膜上形成栅电极。
在半导体基板的背面侧形成有P型的集电极层及N型的阴极层。并且，在基极层的位于集电极层上的部分形成有N+型的发射极区域。此外，在半导体基板的正面侧形成有与基极层及发射极区域电连接的上部电极，在半导体基板的背面侧形成有与集电极层及阴极层电连接的下部电极。并且，在半导体基板的背面侧，形成集电极层的区域是IGBT区域，形成阴极层的区域是FWD区域。此外，通过采用上述构造，在半导体基板中的FWD区域通过N型的阴极层及漂移层和P型的基极层形成具有PN接合的FWD元件。
在这样的半导体装置中，IGBT元件的上部电极被施加比下部电极低的电压、且栅电极被施加接通电压时，在基极层的与沟槽相接的部分形成N型的反转层(即通道)。而且，从发射极区域经由反转层向漂移层供给电子，并且从集电极层向漂移层供给空穴，通过传导度调制而漂移层的电阻值下降，从而成为导通状态。另外，接通电压是指，使栅极-发射极间的电压Vge比绝缘栅极构造的阈值电压Vth更高的电压。
此外，FWD元件在上部电极被施加比下部电极高的电压、上部电极和下部电极之间的电压比正向电压高时成为导通状态，从基极层向漂移层注入空穴。
但是，在这样的半导体装置中，IGBT区域和FWD区域共用基极层，所以FWD区域的基极层(即阳极层)的杂质浓度变得过高。因此，FWD元件成为导通状态(即二极管工作)的情况下，空穴的注入量变得过高而逆回复电荷变得过高，存在恢复电流变大的问题。
现有技术文献
专利文献
专利文献1：特开2013-152996号公报
发明内容
本发明的目的在于，提供一种半导体装置，在具有IGBT区域及FWD区域的半导体装置中能够降低恢复电流。
在本发明的方式中，半导体装置具备：半导体基板，具有第1导电型的漂移层；第2导电型的基极层，形成于所述漂移层上；第2导电型的集电极层及第1导电型的阴极层，形成于所述漂移层的与所述基极层侧相反的一侧；多个沟槽，贯通所述基极层而到达所述漂移层，沿着所述半导体基板的面方向的一个方向形成；栅极绝缘膜，形成于所述沟槽的壁面；栅电极，形成于所述栅极绝缘膜上；第1导电型的发射极区域，形成于所述基极层的表层部，与所述沟槽相接。所述半导体基板中的作为IGBT元件工作的区域是IGBT区域。作为FWD元件工作的区域是FWD区域。所述发射极区域形成于所述IGBT区域。在所述FWD区域，在所述基极层的表层部，沿着所述一个方向交替地形成有比所述漂移层更高杂质浓度的第1导电型的注入抑制区域和比所述基极层更高杂质浓度的第2导电型的接触区域。
根据上述的半导体装置，即使IGBT区域和FWD区域的基极层是同一层，在FWD元件进行二极管动作时，也能够通过注入抑制区域抑制载流子的注入，所以能够减小恢复电流。此外，沿着沟槽的延设方向交替地形成注入抑制区域和接触区域，所以不需要高精度的对准，就能够减小恢复电流。
附图说明
本发明的上述目的及其他目的、特征和优点，提供参照附图进行的下面的详细说明而变得明确。
图1是本发明的第1实施方式中的半导体装置的截面图。
图2是图1所示的半导体装置的立体截面图。
图是表示FWD元件的正向电压和正向电流的关系的模拟结果。
图4是表示时间和FWD元件的正向电流的关系的模拟结果。
图5是表示FWD元件的正向电压和正向电流的关系的模拟结果。
图6是本发明的第2实施方式中的半导体装置的立体截面图。
图7是本发明的第3实施方式中的半导体装置的平面图。
图8是沿着图7中的VIII-VIII线的截面图。
图9是沿着图7中的IX-IX线的截面图。
图10是本发明的第4实施方式中的半导体装置的截面图。
图11是本发明的第5实施方式中的半导体装置的截面图。
图12是本发明的第5实施方式的变形例中的半导体装置的截面图。
具体实施方式
以下基于附图说明本发明的实施方式。另外，在以下的各实施方式中，对于彼此相同或均等的部分，附加同一符号而进行说明。
(第1实施方式)
说明本发明的第1实施方式。另外，本实施方式的半导体装置适合作为例如逆变器、DC/DC变换器等的电源电路所使用的电源开关元件而利用。
如图1及图2所示，半导体装置具有形成IGBT元件的IGBT区域1a和形成FWD元件的FWD区域1b。另外，在图1中，仅示出了一个IGBT区域1a及FWD区域1b，但是IGBT区域1a及FWD区域1b也可以交替地形成。
这些IGBT区域1a及FWD区域1b形成在具有漂移层11的N-型的同一半导体基板10上。并且，在漂移层11上(即半导体基板10的一面10a侧)形成有P型的基极层12。另外，基极层12例如通过从半导体基板10的一面10a侧离子注入P型的杂质后进行热处理而形成，在IGBT区域1a及FWD区域1b是相同的杂质浓度。
并且，以贯通基极层1并到达漂移层11的方式形成有多个沟槽13，通过该沟槽13将基极层12分离为多个。多个沟槽13分别形成在IGBT区域1a及FWD区域1b，沿着半导体基板10的一面10a的面方向之中的一个方向(即图1中的纸面垂直方向)而等间隔地形成。
在IGBT区域1a，在基极层12的表层部形成有比漂移层11更高杂质浓度的N+型的发射极区域14和比基极层12更高杂质浓度的P+型的接触区域15。在FWD区域1b，在基极层12的表层部形成有比漂移层11更高杂质浓度的N+型的注入抑制区域16和比基极层12更高杂质浓度的P+型的接触区域17。
并且，形成于IGBT区域1a的发射极区域14及接触区域15、形成于FWD区域1b的注入抑制区域16及接触区域17分别沿着沟槽13的延设方向而交替地形成。另外，形成于IGBT区域1a的发射极区域14和形成于FWD区域1b的注入抑制区域16是相同的杂质浓度。形成于IGBT区域1a及FWD区域1b的接触区域15、17是相同的杂质浓度。
这样的发射极区域14及注入抑制区域16如下那样形成：在例如半导体基板10的一面10a上配置了在规定部位开口的掩膜，从半导体基板10的一面10a侧向发射极区域形成预定区域及注入抑制区域形成预定区域离子注入相同的N型的杂质，然后进行热处理而同时形成。同样，接触区域15、17如下那样形成：在例如半导体基板10的面10a上配置了在规定部位开口的掩膜，从半导体基板10的一面10a侧向各接触区域形成预定区域离子注入相同的P型的杂质，然后进行热处理而同时形成。
因此，通过适当变更掩膜的形状，在IGBT区域1a中，发射极区域14的沿着沟槽13的延设方向的方向的长度(以下简称为发射极区域14的长度)Wn1和接触区域15的沿着沟槽13的延设方向的方向的长度(以下简称为接触区域15的长度)Wp1的比能够适当变更。同样，在FWD区域1b中，注入抑制区域16的沿着沟槽13的延设方向的方向的长度(以下简称为注入抑制区域16的长度)Wn2和接触区域17的沿着沟槽13的延设方向的方向的长度(以下简称为接触区域17的长度)Wp2的比能够适当变更。
在本实施方式中，发射极区域14的长度Wn1与接触区域15的长度Wp1之比、和注入抑制区域16的长度Wn2与接触区域17的长度Wp2之比不同。具体地说，发射极区域14的长度Wn1比接触区域15的长度Wp1更长，注入抑制区域16的长度Wn2与接触区域17的长度Wp2相等。
沟槽13被栅极绝缘膜18和栅电极19填埋，该栅极绝缘膜18以覆盖各沟槽13的壁面的方式形成，该栅电极19形成在该栅极绝缘膜18之上，由多晶硅等构成。由此，构成沟槽栅极构造。
在半导体基板10的一面10a上形成由BPSG等构成的层间绝缘膜20。并且，在层间绝缘膜20上，形成有经由形成于层间绝缘膜20的接触空穴20a而与发射极区域14、各接触区域15、17、注入抑制区域16电连接的上部电极21。即，在层间绝缘膜20上形成有上部电极21，该上部电极21在IGBT区域1a作为发射极电极起作用，在FWD区域1b作为阳电极起作用。另外，在图2中，为了便于理解发射极区域14、接触区域15、注入抑制区域16、接触区域17的关系，省略了层间绝缘膜20及上部电极21。
在漂移层11的与基极层12侧相反侧(即半导体基板10的另一面10b侧)形成有N型的场阑层(以下简称为FS层)22。该FS层22并不是必须的，但是为了控制从半导体基板10的另一面10b侧注入的空穴的注入量而设置，以防止空穴层扩散而提高耐压和正常损失的性能。
然后，在IGBT区域1a，隔着FS层22在漂移层11的相反侧形成有P型的集电极层23，在FWD区域1b，隔着FS层22在漂移层11的相反侧形成有N型的阴极层24。即，IGBT区域1a和FWD区域1b根据在半导体基板10的另一面10b侧形成的层是集电极层23还是阴极层24而被划分。即，在本实施方式中，集电极层23上的部分是IGBT区域1a，阴极层24上的部分是FWD区域1b。
此外，在集电极层23及阴极层24上(即半导体基板10的另一面10b)形成有下部电极25。换言之，形成有下部电极25，该下部电极25在IGBT区域1a作为集电极起作用，在FWD区域1b作为阴电极起作用。
并且，通过如上述那样构成，在FWD区域1b，将基极层12及接触区域17作为阳极，将漂移层11、FS层22、阴极层24作为阴极，从而构成PN接合的FWD元件。
以上是本实施方式的半导体装置的基本构成。另外，在本实施方式中，N+型、N-型相当于本发明的第1导电型，P型、P+型相当于本发明的第2导电型。接下来说明上述半导体装置的动作。
首先，将上部电极21接地，并且对下部电极25施加正电压后，在基极层12和漂移层11之间形成的PN接合成为逆导通状态。因此，栅电极19被施加低电平(例如0V)的电压时，在PN接合形成空穴层，在上部电极21和下部电极25之间不流动电流。
然后，为了使IGBT元件成为导通状态，在将上部电极21接地、且向下部电极25施加正电压的状态下，向栅电极19施加绝缘栅极构造的阈值电压Vth以上的电压。由此，在与基极层12中的配置有栅电极19的沟槽13相接的部分形成反转层，从发射极区域14经由反转层向漂移层11供给电子，并且从集电极层23向漂移层11供给空穴，通过传导度调制而漂移层11的电阻值下降，从而成为导通状态。
此外，使IGBT元件成为截止状态而使FWD元件进行二极管动作(即导通状态)时，对于向上部电极21和下部电极25施加的电压进行开关，向上部电极21施加正的电压，并且将下部电极25接地。然后，向栅电极19施加低电平(例如0V)的电压。由此，在基极层12的与沟槽13相接的部分不形成反转层，FWD元件进行二极管动作。
这时，在FWD区域1b，在基极层12的表层部形成注入抑制区域16。因此，基极层12与IGBT区域1a同样，作为FWD元件虽然杂质浓度变高，但是通过注入抑制区域16抑制了空穴的注入，基极层12的电阻成分也变高，FWD元件的正向电压也上升。具体地说，如图3所示，注入抑制区域16的长度Wn2越长，越抑制空穴的注入，正向电压变大。换言之，基极层12的表层部中的注入抑制区域16所占的比例越高，正向电压越大。
并且，从FWD元件进行二极管动作的状态起将电流切断时，向上部电极21施加负的电压，并且向下部电极25施加正的电压，即逆电压施加。由此，FWD元件成为恢复状态之后，电流切断。
这时，在恢复状态下产生逆回复电荷，但是通过注入抑制区域16而预先减少漂移层11内的过剩载流子。因此，能够使逆回复电荷成为充分小的值，能够减小恢复电流。具体地说，如图4所示，注入抑制区域16的长度Wn2越长，越能够减小恢复电流。换言之，基极层12的表层部中的注入抑制区域16所占的比例越高，越能够减小恢复电流。
即，如图5所示，注入抑制区域16的长度Wn2越长，FWD元件的正向电压越高，并且能够减小恢复电流。另外，如上述那样，注入抑制区域16的长度Wn2和接触区域17的长度Wp2之比能够适当变更，所以优选为根据用途而适当变更各长度Wn2、Wp2。
如以上说明，在本实施方式中，在FWD区域1b，在基极层12的表层部形成有注入抑制区域16。因此，即使IGBT区域1a和FWD区域1b共用基极层12，也通过注入抑制区域16抑制载流子的注入，所以能够减小恢复电流。
另外，近年来，希望将相邻的沟槽13之间的长度设为1μm程度而微细化。这种情况下，即使想要沿着相邻的沟槽13的排列方向(即图1及图2中纸面左右方向)形成注入抑制区域16和接触区域17，也需要高精度的对准。与此相对，在本实施方式中，沿着沟槽13的延设方向交替地形成注入抑制区域16和接触区域17，所以不需要高精度的对准，能够减小恢复电流。即，制造工序不会复杂化，能够减小恢复电流。
(第2实施方式)
说明本发明的第2实施方式。相对于第1实施方式，本实施方式形成体区域，其他与第1实施方式同样，因此省略说明。
在本实施方式中，如图6所示，在基极层12之中的发射极区域14、接触区域15、注入抑制区域16、接触区域17的下方形成有体区域26。具体地说，体区域26比基极层12的高杂质浓度更高，是沿着沟槽13的延设方向而延设的棒状。即，从半导体基板10的一面10a侧观察时，体区域26以与发射极区域14、接触区域15、注入抑制区域16、接触区域17交叉的方式形成。并且，体区域26与沟槽13分离地形成，并且与各接触区域15、17相连。
由此，使IGBT元件截止时，能够将漂移层11中蓄积的空穴容易地经由基极层12、体区域26、接触区域15、17从上部电极21排出。即，能够抑制空穴流向发射极区域14。因此，能够抑制闩锁，得到与上述第1实施方式同样的效果。
(第3实施方式)
说明本发明的第3实施方式。本实施方式与第1实施方式相比，具备外周区域，其他与上述第1实施方式同样，因此省略说明。
如图7所示，本实施方式的半导体装置具有单元区域1和包围单元区域1的外周区域2。单元区域1具有上述第1实施方式中说明的IGBT区域1a及FWD区域1b。另外，在上述第1实施方式中说明的图1是沿着图7中的I-I线的截面图，IGBT区域1a及FWD区域1b沿着与沟槽13的延设方向正交的方向交替地形成。
如图8及图9所示，外周区域2具有与单元区域1同样的漂移层11，在该漂移层11中的FWD区域1b侧的部分形成有基极层12以提高耐压。换言之，在外周区域2，在FWD区域1b侧的部分从该FWD区域1b侧延伸设置有基极层12。此外，沟槽13由于延设方向上的端部容易集中电场，所以如图8所示，以两端部位于外周区域2的方式，从FWD区域1b延伸设置到外周区域2。同样，多个沟槽13中，位于沟槽13的排列方向的两端部的沟槽13容易集中电场，所以如图9所示，在外周区域2也形成有沟槽13。即，多个沟槽13中，排列方向的两端部成为形成于外周区域2的沟槽13。
另外，图8也相当于沿着图1中的VIII-VIII线的截面图，表示相邻的沟槽13之间的部分的截面图。此外，沟槽13如图8及图9所示，在延伸设置到外周区域2的基极层12的平面方向的内侧(即FWD区域1b侧)结束。进而，虽然没有图示，在IGBT区域1a和外周区域2的边界，也与FWD区域1b和外周区域2的边界同样，在外周区域2延伸设置有基极层12及沟槽13。
此外，注入抑制区域16仅形成在单元区域1，在外周区域2不形成。因此，本实施方式中的单元区域1和外周区域2的边界也可以说是形成有注入抑制区域16的部分和未形成的部分的边界。
此外，在外周区域2，在漂移层11的表层部形成有P型的保护层27。该保护层27经由形成于层间绝缘膜20的接触空穴20a而分别电配置于与独立的外周电极28。此外，在外周区域2，在半导体基板10的另一面10b侧形成有与IGBT区域1a同样的P+型的集电极层23。
以上是本实施方式的半导体装置的构成。由此，在外周区域2，在半导体基板10的另一面10b侧形成有P+型的集电极层23，外周区域2中的基极层12与漂移层11及FWD区域1b中的阴极层24一起构成寄生二极管。因此，该寄生二极管与外周区域2中的半导体基板10的另一面10b侧为N型层(即阴极层24)、外周区域2中的基极层12与漂移层11及外周区域2的另一面10b侧的N型层一起构成寄生二极管的情况相比，内部电阻变高。因此，使FWD元件进行二极管动作时，通过外周区域2抑制了从基极层12注入空穴，所以从FWD元件进行二极管动作的状态起切断电流时，能够减小外周区域2中的恢复电流。
进而，在本实施方式中，在外周区域2不形成注入抑制区域16。因此，从FWD元件进行二极管动作的状态起切断电流时，能够抑制外周区域2的过剩载流子(即空穴)流入注入抑制区域16，能够抑制半导体装置的误动作。
(第4实施方式)
说明本发明的第4实施方式。本实施方式与第3实施方式相比，变更了半导体基板10的另一面10b侧的构成，其他与上述第3实施方式同样，因此省略说明。
在本实施方式中，如图10所示，FWD区域1b在半导体基板10的另一面10b侧，与外周区域2的边界的距离为L的部分(即外缘部)为集电极层23。具体地说，在本实施方式中，距离L是半导体基板10的一面10a与另一面10b之间的距离(以下称作半导体基板10的厚度)以上。
由此，FWD区域1b的与外周区域2的边界为距离L的部分是集电极层23，所以能够进一步增大外周区域2中的基极层12和FWD区域1b中的阴极层24构成的寄生二极管的内部电阻。因此，能够进一步抑制使FWD元件进行二极管动作时的空穴的注入，从FWD元件进行二极管动作的状态起将电流切断时，能够进一步减小外周区域2中的恢复电流。
此外，从经验可知，在半导体基板10的一面10a和另一面10b之间流动的电流具有约45°的扩散(即分布)。而在本实施方式中，FWD区域1b在半导体基板10的另一面10b侧，从与外周区域2的边界起半导体基板10的厚度以上是集电极层23。即，假想线K(参照图10)和半导体基板10的一面10a所成的角度θ为45°以上，该假想线K是将半导体基板10的一面10a中的FWD区域1b与外周区域2的边界、和FWD区域1b中的集电极层23与阴极层24的边界连结的线。因此，能够减少由外周区域2中的基极层12和FWD区域1b中的阴极层24构成的寄生二极管起作用。因此，能够进一步减小恢复电流。
(第5实施方式)
说明本发明的第5实施方式。本实施方式与第3实施方式相比，变更了注入抑制区域16的长度Wn2，其他与上述第3实施方式同样，因此省略说明。
在本实施方式中，如图11所示，在FWD区域1b，注入抑制区域16的长度Wn2和接触区域17的长度Wp2在每个部分不同。具体地说，在FWD区域1b和外周区域2的边界部分，与FWD区域1b的内缘部(例如FWD区域1b的中心部)相比，注入抑制区域16更致密地形成。详细地说，在FWD区域1b和外周区域2的边界部分，与FWD区域1b的内缘部相比，邻接的注入抑制区域16的沿着沟槽13的延设方向的间隔更短。更详细地说，在本实施方式中，在FWD区域1b和外周区域2的边界部分，与注入抑制区域16的长度Wn2相比，接触区域17的长度Wp2更短。另外，在本实施方式中，在FWD区域1b的内缘部，与上述第3实施方式同样，注入抑制区域16的长度Wn2和接触区域17的长度Wp2相等。
由此，在FWD区域1b的与外周区域2的边界部分，注入抑制区域16致密地形成，所以能够进一步抑制使FWD元件进行二极管动作时的空穴的注入。因此，从FWD元件进行二极管动作的状态起切断电流时，能够进一步减小外周区域2中的恢复电流。
(第5实施方式的变形例)
说明本发明的第5实施方式的变形例。在上述第5实施方式中，如图12所示，在FWD区域1b和外周区域2的边界部分，与FWD区域1b的内缘部相比，注入抑制区域16稀疏地形成。具体地说，在FWD区域1b和外周区域2的边界部分，与FWD区域1b的内缘部相比，邻接的注入抑制区域16的沿着沟槽13的延设方向的间隔更长。更详细地说，在FWD区域1b和外周区域2的边界部分，与注入抑制区域16的长度Wn2相比，接触区域17的长度Wp2更长。由此，与上述图11中说明的半导体装置相比，使FWD元件进行二极管动作时的空穴的注入变多，能够提高FWD元件的特性。
(其他实施方式)
例如，在上述各实施方式中，说明了第1导电型为N型、第2导电型为P型的例子，但是也可以是第1导电型为P型、第2导电型为N型。
此外，在上述各实施方式中，说明了IGBT区域1a中的发射极区域14的长度Wn1与接触区域15的长度Wp1之比、和FWD区域1b中的注入抑制区域16的长度Wn2与接触区域17的长度Wp2之比不同。但是，IGBT区域1a中的发射极区域14的长度Wn1与接触区域15的长度Wp1之比、和FWD区域1b中的注入抑制区域16的长度Wn2与接触区域17的长度Wp2之比也可以相同。
此外，在上述第3实施方式中，也可以在外周区域2的基极层12形成注入抑制区域16。在这样的半导体装置中，通过该注入抑制区域16，在FWD元件进行二极管动作时，能够进一步抑制空穴注入。
并且，在上述第4实施方式中，距离L也可以低于半导体基板10的一面10a与另一面10b之间的距离(以下称作半导体基板10的厚度)。作为这样的半导体装置，在FWD区域1b的外缘部形成有集电极层23，所以能够减小由外周区域2中的基极层12和FWD区域1b中的阴极层24构成的寄生二极管起作用。
此外，在上述第3实施方式中，也可以以包围IGBT区域1a的方式形成FWD区域1b。即，与外周区域2的边界全部成为FWD区域1b。
进而，也可以将上述各实施方式的半导体装置组合。例如，可以将上述第2实施方式组合到上述第3～第5实施方式而具备体区域26。此外，也可以将上述第4实施方式组合到上述第5实施方式，将FWD区域1b的外缘部作为集电极层23。此外，也可以将上述各实施方式组合之后再进一步组合。
基于实施例说明了本发明，但是本发明不限于该实施例和构造。本发明也包含各种变形例和均等范围内的变形。此外，各种组合或方式、以及仅包含一个要素或其以上或其以下的其他组合和方式，也包含在本发明的范畴和思想范围。

Claims (7)

1.一种半导体装置，具备：
半导体基板(10)，具有第1导电型的漂移层(11)；
第2导电型的基极层(12)，形成于所述漂移层上；
第2导电型的集电极层(23)及第1导电型的阴极层(24)，形成于所述漂移层的与所述基极层侧相反的一侧；
多个沟槽(13)，贯通所述基极层而到达所述漂移层，沿着所述半导体基板的面方向的一个方向形成；
栅极绝缘膜(18)，形成于所述沟槽的壁面；
栅电极(19)，形成于所述栅极绝缘膜上；以及
第1导电型的发射极区域(14)，形成于所述基极层的表层部，与所述沟槽相接，
所述半导体基板中的作为IGBT元件工作的区域是IGBT区域(1a)，作为FWD元件工作的区域是FWD区域(1b)，
所述发射极区域形成于所述IGBT区域，
在所述FWD区域，在所述基极层的表层部，沿着所述一个方向交替地形成有比所述漂移层更高杂质浓度的第1导电型的注入抑制区域(16)和比所述基极层更高杂质浓度的第2导电型的接触区域(17)，
所述半导体基板具备单元区域(1)和外周区域(2)，所述单元区域(1)具有所述IGBT区域及所述FWD区域，所述外周区域(2)包围所述单元区域，且具有所述漂移层，
位于与所述外周区域的边界的所述单元区域的至少一部分是所述FWD区域，
在所述外周区域，在所述漂移层上形成于所述单元区域的基极层延伸设置，
在所述外周区域，在所述漂移层的与所述基极层相反侧的部分形成有所述集电极层，
在所述FWD区域的与所述外周区域的边界部分，所述漂移层之中的与所述基极层侧相反的一侧是集电极层。
2.一种半导体装置，具备：
半导体基板(10)，具有第1导电型的漂移层(11)；
第2导电型的基极层(12)，形成于所述漂移层上；
第2导电型的集电极层(23)及第1导电型的阴极层(24)，形成于所述漂移层的与所述基极层侧相反的一侧；
多个沟槽(13)，贯通所述基极层而到达所述漂移层，沿着所述半导体基板的面方向的一个方向形成；
栅极绝缘膜(18)，形成于所述沟槽的壁面；
栅电极(19)，形成于所述栅极绝缘膜上；以及
第1导电型的发射极区域(14)，形成于所述基极层的表层部，与所述沟槽相接，
所述半导体基板中的作为IGBT元件工作的区域是IGBT区域(1a)，作为FWD元件工作的区域是FWD区域(1b)，
所述发射极区域形成于所述IGBT区域，
在所述FWD区域，在所述基极层的表层部，沿着所述一个方向交替地形成有比所述漂移层更高杂质浓度的第1导电型的注入抑制区域(16)和比所述基极层更高杂质浓度的第2导电型的接触区域(17)，
所述半导体基板具备单元区域(1)和外周区域(2)，所述单元区域(1)具有所述IGBT区域及所述FWD区域，所述外周区域(2)包围所述单元区域，且具有所述漂移层，
位于与所述外周区域的边界的所述单元区域的至少一部分是所述FWD区域，
在所述外周区域，在所述漂移层上形成于所述单元区域的基极层延伸设置，
在所述外周区域，在所述漂移层的与所述基极层相反侧的部分形成有所述集电极层，
在所述FWD区域，形成在与所述外周区域的边界部分的多个注入抑制区域相比于形成在比所述边界部分更靠内缘部的多个注入抑制区域，沿着所述一个方向的邻接的相互间隔更短。
3.一种半导体装置，具备：
半导体基板(10)，具有第1导电型的漂移层(11)；
第2导电型的基极层(12)，形成于所述漂移层上；
第2导电型的集电极层(23)及第1导电型的阴极层(24)，形成于所述漂移层的与所述基极层侧相反的一侧；
多个沟槽(13)，贯通所述基极层而到达所述漂移层，沿着所述半导体基板的面方向的一个方向形成；
栅极绝缘膜(18)，形成于所述沟槽的壁面；
栅电极(19)，形成于所述栅极绝缘膜上；以及
第1导电型的发射极区域(14)，形成于所述基极层的表层部，与所述沟槽相接，
所述半导体基板中的作为IGBT元件工作的区域是IGBT区域(1a)，作为FWD元件工作的区域是FWD区域(1b)，
所述发射极区域形成于所述IGBT区域，
在所述FWD区域，在所述基极层的表层部，沿着所述一个方向交替地形成有比所述漂移层更高杂质浓度的第1导电型的注入抑制区域(16)和比所述基极层更高杂质浓度的第2导电型的接触区域(17)，
所述半导体基板具备单元区域(1)和外周区域(2)，所述单元区域(1)具有所述IGBT区域及所述FWD区域，所述外周区域(2)包围所述单元区域，且具有所述漂移层，
位于与所述外周区域的边界的所述单元区域的至少一部分是所述FWD区域，
在所述外周区域，在所述漂移层上形成于所述单元区域的基极层延伸设置，
在所述外周区域，在所述漂移层的与所述基极层相反侧的部分形成有所述集电极层，
在所述FWD区域，形成在与所述外周区域的边界部分的多个注入抑制区域相比于形成在比所述边界部分更靠内缘部的多个注入抑制区域，沿着所述一个方向的邻接的相互间隔更长。
4.如权利要求1～3中任一项所述的半导体装置，
在所述IGBT区域，在所述基极层的表层部，与所述发射极区域一起形成有第2导电型的接触区域，
该接触区域和所述发射极区域沿着所述一个方向交替地形成，
设所述IGBT区域中的所述发射极区域的沿着所述一个方向的方向的长度(Wn1)与所述接触区域的沿着所述一个方向的方向的长度(Wp1)之比为第一比，设所述FWD区域中的所述注入抑制区域的沿着所述一个方向的方向的长度(Wn2)与所述接触区域的沿着所述一个方向的方向的长度(Wp2)之比为第二比，第一比和第二比不同。
5.如权利要求1～3中任一项所述的半导体装置，
在所述基极层中的所述发射极区域、所述接触区域、所述注入抑制区域的下方形成有体区域(26)，
所述体区域比所述基极层更高杂质浓度，并且沿着所述一个方向延设，与所述接触区域相连，并且与所述沟槽分离。
6.如权利要求1～3中任一项所述的半导体装置，
所述注入抑制区域仅形成在所述FWD区域。
7.如权利要求1所述的半导体装置，
所述半导体基板具有：位于所述基极层侧的一面(10a) 和与该一面相反侧的另一面(10b)，该另一面(10b)位于所述集电极层或所述阴极层侧，
形成于所述FWD区域的集电极层从与所述外周区域的边界起形成为所述半导体基板的一面和另一面之间的长度以上。
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