CN107210190A - 包含硅晶片和碳化硅外延层的复合晶片中晶片弯曲的减少 - Google Patents

包含硅晶片和碳化硅外延层的复合晶片中晶片弯曲的减少 Download PDF

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CN107210190A
CN107210190A CN201580073382.3A CN201580073382A CN107210190A CN 107210190 A CN107210190 A CN 107210190A CN 201580073382 A CN201580073382 A CN 201580073382A CN 107210190 A CN107210190 A CN 107210190A
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silicon carbide
nitrogen
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P·沃德
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Anvil Semiconductors Ltd
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Abstract

我们描述了一种用于减少复合晶片中的弯曲的方法，该复合晶片包含硅晶片和生长于所述硅晶片上的碳化硅层。该方法包括在硅晶片上碳化硅层的生长过程中施加氮原子，以便在复合晶片内产生压应力。

Description

包含硅晶片和碳化硅外延层的复合晶片中晶片弯曲的减少
技术领域
本发明涉及复合晶片(composite wafer)中弯曲(bow)的减少，具体地但不完全是基于碳化硅(SiC)的复合晶片中。
背景技术
制造碳化硅/硅，特别是3-步立方碳化硅(3-step cubic silicon carbide，3C-SiC)和Si异质外延(Si heteroepitaxy)时，所面临的挑战为：由于两种材料之间晶格错配以及从1370℃的典型生长温度降温时SiC更快热收缩而在Si/SiC界面引入的张应力(tensile stress)。
早已证明，用多晶SiC细线将晶片表面划分为每侧约2.5mm的子晶片对减少张应力引起的晶片弯曲是有益的。
本发明目的在于使用有效技术减少晶片弯曲。
发明内容
本发明通过在复合晶片临界部分，即在Si/SiC界面引入抵消作用的压应力(compressive stress)来减少晶片弯曲。为了减少压力和弯曲存在两个动机。首先是提高晶片的坚固性(robustness)，因为高度承压的晶片易碎。其次是制造尽可能平的晶片以便于通过各种设备进行加工制得微电子组件。
据本发明的一个方面，提供了一种用于减少复合晶片中弯曲的方法，所述复合晶片包含硅晶片和生长于硅晶片上的碳化硅外延层。该方法包括在硅晶片上碳化硅层的外延生长过程中施加氮原子，以便在复合晶片内产生压应力。该技术允许氮原子在外延层的初始外延生长(epitaxial growth)过程中掺入晶片。该技术在晶片内产生压应力，抵消引起晶片内引起弯曲的张应力。
据本发明的另一方面，提供了一种复合晶片的制备方法，该方法包括：形成硅晶片；在硅晶片上热生长碳化硅外延层以形成复合晶片；在碳化硅层的热生长期间施加氮原子，以便在复合晶片内生成压应力。
氮原子可以在碳化硅层的初始单晶外延生长阶段或过程中施加。因此，氮原子的引入除了碳化硅层的掺杂分布之外的。应理解的是，SiC掺杂材料可以含有含氮物质，但是在层掺杂期间含氮物质的引入与SiC层外延生长期间引入氮原子是不同的。本发明针对在外延生长过程(独立于SiC层的掺杂过程之外)中施加氮原子。
应理解的是，外延生长工艺和沉积工艺(deposition process)是存在区别的。在沉积工艺中，材料是直接从气体和/或液体(相)成分中的化学反应产生的，那些化学反应的产物以不连贯“雨”的形式到达固体基体上。固体材料通常并非反应形成的唯一产物。副产物可以包括气体、液体甚至其他固体。沉积工艺的例子包括低压化学气相沉积(LPCVD)和等离子体增强气相沉积(PECVD)。通过对比，外延生长工艺完全不同于沉积工艺。如果基体为有序半导体晶体(即，硅、砷化镓等)，有了这个工艺，就可能在基体上继续形成相同的定向结晶，而基体则作为生长模板且通过前体物质吸附到表面上进入精确的晶格位置。沉积工艺包括非晶或小晶粒多晶材料的不连贯雨。外延生长工艺包括基体单晶结构的延续。在沉积工艺中，高氮流可以改变非晶或多晶材料的宏观结构，例如：减少结晶粒尺寸(grainsize)，这会因TCE差异而影响应力。在外延生长工艺中，更低的氮流被完全掺入到微观晶体结构中，通过借助与主晶(host crystal)相比原子尺寸的差异来施加压应力。
关键点是，两种情况的结构和机制不同，因此应意识到，在晶体生长过程中施加氮原子的本发明的技术仅适用于外延生长工艺。
本发明仅涉及在Si上SiC的外延生长过程以及在外延生长过程中施加氮原子以减少晶片弯曲。
在本发明中，在外延生长过程中氮原子构成气相的约0.5％-0.001％，典型的生长温度为1370℃。一般情况下，从应力和缺陷来看，氢气中含氮0.25％是最优化生长SiC的氮含量。
施加氮原子会产生压应力来抵消引起复合晶片弯曲的自然张应力。
所述压应力可产生于复合晶片内与可产生自然张应力相同的部位。
所述硅晶片和碳化硅层间的界面可以包括位错(dislocations)或晶体缺陷。所述界面处的位错或晶体缺陷可以使氮原子以高于单晶的速率掺入。
碳化硅层可以为3-步立方碳化硅(3C-SiC)。该方法也可适用于其他类型碳化硅材料。
施加氮原子可以引起复合晶片大部分的中心部分基本变平，以减少复合晶片弯曲。该技术使晶片整体基本变平，以便一层或多层的层能够易于在初始异质外延(initialheteroepitaxy)的顶部生长，并促进正常半导体器件加工步骤。
氮原子的施加可以穿过整个复合晶片，最终结果为75％的晶片区域可以处于晶片直径约+50微米和约-50微米的范围内。
在碳化硅层晶体生长期间施加的氮原子可以除在形成碳化硅层的掺杂浓度之外的氮原子。一般地，3C-SiC层中通常氮位于掺杂浓度内，但在初始晶体生长过程中氮原子的引入是独立于用于形成掺杂分布的技术。
复合晶片可以为同轴晶片(on-axis wafer)。或者，复合晶片可以为离轴晶片(off-axis wafer)。
据本发明的另一方面，提供了一种碳化硅半导体结构，其包括：单晶硅晶片；生长于所述单晶硅晶片上的碳化硅层。硅晶片和碳化硅层间的界面包括碳化硅层最初生长过程中施加的氮原子，以便在半导体结构内产生压应力。
氮原子可在碳化硅层的初始晶体生长阶段施加。
施加氮原子可产生压应力以抵消引起半导体结构弯曲的自然张应力。
所述压应力可产生于半导体内与可产生自然张应力相同的部位。
所述硅晶片和碳化硅层间的界面可以包括位错或晶体缺陷。
所述界面处的位错或晶体缺陷可以使氮原子以高于单晶的速率掺入。
碳化硅层可以为3-步立方碳化硅(3C-SiC)。
施加氮原子可以引起半导体大部分的中心部分基本变平，以减少半导体结构的弯曲。
氮原子的施加可以穿过整个半导体结构区域。
在所述碳化硅层晶体生长期间施加的氮原子可不形成碳化硅层的掺杂浓度的一部分。
硅晶片可以为同轴晶片。或者，硅晶片可以为离轴晶片。
在本发明的实施方式中，提供了一种SiC器件，其包括：如上所述的半导体结构；和在所述半导体结构上的一个或多个半导体器件(semiconductor device)或晶体管结构(transistor structures)。
SiC二极管可以包括上述SiC器件。SiC绝缘栅双极晶体管(SiC insulated gatebipolar transistor，IGBT)可以包括上述SiC器件。SiC MOSFET可以包括上述SiC器件。
附图说明
本发明公开将从以下详述和附图中获得更充分的理解，然而不应将本发明先定位所示具体实施方式，而是仅用于解释和理解。
图1a-1e表明异质外延的第一处理期间的阶段；
图2表明没有施加氮原子的二维离轴硅晶片[100]的弯曲图形；
图3表明Si、3C-SiC和氮原子的次级离子质谱(Secondary Ion MassSpectrometry，SIMS)分布；
图4表明施加了氮原子的二维离轴硅晶片[100]的弯曲图形；
图5表明另一个施加了氮原子的二维离轴硅晶片[100]的弯曲图形；以及
图6表明在绝缘栅双极晶体管(IGBT)形式下的垂直功率半导体晶体管100(vertical power semiconductor transistor 100)。
具体实施方式
在描述本发明的实施方式前，先参考图1a-1e描述碳化硅/硅异质外延生长过程，这有助于理解本发明。
图1a显示室温(约25℃)下的单晶硅晶片1。硅晶片1充当可层外延生长得到的三步立方碳化硅(3C-SiC)的种子晶片。硅晶片1直径为d。
将硅晶片1置于碳化硅外延反应器(未显示)中，加热到约1350℃。如图1b所示(以高度图解形式)，加热时硅晶片1扩大。加热后的晶片直径为d’，大于室温下晶片的直径d。
参考图1c，在化学气相沉积(CVD)工艺中，将加热后的硅晶片1暴露于硅和碳反应性组分的蒸气2中。蒸气2吸附在硅晶片1上形成三步立方碳化硅。虽然通常碳化硅和硅的晶格常数不同，但三步立方碳化硅的外延层3生长于硅基质1上，通过晶格位错(未显示)与硅的晶格常数相匹配，并形成复合结构4，如图1d所示。然而，在该结构形成期间会形成残留张应力。
此外，如图1e所示，当将复合结构4进行冷却时，碳化硅外延层3收缩速率快于下层的硅晶片3，形成进一步的张应力，结构4因此弯曲。
本发明设法解决这个问题。
图2表明没有施加氮原子的二维离轴硅晶片[100]的弯曲图形。可以看出，离轴晶片200形状为弧形，其中晶片从中心205弯曲。图2的晶片表明实验晶片中的弯曲，而图1e表明示意图中的弯曲。
在本发明中，用于减少晶片弯曲的技术非常简单，包括在晶体生长期间引入氮(SiC中的n-型掺杂)来形成压应力。这是因为在晶格中氮替代碳，但氮更小，因此产生压应力。应意识到，本技术区别于在3C-SiC中引入以提供掺杂分布的氮，其包括在3C-SiC晶体生长过程中施加氮原子。引入氮原子以便在3C-SiC层和复合晶片中产生压应力，这可以抵消晶片中产生的张应力。该技术为独立于引入氮以形成掺杂分布的步骤。
在本发明的实施方式中，界面的性质有助于这一方法，在其界面中有高浓度晶体缺陷，而这些缺陷使氮以高于常规单晶的速率掺入。图3显示Si、3C-SiC和氮离子的次级离子质谱(SIMS)分布。图3的SIMS分布显示氮(原子态)流对掺杂浓度校准。氮流300在SiC层的底部～3.6微米处以100sccm(标准立方厘米每分钟)保持恒定，但是很明显，在界面处掺入率高且逐渐减少至平衡的单晶值。图3中的氮分布为原子分布，它显示外延生长过程期间的氮原子流在Si/3C-SiC界面中更有效。氮的高掺入率有助于在张应力自然产生的相同位点产生压应力。因此，压应力可在形成自然弯曲的位置抵消推/拉晶片的张应力。
图4表明施加了氮原子的二维离轴硅晶片[100]的弯曲图形。在该例子中，在碳化硅层初始生长阶段添加了约200sccm的氮。与图2相比，这产生了更复杂的形状。在初始生长阶段施加氮原子后，晶片形成一个“Pringle(菱形格纹)”形状。如图4所示，晶片的中心400由于总应力减少而凸起，这是由于引入了压应力。
图5表明另一个施加了氮原子的二维离轴硅晶片[100]的弯曲图形。应意识到，优化的方法可以制造弯曲锐减的晶片，且对在用于加工设备中的整个过程都有所优化。图5显示了这种晶片的一个例子。一般地，目标应为形成最大晶片区域其高度约+50微米和约-50微米的范围内。
图6表明在绝缘栅双极晶体管(IGBT)形式下的垂直功率半导体晶体管100。晶体管100具有p-型硅基体110和使用本发明中上述实施方式所述方法生长的第一3-步立方碳化硅(3C-SiC)外延层120。氮原子流入或施加到基体110和外延层120之间的界面中。该技术有助于减少晶片弯曲或为外延层120提供基本上平的表面。因此，将另外的3C-SiC层形成于外延层120的基本平的表面上。在该例子中，碳化硅外延层120、130包括一个重掺杂的p型层120(heavily-doped p-type layer 120)，设置在p-型硅基体110上，以及一个轻掺杂的n-型层130(lightly-doped n-type layer 130)以提供漂移区(drift region)，并设置在p-型碳化硅层120上。第一外延层120提供p-型集电体(p-type collector)。位于外延层130的表面160的p-型阱140(p-type wells140)提供主体区140。位于p-型阱140内的n-型阱150提供接触区并提供发射体(emitters)。主体区140和接触区150可由3C-SiC材料构成。通道170形成于栅180下，并使用栅极介电层190隔开(gate dielectric layer 190)。所有这些层的使用都用到了3C-SiC层。
虽然在图6中给出了IGBT的示例，但是本领域技术人员显然也可以将本技术同样适用于形成其他半导体器件和晶体管，例如：二极管、MOSFET、晶体闸流管(Thyristor)。
虽然本说明书引用了硅基体和3C-SiC外延层界面，但是应意识到，该技术同样可以适用于其他多种类型SiC。
虽然本发明已如上述优选例子进行了描述，但是应理解这些例子仅为解说性的，权利要求不限于这些例子。本领域技术人员能够基于被视为属于所附权利要求范围的本发明进行修改和替代。本说明书中公开或表明的每个特性都可并入本发明，无论以单独还是以与本文中任何其他公开或表明的特性适当结合的形式。

Claims (31)

1.一种用于减少复合晶片中弯曲的方法，所述复合晶片包含硅晶片和生长于所述硅晶片上的碳化硅外延层，该方法包括：
在硅晶片上碳化硅层的外延生长过程中施加氮原子，以便在复合晶片内产生压应力。
2.一种复合晶片的制备方法，该方法包括：
形成硅晶片；
在硅晶片上热生长碳化硅外延层以形成复合晶片；以及
在碳化硅层的热外延生长过程中施加氮原子，以便在复合晶片内产生压应力。
3.根据权利要求1或2所述的方法，其中，氮原子在碳化硅层的单晶外延生长阶段施加。
4.根据前述权利要求中任意一项所述的方法，其中，施加氮原子产生压应力以抵消引起复合晶片弯曲的自然张应力。
5.根据权利要求4所述的方法，其中，所述压应力产生于复合晶片内与产生所述自然张应力相同的部位。
6.根据前述权利要求中任意一项所述的方法，其中，所述硅晶片和碳化硅层间的界面包括位错或晶体缺陷。
7.根据权利要求6所述的方法，其中，所述界面处的位错或晶体缺陷使氮原子以高于单晶的速率掺入。
8.根据前述权利要求中任意一项所述的方法，其中，所述碳化硅层为3-步立方碳化硅(3C-SiC)。
9.根据前述权利要求中任意一项所述的方法，其中，施加氮原子引起复合晶片大部分中心部分基本变平，以减少复合晶片弯曲。
10.根据前述权利要求中任意一项所述的方法，其中，氮原子的施加基本穿过复合晶片的整个区域。
11.根据前述权利要求中任意一项所述的方法，其中，在碳化硅层的单晶外延生长期间，施加的氮原子不形成碳化硅层掺杂浓度的一部分。
12.根据前述权利要求中任意一项所述的方法，其中，所述复合晶片是同轴晶片。
13.根据权利要求1-11中任意一项所述的方法，其中，所述复合晶片是离轴晶片。
14.一种碳化硅半导体结构，其包括：
单晶硅晶片；
生长于所述单晶硅晶片上的碳化硅外延层；
其中，所述硅晶片和碳化硅层间的界面包含碳化硅层外延生长过程中施加的氮原子，以便在半导体结构内产生压应力。
15.根据权利要求14所述的半导体结构，其中，氮原子在碳化硅层的单晶外延生长阶段施加。
16.根据权利要求14或15所述的半导体结构，其中，施加氮原子产生压应力以抵消引起半导体结构弯曲的自然张应力。
17.根据权利要求14、15或16所述的半导体结构，其中，所述压应力产生于半导体内与产生自然张应力相同的部位。
18.根据权利要求14-17中任意一项所述的半导体结构，其中，所述硅晶片和碳化硅层间的界面包括位错或晶体缺陷。
19.根据权利要求18所述的半导体结构，其中，所述界面处的位错或晶体缺陷使氮原子以高于单晶的速率掺入。
20.根据权利要求14-19中任意一项所述的半导体结构，其中，所述碳化硅层为3-步立方碳化硅(3C-SiC)。
21.根据权利要求14-20中任意一项所述的半导体结构，其中，施加氮原子引起半导体结构大部分中心部分基本变平，以减少半导体结构的弯曲。
22.根据权利要求14-21中任意一项所述的半导体结构，其中，氮原子的施加基本穿过半导体结构的整个区域。
23.根据权利要求14-22中任意一项所述的半导体结构，其中，在所述碳化硅层的单晶外延生长期间，施加的氮原子不形成碳化硅层掺杂浓度的一部分。
24.根据权利要求14-23中任意一项所述的半导体结构，其中，所述硅晶片是同轴晶片。
25.根据权利要求14-23中任意一项所述的半导体结构，其中，所述硅晶片是离轴晶片。
26.一种SiC器件，其包括：
根据权利要求14-23中任意一项所述的半导体结构；和
在所述半导体结构上的一个或多个半导体器件或晶体管结构。
27.包括权利要求26所述的SiC器件的SiC二极管。
28.包括权利要求26所述的SiC器件的SiC绝缘栅双极晶体管(IGBT)。
29.包括权利要求26所述的SiC器件的SiC MOSFET。
30.一种用于减少复合晶片中弯曲的方法和用于生产复合晶片的方法，基本如上文所述，参照附图所示。
31.碳化硅半导体结构，基本如上文所述，参照附图所示。
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Publication number Priority date Publication date Assignee Title
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005057630A2 (en) * 2003-08-01 2005-06-23 The Regents Of The University Of California Manufacturable low-temperature silicon carbide deposition technology
JP2006032457A (ja) * 2004-07-13 2006-02-02 Shindengen Electric Mfg Co Ltd ＳｉＣ半導体装置およびＳｉＣ半導体装置の製造方法
KR100796607B1 (ko) * 2006-08-08 2008-01-22 삼성에스디아이 주식회사 다결정 실리콘 결정화방법과 그를 이용한 박막트랜지스터의 제조 방법
US20090014756A1 (en) * 2007-07-13 2009-01-15 Narsingh Bahadur Singh Method of producing large area SiC substrates
CN101442010A (zh) * 2007-11-21 2009-05-27 中国科学院半导体研究所 图形衬底上生长碳化硅厚膜的方法
US20110006309A1 (en) * 2007-09-12 2011-01-13 Showa Denko K.K. EPITAXIAL SiC SINGLE CRYSTAL SUBSTRATE AND METHOD OF MANUFACTURE OF EXPITAXIAL SiC SINGLE CRYSTAL SUBSTRATE
WO2011022520A1 (en) * 2009-08-18 2011-02-24 Qs Semiconductor Australia Pty Ltd. Substrates and methods of fabricating epitaxial silicon carbide structures with sequential emphasis
GB2495949A (en) * 2011-10-26 2013-05-01 Anvil Semiconductors Ltd Epitaxially deposited silicon carbide
US20130221377A1 (en) * 2010-10-13 2013-08-29 The University Of Warwick Heterogrowth
GB2514268A (en) * 2011-10-26 2014-11-19 Anvil Semiconductors Ltd Silicon carbide epitaxy

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6537733B2 (en) * 2001-02-23 2003-03-25 Applied Materials, Inc. Method of depositing low dielectric constant silicon carbide layers
US20040259379A1 (en) * 2003-06-23 2004-12-23 Yoshi Ono Low temperature nitridation of silicon
US20110146787A1 (en) * 2008-05-28 2011-06-23 Sebastien Allen Silicon carbide-based antireflective coating
CN102931072A (zh) * 2012-11-12 2013-02-13 上海华力微电子有限公司 双应力薄膜的制造方法以及半导体器件
JP6248532B2 (ja) * 2013-10-17 2017-12-20 セイコーエプソン株式会社 ３Ｃ−ＳｉＣエピタキシャル層の製造方法、３Ｃ−ＳｉＣエピタキシャル基板および半導体装置

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005057630A2 (en) * 2003-08-01 2005-06-23 The Regents Of The University Of California Manufacturable low-temperature silicon carbide deposition technology
JP2006032457A (ja) * 2004-07-13 2006-02-02 Shindengen Electric Mfg Co Ltd ＳｉＣ半導体装置およびＳｉＣ半導体装置の製造方法
KR100796607B1 (ko) * 2006-08-08 2008-01-22 삼성에스디아이 주식회사 다결정 실리콘 결정화방법과 그를 이용한 박막트랜지스터의 제조 방법
US20090014756A1 (en) * 2007-07-13 2009-01-15 Narsingh Bahadur Singh Method of producing large area SiC substrates
US20110006309A1 (en) * 2007-09-12 2011-01-13 Showa Denko K.K. EPITAXIAL SiC SINGLE CRYSTAL SUBSTRATE AND METHOD OF MANUFACTURE OF EXPITAXIAL SiC SINGLE CRYSTAL SUBSTRATE
CN101442010A (zh) * 2007-11-21 2009-05-27 中国科学院半导体研究所 图形衬底上生长碳化硅厚膜的方法
WO2011022520A1 (en) * 2009-08-18 2011-02-24 Qs Semiconductor Australia Pty Ltd. Substrates and methods of fabricating epitaxial silicon carbide structures with sequential emphasis
US20130221377A1 (en) * 2010-10-13 2013-08-29 The University Of Warwick Heterogrowth
GB2495949A (en) * 2011-10-26 2013-05-01 Anvil Semiconductors Ltd Epitaxially deposited silicon carbide
GB2514268A (en) * 2011-10-26 2014-11-19 Anvil Semiconductors Ltd Silicon carbide epitaxy

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
CHRISTIAN A. ZORMAN ET AL: "Epitaxial growth of 3C–SiC films on 4 in. diam (100) silicon wafers by atmospheric pressure chemical vapor deposition", 《JOURNAL OF APPLIED PHYSICS 》 *
MITSUGU YAMANAKA ET AL: "Temperature Dependence of Electrical Properties of Nitrogen-Doped 3C-SiC", 《JAPANESE JOURNAL OF APPLIED PHYSICS》 *

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