CN107204300A - 用于制造芯片复合结构的方法 - Google Patents

用于制造芯片复合结构的方法 Download PDF

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Publication number
CN107204300A
CN107204300A CN201710156264.XA CN201710156264A CN107204300A CN 107204300 A CN107204300 A CN 107204300A CN 201710156264 A CN201710156264 A CN 201710156264A CN 107204300 A CN107204300 A CN 107204300A
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China
Prior art keywords
coordination electrode
filler
chip
coordination
wire structures
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CN201710156264.XA
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English (en)
Inventor
A·海因里希
I·埃舍尔-珀佩尔
M·格鲁贝尔
A·蒙丁
C·威尔
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Infineon Technologies AG
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Infineon Technologies AG
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Publication of CN107204300A publication Critical patent/CN107204300A/zh
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Abstract

本发明的一个方面涉及一种用于制造芯片复合结构的方法。分别通过使导电的第一平衡片(21)与半导体芯片(1)的第一主电极(11)材料锁合地且导电地连接来制造两个或更多个芯片组件(2)。在所述芯片组件(2)之间的自由空间(211)中布置控制电极布线结构(70)。在所述控制电极布线结构(70)与各个芯片组件(2)的半导体芯片(1)的控制电极(13)之间建立导电连接。借助介电填料(4)使所述芯片组件(2)材料锁合地连接。

Description

用于制造芯片复合结构的方法
技术领域
本发明涉及芯片复合结构(Chipverbund)的制造，所述芯片复合结构可以应用在紧压包装单元(Press-Pack-Zelle)中。
背景技术
常规的紧压包装单元具有多个半导体芯片，所述多个半导体芯片松脱地挤压在导电的压力接触件之间并且在此电接触并且必要时并联连接。然而，各个半导体芯片的处理是困难的并且因此值得期望的是，简化该处理。
发明内容
本发明的一个方面涉及一种用于制造芯片复合结构的方法。在此，分别通过使导电的第一平衡片与半导体芯片的第一主电极材料锁合地且导电地连接来制造两个或更多个芯片组件。在所述芯片组件之间的自由空间中布置控制电极布线结构。在所述控制电极布线结构与各个芯片组件的半导体芯片的控制电极之间建立导电连接。借助介电填料使所述芯片组件材料锁合地连接。
本发明提出一种用于制造芯片复合结构的方法，所述方法具有：分别通过使导电的第一平衡片与半导体芯片的第一主电极材料锁合地且导电地连接来制造两个或更多个芯片组件；在所述芯片组件之间的自由空间中布置控制电极布线结构；在所述控制电极布线结构与各个芯片组件的半导体芯片的控制电极之间建立导电连接；借助介电填料使所述芯片组件材料锁合地连接。
根据所述方法的一种有利的扩展方案，借助所述填料的第一部分使所述半导体芯片相互材料锁合地连接，从而所述第一部分覆盖所述控制电极；在所述第一部分中分别在所述控制电极的区域中产生开口，从而所述控制电极在所述相应的开口中暴露；以及借助所述控制电极布线结构使所述控制电极穿过所述开口地相互导电连接。
根据所述方法的一种有利的扩展方案，借助导电粘接剂使所述控制电极布线结构与所述控制电极导电连接。
根据所述方法的一种有利的扩展方案，为了所述开口，借助以下中的至少一个局部地除去所述第一部分：激光束；蚀刻剂。
根据所述方法的一种有利的扩展方案，使所述控制电极直接在所述第一部分开口之后暴露；或者，在所述半导体芯片的每一个中，使其控制电极在所述控制电极的与所述半导体芯片的半导体本体背离的一侧上与导电接触件材料锁合地以及导电地连接，其中，所述接触件直接在所述第一部分开口之后暴露。
根据所述方法的一种有利的扩展方案，所述第一部分是酰亚胺或模制材料。
根据所述方法的一种有利的扩展方案，在借助所述控制电极布线结构使所述控制电极相互导电连接之后，将所述控制电极布线结构嵌入到所述填料的第二部分中并且在此由所述第二部分覆盖所述控制电极布线结构。
根据所述方法的一种有利的扩展方案，所述第二部分是模制材料。
根据所述方法的一种有利的扩展方案，所述控制电极布线结构具有多个键合引线以及一个或多个键合支承点元件，其中，至少一个键合支承点元件布置在所述芯片组件之间的自由空间中；以及使所述控制电极中的每一个借助所述键合引线之一与一个键合支承点元件导电连接。
根据所述方法的一种有利的扩展方案，所述控制电极布线结构具有第一键合引线、第二键合引线和键合支承点元件；所述第一键合引线、所述键合支承点元件和所述第二键合引线串联电连接在所述控制电极中的第一控制电极与所述控制电极中的第二控制电极之间并且将所述控制电极中的第一和第二控制电极相互导电连接；使所述第一键合引线和所述第二键合引线分别直接键合到所述键合支承点元件上。
根据所述方法的一种有利的扩展方案，使所述第一键合引线直接键合到所述控制电极中的所述第一控制电极上或者直接键合到第一接触件上，所述第一接触件布置在所述控制电极中的所述第一控制电极的与所属的半导体本体背离的一侧上并且与所述侧导电连接；使所述第二键合引线直接键合到所述控制电极中的所述第二控制电极上或者直接键合到第二接触件上，所述第二接触件布置在所述控制电极中的所述第二控制电极的与所属的半导体本体背离的一侧上并且与所述侧导电连接。
根据所述方法的一种有利的扩展方案，在借助所述介电填料使所述半导体芯片相互材料锁合地连接之前借助所述控制电极布线结构使所述控制电极电连接。
根据所述方法的一种有利的扩展方案，在通过所述介电填料使所述半导体芯片相互材料锁合地连接之后借助所述控制电极布线结构使所述控制电极电连接。
根据所述方法的一种有利的扩展方案，在借助所述填料使所述半导体芯片相互材料锁合地连接之后由所述填料覆盖所述控制电极；在借助所述控制电极布线结构使所述控制电极电连接之前，在所述填料中分别在所述控制电极的区域中产生开口，从而所述控制电极在所述相应的开口中暴露；以及借助所述控制电极布线结构使所述控制电极穿过所述开口地导电连接。
根据所述方法的一种有利的扩展方案，所述第一平衡片中的每一个在20℃的温度下具有小于11ppm/K或者小于7ppm/K的线性热膨胀系数。
根据所述方法的一种有利的扩展方案，所述半导体芯片中的每一个具有第二主电极，在所述第二主电极上，使所述半导体芯片与导电的第二平衡片材料锁合地且导电地连接。
根据所述方法的一种有利的扩展方案，所述第二平衡片中的每一个在20℃的温度下具有小于11ppm/K或者小于7ppm/K的线性热膨胀系数。
根据所述方法的一种有利的扩展方案，所述控制电极布线结构具有元件，首先预制所述元件并且随后将所述元件布置在所述自由空间中并且随后将所述元件与至少一个控制电极导电连接。
根据所述方法的一种有利的扩展方案，将所述预制的元件构造为：金属板；或电路板；或单侧或双侧导电地金属化的半导体衬底；或单侧或双侧导电地金属化的功能半导体芯片；或单侧或双侧导电地金属化的玻璃衬底；或单侧或双侧导电地金属化的陶瓷衬底。
附图说明
以下根据实施例参照附图进一步阐述本发明。在附图中，相同附图标记表示相同的或作用相同的元素。其中：
图1至17：用于制造芯片复合结构的第一示例的不同步骤；
图18至20：用于制造芯片复合结构的第二示例的不同步骤；
图21至23：用于制造芯片复合结构的第三示例的不同步骤；
图24至27：用于制造芯片复合结构的第四示例的不同步骤；
图28至29：用于制造芯片复合结构的第五示例的不同步骤；
图30至31：用于制造芯片复合结构的第六示例的不同步骤；
图32至33：用于制造紧压包装单元的方法的不同步骤，其中，芯片复合结构布置在壳体的两个导电接触板之间；
图34：紧压包装单元的一个区段的垂直剖面，所述紧压包装单元具有根据图16构造的芯片复合结构；
图35：一个装置的垂直剖面，在所述装置中，紧压包装单元压入在两个压力接触件之间并且在此通过所述两个压力接触件电接触。
具体实施方式
图1示出半导体芯片1以及用于制造中间产品的另外的部分，如其在图3中所示的那样。半导体芯片1具有由半导体基本材料制成的半导体本体10，其中，为了实现集成到半导体本体10中的功率半导体构件，尤其可以包含p型导电的和n型导电的半导体区域。此外，半导体芯片1还可以具有任意多的导电层，如例如金属化部、硅化物层或者由掺杂的多晶半导体材料(例如多晶硅)构造的层，但也可以具有任意多的介电层，如例如氮化物层(例如氮化硅)或氧化物层(例如氧化硅)或者钝化层，如例如酰亚胺层。半导体基本材料可以是每种已知的通常用于制造半导体构件的半导体基本材料，例如任意的元素半导体(例如硅、锗)，任意的复合半导体(例如II-VI半导体，如硒化锌或者硫化镉；III-V半导体，如磷化镓，砷化镓，磷化铟，锑化铟；或者IV-IV半导体，如碳化硅或锗化硅)。
半导体本体10具有上侧10t以及与上侧相对的下侧10b。上侧10t沿垂直方向v与下侧10b间隔开，其中，垂直方向v垂直于下侧10b地延伸。在上侧10t上布置有第一(上)主电极11，在下侧10b上布置有第二(下)主电极12。控制电极13同样位于上侧10t上。此外，可选的上介电钝化层15可施加到上侧10t上。所述钝化层15例如可以是聚酰亚胺。
上主电极11、下主电极12和控制电极13可以例如是薄的金属化层。这样的金属化层可以例如已经在半导体芯片1的制造期间在具有另外的相同的半导体芯片1的晶片复合结构中施加到半导体本体10上，也就是还在晶片分离为相互独立的半导体芯片1之前。
如图2所示，多个这样的半导体芯片1可以共同地并且相互间隔开地装配在导电的下平衡片22上，其方式是，将这些半导体芯片分别在其下主电极12上借助下连接层32与下平衡片22材料锁合地并且导电地连接。那么，下平衡片22位于下主电极12的与半导体本体10背离的一侧上。
在半导体芯片1装配在下平衡片22上之前、同时或——如在此所示——之后，使每个半导体芯片1材料锁合地设有自身的导电的上平衡片21，其方式是，使上平衡片21借助上连接层31材料锁合地——例如通过焊接、粘接或烧结与上主电极11连接。上平衡片21那么位于所涉及的半导体芯片1的上主电极11的与所涉及的半导体芯片1的半导体本体10背离的一侧上。
在所述半导体芯片1中的每一个的控制电极13上还可以可选地安装有导电接触件23，所述接触件借助上连接层31与控制电极13材料锁合地并且导电地连接。只要设有这样的接触件23，则位于其旁边的上平衡片21可以具有留空213(图1)，接触件23放置在所述留空中。
分别可选的平衡片21和22尤其用于消除机械应力，所述机械应力在如下情况下出现，即当借助稍后阐述的接触板41或42(例如由铜制成)使这样的平衡片21、22压力接触时，所述接触板具有与半导体本体10的热膨胀系数显著不同的热膨胀系数。只要平衡片21、22不存在，则接触板41或42直接接触非常薄的主电极11或12。
平衡片21和22(在装配在上主电极11或下主电极12上之前以及直接在装配之后)沿垂直方向v——相互独立地并且以相互任意组合地——具有相对大的厚度d21'或d22'，例如至少0.5毫米、至少1毫米或至少1.5毫米。如果平衡片21和/或22如稍后还将阐述的那样被磨削，则通过大的厚度应避免主电极11或12的损坏。
可选地，上平衡片21和/或下平衡片22可以分别具有线性的热膨胀系数，所述热膨胀系数显著小于还要描述的接触板41、42的线性热膨胀系数，以便实现接触板41、42的高的线性热膨胀系数与半导体本体10的低的线性热膨胀系数的匹配。例如上平衡片21和/或下平衡片22可以在20℃的温度下具有小于11ppm/K或者甚至小于7ppm/K的线性热膨胀系数。上平衡片21和/或下平衡片22可以在此例如由以下材料之一组成、具有以下材料之一或者具有以下构造之一：钼；金属基复合材料(MMC材料)，例如AlSiC(铝-硅-碳化物)；具有两个或更多个金属层的多层材料，例如具有层序列铜-钼-铜(Cu-Mo-Cu)的三层材料，其例如具有比例为1：4：1的层厚，这产生大约7.3ppm/K的Cu-Mo-Cu三层材料的膨胀系数。
上连接层31可以例如构造为任意的焊接层，尤其也可以构造为扩散焊接层、包含经烧结的金属粉末(例如银粉末或银凝聚块)的经烧结的层(也即烧结层)、或者导电粘接层。与此无关地，下连接层32也可以构造为任意的焊接层，尤其也可以构造为扩散焊接层、包含经烧结的金属粉末(例如银粉末或银凝聚块)的经烧结的层(也即烧结层)或者构造为导电粘接层。上连接层31和下连接层32可以尤其由相同材料组成，但也可以使用对于所述两个层提到的材料的任意组合。
在图1中，用于制造上连接层31或下连接层32的初始材料以31'或32'表示。因此应表述为，初始的连接机构31'和32'在连接建立之后可以以变化的形式存在。
在构造为焊料的初始材料31'、32'(例如包含锌的焊料)的情况下，最终的连接层31或32可以包含如下材料(例如铜)：所述材料在上主电极11或下主电极12的连接过程期间扩散到焊料中并且因此是已制成的连接层31或32的组成部分。为了建立连接，焊料31'、32'可以例如以焊膏的形式涂覆到主电极11、12和/或平衡片21、22上(例如借助丝网印刷或打字蜡纸印刷)。但同样地，焊料31'、32'也可以以预制的焊片(“预成型的焊料”)的形式***在上平衡片21与所涉及的半导体芯片1的上主电极11之间或者在下平衡片22与下主电极12之间。在每种情况下，使用于建立所阐述的连接的焊膏或一个/多焊片熔化并且随后冷却，从而在上平衡片21与上主电极11之间或者在下平衡片22与下主电极12之间分别产生材料锁合的连接。
在构造为经烧结的层的连接层31或32的情况下，其所基于的初始材料31'或32'可以构造为膏，所述膏包含金属粉末(例如银粉末或银凝聚块)以及溶剂。为了建立连接，可以将膏例如涂覆到主电极11、12上和/或平衡片21、22上(例如通过丝网印刷或打字蜡纸印刷)。由膏形成的膏层随后分别布置在上主电极11与上平衡片21之间并且分别接触它们。相应地，由膏形成的另一膏层布置在下主电极12与下平衡片22之间并且分别接触它们。在该状态中，通过包含在其中的溶剂的蒸发来烘干膏层并且随后将膏层烧结，其中，烧结可以在明显低于250℃的温度下实现。通过烧结，由膏层形成(导电的)上连接层31或(导电的)下连接层32。
在构造为导电粘接层的连接层31或32的情况下，其所基于的初始材料31'或32'构造为导电粘接剂。为了建立连接，可以将粘接剂例如涂覆到主电极11、12上和/或平衡片21、22上(例如通过丝网印刷或打字蜡纸印刷)。分别一个由粘接剂形成的上粘接材料层布置在上主电极11与上平衡片21之间并且分别接触它们。通过随后的硬化，由上粘接材料层形成导电的上连接层31。相应地，由粘接剂形成的下粘接材料层布置在下主电极12与下平衡片22之间并且分别接触它们。通过随后的硬化，由下粘接材料层形成导电的下连接层32。
只要设有可选的接触件23，则可以借助所述连接技术中的任意连接技术将所述接触件与控制电极13材料锁合地连接，如其已经对于在上平衡片21与上主电极11之间的连接阐述的那样，更确切地说，与对于在上平衡片21与上主电极11之间的连接选择的连接技术无关。
每个半导体芯片1和所属的上平衡片21形成芯片组件2的组成部分，如图3所示的那样。如图3所示，多个这样的芯片组件2可以在芯片组件2的半导体芯片1的下主电极12上如所阐述的那样与下平衡片22材料锁合地并且导电地连接。
在上平衡片21装配在半导体芯片1上之后或之前或者甚至在半导体芯片1装配在下平衡片22上之前，下平衡片22可以为了进一步处理而暂时地必要时连同已经与其材料锁合地连接的半导体芯片1和/或与半导体芯片1材料锁合地连接的上平衡片21固定在辅助载体300上，这作为结果在图4中示出。为此，辅助载体300例如可以具有粘性的表面。也可以使用双侧粘接薄膜，借助所述粘接薄膜，下平衡片22与辅助载体300粘接。结果，上平衡片21分别位于所涉及的半导体芯片1的与辅助载体300背离的一侧上，而下平衡片22布置在一方面半导体芯片1与另一方面辅助载体300之间。
如此外在图5中示出的那样，随后位于辅助载体300上并且设有上平衡片21的半导体芯片1嵌入到粘稠的填料4a中。如图6所示，例如填料4a可以借助冲具310朝半导体芯片1和辅助载体300的方向挤压，从而至少位于分别相邻的半导体芯片1之间的间隙以填料4a填充。为此，在填料4a事先施加到位于辅助载体300上并且设有上平衡片21的半导体芯片1上之后，冲具310可以从半导体芯片1的和填料4a的与辅助载体300背离的一侧相对于填料4a按压。由此，使填料4a均匀地分布在半导体芯片1上并且使位于半导体芯片1之间的间隙以填料4a填充，这作为结果在图7中在取走冲具7之后示出。
在取走冲具7之前、期间或之后填料4a被硬化，从而嵌入到填料4a的半导体芯片1连同填料4a一起形成固定的复合结构。半导体芯片1因此借助填料4a相互材料锁合地连接。
填料4a至少在硬化状态中是介电的。作为填料4a例如缩聚的聚合物(例如环氧树脂或基于聚氨酯的浇铸材料)适用。填料4a尤其可以是模制材料(Moldmasse)，模制材料通过加压或注塑来施加。然而，理论上对于本发明的全部构型可以使用任意填料4a，只要所述填料在硬化状态中是介电的。根据本发明，填料4a尤其可以由均匀的材料或均匀的材料混合物形成。
根据可选的、同样在图5至7中示出的构型，冲具310可以具有一个或多个突出部311，所述一个或多个突出部当冲具310相对于还未硬化的填料4a按压的时候伸入到在相邻的芯片组件2之间的自由空间211中，从而所述自由空间211未以填料4a填充。
原则上，在相邻的芯片组件2之间的这样的自由空间211也可以通过任意的其他方式制造，例如通过铣削、化学方式(通过掩膜蚀刻)、通过激光烧蚀或者通过任意其他适合的方法。
与如何实现这样的自由空间211无关地，这些自由空间可以用于容纳控制电极布线结构70。一般地，控制电极布线结构70是导电结构，所述导电结构用于将半导体芯片1的控制电极13相互导电连接，以及借助连接点通过全部控制电极13可以输送相同的、也即共同的电控制信号。
如由根据图7的装置(可选地由辅助载体300取下)的在图8中示出的放大的区段可见的那样，控制电极13还可以由填料4a中的一层覆盖。在这样的情况下，在填料4a中构造开口的情况下填料4a在控制电极13之上被局部开口，以便能够实现控制电极13的电接触。为此可以使用激光束401和/或蚀刻剂402，这在图9中以及作为结果在图10中示出。
在蚀刻剂的情况下可以在使用经结构化的蚀刻掩膜的情况下以掩膜的方式实现蚀刻，在填料4a上产生所述蚀刻掩膜并且所述蚀刻掩膜在控制电极13之上具有开口。只要控制电极13仅仅由填料4a的非常薄的层覆盖，蚀刻也就可以无掩膜地实现，因为控制电极13随后在蚀刻时被暴露，而填料4a在其他(较厚的)区域中没有被开口。作为蚀刻方法原则上任意蚀刻方法适用，例如各向同性的(借助液体蚀刻剂的蚀刻)或者各向异性的蚀刻方法(例如反应式离子蚀刻；RIE)。在图9和10中的水平箭头示意地表示激光束401的运动。
在任何情况下，结果，可以使控制电极13基于被开口的填料4a而电接触并且相互电连接，这原则上根据任意技术是可能的。在所示出的例子中，控制电极配备有可选的接触件23。接触件23在填料4a开口之后暴露并且可以直接接触。只要不应用接触件23，控制电极13自身就是接触件，控制电极13在填料4a开口之后暴露并且可以直接被接触。
根据按照图11至13阐述的例子，控制电极布线结构70(图12和13)可以借助导电粘接剂75穿过被开口的填料4导电地或者与控制电极13(只要不应用接触件23)或者与接触件23直接粘接。在该意义上，“直接”表示：粘接剂75一方面贴靠在控制电极13上(只要不应用接触件23)或者贴靠在接触件23上，另一方面贴靠在控制电极布线结构70上。
如在图12和13中(仅仅示例性地)示出的那样，控制电极布线结构70可以具有经结构化或未经结构化的金属板，或者构造为经结构化或未经结构化的金属板。可选地，这样的金属板可以构造为平整的板。在本发明的意义上，薄的金属薄膜也视为“金属板”。
然而，原则上也可应用任意的其他控制电极布线结构70。一般地，控制电极布线结构70可以任意地构造，只要借助控制电极布线结构可以实现控制电极13的导电连接。可选地，控制电极布线结构70可以完全安置在相邻芯片组件2之间的自由空间211中，这同样在图13中示出。
图14示出根据图13的整个装置的俯视图，该装置具有在填料4a中暴露的上平衡片21并且具有控制电极布线结构70。控制电极布线结构70的连接点701稍后用作用于控制电极13的共同电接触的连接点。
在根据图14的装置中，示例性地16个半导体芯片1以4×4矩阵的形式并排地布置在下平衡片22上。如同样示出的那样，可选地，所述半导体芯片1中的分别四个可以如此并排地布置在2×2矩阵中，使得控制电极13(在图14中由控制电极布线结构70覆盖；控制电极分别位于上平衡片21的留空213的区域中)分别位于四个半导体芯片1的相互朝向的角上。原则上，如在本发明的所有其他例子中那样，半导体芯片1的数量和布置是任意的，也即可以连接少于或多于16个半导体芯片1。例如，半导体芯片1的数量可以通过2的幂2n(其中，n>2)来给定。与此无关地，半导体芯片1的数量可以为例如至少4、至少8或者甚至至少16。
设有控制电极布线结构70的装置——如其示例性地在图13和14中所示的那样——可选地还可以设有另一填料4b，该另一填料也部分地或完全地嵌入控制电极布线结构70，这作为结果在图15中示出。作为用于另一填料4b的材料可以应用已经阐述的可用于填料4a的材料中的全部材料，更确切地说，以任意的材料组合。尤其对于填料4a和4b也可以应用相同材料。
在本申请的范围中，附图标记“4”表示填料。填料可以仅仅由第一部分4a组成，但填料也可以具有第一部分4a和第二部分4b或者由第一部分4a和第二部分4b组成。
因为上平衡片21可以以填料4a和/或4b覆盖，所以可以磨削所述装置，直至上平衡片21可以分别在其与所属的半导体芯片1背离的一侧上暴露并且因此可以被电接触，这作为结果在图16中示出。由此例如可以实现，上平衡片21的与所属半导体芯片1背离的一侧布置在一个平面中。在磨削之后也借助填料4相互材料锁合地连接的半导体芯片1、在其与半导体芯片1背离的一侧上暴露的上平衡片21、填料4以及控制电极布线结构70是复合结构6的组成部分。
磨削可以例如通过加工(磨制、抛光、研磨等)在传统晶片磨削设备中实现。在所有构型中——在所述构型中磨削上平衡片21，上平衡片21的厚度相比于其初始厚度d21'(参见图1)稍微减小，例如减小大约0.1毫米。但减小的厚度始终还可以是例如至少0.4毫米、至少0.9毫米，或者至少1.4毫米。
图17示出根据图16的整个装置的俯视图，该装置具有在整个填料4中(所述填料包括填料4a和4b)暴露的上平衡片21和由整个填料4覆盖的并且因此用虚线示出的控制电极布线结构70。
如此外示出的那样，连接点701可嵌入到全部填料4中。在所述情况下填料4可以局部地被开口，以便能够实现连接点701的电接触。例如这又可以借助激光束、掩膜蚀刻、通过连接点701的旋入来接触的连接螺栓或通过任意其他接触方式实现。对此替代地，连接点701也可以从填料4突出。
图18至20示出上述方法的改型。唯一的区别在于，无接触件23应用在控制电极13上，从而控制电极13自身是接触件23，所述控制电极在填料4a的局部开口之后暴露并且因此可以直接被电接触。否则，图18至20示出的步骤相应于图9、10或16。借助填料4相互材料锁合地连接的半导体芯片1、在其与半导体芯片1背离的一侧上暴露的上平衡片21、填料4以及控制电极布线结构70又是复合结构6的组成部分。
如此外在图21中示出的那样，控制电极布线结构70可以具有一个或多个预制的元件，例如一个或多个预制的电路板76，其中的每一个具有介电的绝缘载体74和电路板金属化部71。
作为介电的绝缘载体74例如可以使用陶瓷，如氧化铝、氮化铝或其他陶瓷，但也可以使用非陶瓷材料，如例如玻璃或FR4。在由氧化铝制成的介电的绝缘载体74的情况下，电路板76可以构造为DCB衬底(DCB＝“direct copper bonding：直接键合铜”)，其中，电路板金属化部71由铜组成并且与氧化铝绝缘载体74直接连接。电路板76的介电的绝缘载体74(陶瓷、玻璃、塑料)可以在两侧或者——如所示——仅仅在一侧金属化。用于预制元件的另外的例子是：单侧或两侧导电的金属化半导体衬底；单侧或双侧导电的金属化功能半导体芯片；单侧或双侧导电的金属化玻璃衬底；单侧或双侧导电的金属化陶瓷衬底。
控制电极布线结构70连同一个或多个预制的电路板76又可以完全布置在自由空间211中。在此，电路板金属化部71可以分别位于绝缘载体74的与半导体芯片1背离的一侧上，从而电路板金属化部71从上方可自由进入。电路板76可以可选地借助导电的或电绝缘的粘接剂75固定在填料4a和/或半导体芯片1上。
如此外在图22中示出的那样，可以应用键合引线72，键合引线分别在第一键合位置上直接键合到暴露的控制电极13上，或者，只要应用接触件32(未示出)，就直接键合在暴露的接触件23上；以及在第二键合位置上直接键合到所述电路板金属化部71上或所述电路板金属化部71中的一个上。通常，键合引线72也形成控制电极布线结构70的组成部分。
如此外在图23中所示的那样，结果，这样的控制电极布线结构70也可以被嵌入到另一填料4b中并且随后所述装置被磨削，从而上平衡片21在其与所属半导体芯片1背离的一侧上暴露并且可以电接触。借助填料4相互材料锁合地连接的半导体芯片1、在其与半导体芯片1背离的一侧上暴露的上平衡片21、填料4以及控制电极布线结构70又是复合结构6的组成部分。
根据图21至23阐述的例子的改型在图24和25中示出。与图21至23的例子不同，在借助填料4a和/或4b使半导体芯片1相互材料锁合地连接之前实现控制电极布线结构70在自由空间211中的装配。控制电极布线结构70因此借助粘接剂75粘接到半导体芯片1上(图24)。仅仅此后才使所述装置设有填料4a(所述填料可以构成全部填料4)，该填料在硬化之后材料锁合地连接半导体芯片1并且此外包围控制电极布线结构70，从而控制电极布线结构70嵌入到填料4a或4中。在嵌入之后又可以磨削所述装置，从而上平衡片21在其与所属的半导体芯片1背离的一侧上暴露并且可以被电接触。在此，借助填料4相互材料锁合地连接的半导体芯片1、在其与半导体芯片1背离的一侧上暴露的上平衡片21、填料4以及控制电极布线结构70也是复合结构6的组成部分。
如根据按照图26的与图24对应的俯视图可见的那样，控制电极布线结构70可以具有两个或更多个电路板，所述两个或更多个电路板分别具有介电的绝缘载体74和电路板金属化部71。键合引线72然后紧接着可以分别键合到控制连接端13之一上和电路板金属化部71之一上。
可选地，另外的键合引线72可以用于相互电连接不同电路板的电路板金属化部71。此外，所述电路板之一的电路板金属化部71可以用作连接点701。
其改型在图28和29中示出。在此，控制电极布线结构70具有仅仅一个唯一的电路板，该电路板具有介电的绝缘载体74和电路板金属化部71。图28示出在电路板76粘接之后的装置。随后，将键合引线72分别键合到控制连接端13之一上和电路板金属化部71上，这作为结果在图29中示出。
如在其他变型中那样，所述装置也可以在根据图24至27的例子中或者在根据图28和29的例子中在控制电极13借助控制电极布线结构70电连接之后设有填料4，所述填料将半导体芯片1相互材料锁合地连接。
替代地也可能的是，半导体芯片1已经在借助控制电极布线结构70电连接控制电极13之前设有填料4a——该填料将半导体芯片1相互材料锁合地连接——并且随后设有另一填料4b，该另一填料也包围并且嵌入控制电极布线结构70。
相应的也适用于另外的根据图30和31示出的改型，其中，一个或多个电路板76在相邻的半导体芯片1之间布置在自由空间211中。如所示的那样，一个或多个电路板76可以可选地直接借助导电的或电绝缘的粘接剂75粘接到下平衡片22上。此外，键合引线72的电布线可以如上根据图22至29阐述那样实现。整个控制电极布线结构70并且因此键合引线72又可以完全布置在自由空间211中并且嵌入到填料4中。
在控制电极13电连接之后，可以使所述装置设有填料4a(该填料可以形成全部填料4或者其中的仅仅一部分)，填料在硬化之后材料锁合地连接半导体芯片1并且此外包围控制电极布线结构70，从而控制电极布线结构70嵌入到填料4a或4中。在嵌入之后又可以磨削所述装置，从而上平衡片21在其与所属的半导体芯片1背离的一侧上暴露并且可以被电接触，这作为结果在图31中示出。借助填料4相互材料锁合地连接的半导体芯片1、在其与半导体芯片1背离的一侧上暴露的上平衡片21、填料4以及控制电极布线结构70是复合结构6的组成部分。
关于图23、25和31应指出，在此，键合引线72的表示以如此程度简化，使得键合引线——除其横剖面以外——实际上必须由填料4覆盖。虽然如此，选择所述表示，以便更好地阐述借助键合引线32实现的电连接。
如上阐述的那样，可以在键合引线72的应用中使用键合支承点元件，所述键合支承点元件在所示出的例子中构造为电路板76。然而对于电路板76代替地或附加地，键合支承点元件作为控制电极布线结构70的组成部分也可以具有任意其他的结构，只要至少两个键合引线72可以在分别至少一个键合点上键合到键合支承点元件上。键合支承点元件例如可以构造为预制的金属片。
同样可能的是，使用一个或多个功能芯片作为键合支承点元件。这样的功能芯片可以包含例如二极管和/或欧姆电阻，它们集成到用于控制控制电极13的信号路径中并且由此前置于控制电极13。也可能的是，应用电阻构件，所述电阻构件例如构造为(例如构造在HTTC衬底上的；HTTC＝High Temperature Coflred Ceramics：高温烧结玻璃陶瓷)芯片电阻或SMD电阻或膏印刷的电阻。此外可以应用任意的SMD构件，例如欧姆SMD电阻、SMD二极管或者一般的有源和/或无源的SMD构件。
特别地，一个或多个电阻构件的应用能够实现：前置各个控制电极——只要这是需要的或所期望的——、串联电阻(例如栅极串联电阻)，以便将集成到半导体芯片1中的半导体构件的开关性能匹配于如下要求，即所述要求例如可以通过确定的应用产生。
键合支承点元件也可以补充地用于确保：提供给全部控制电极13的电控制信号也同时并且以相同信号强度(例如相同电压水平)到达控制电极13，这可以通过控制电极布线结构70的相应设计而发生。
键合引线72连同一个或多个键合支承点元件的应用具有如下优点：每个控制电极13或施加到所述控制电极上的接触件32可以直接借助键合引线72来连接。键合引线72的应用相比于如下情况简单得多并且结果更可靠，即当例如预制的经结构化的板分别借助经烧结的连接与全部控制电极13或接触件23连接时。
在使用具有两个或更多个(可选地相同的)半导体芯片1的复合结构6——其中上平衡片21的与半导体芯片1背离的一侧暴露——的情况下，现在可以制造如结果在图33中示出的那样的半导体装置。图32示出根据33的已制成的半导体装置的分解图。如由图32和33得知，也称为“紧压包装单元”的半导体装置包括壳体，所述壳体具有导电的上接触板41、导电的下接触板42以及介电的间隔环50。复合结构6布置在上接触板41与下接触板42之间。上接触板41用于：从芯片组件2中的每一个电接触和机械接触朝向上接触板41的上平衡片21。相应地，下接触板42用于电接触和机械接触下平衡片22。在此，电接触分别可以是纯压力接触，所述压力接触至少当接触板41和42通过足够大的外挤压力相对挤压时产生。
作为用于上接触件41和/或下接触件42的材料例如铜或铜合金适用。可选地，上接触件41和/或下接触件42可以设有薄镍层。然而原则上也可以应用任意其他的导电材料、尤其金属或金属合金，例如铝或铝合金或铜合金。
间隔环50——其布置在接触板41与42之间并且环形包围复合结构5——由介电材料组成，例如由陶瓷组成，以便将接触板41与42相互电绝缘。如也在本发明的所有其他构型中的那样，间隔环50可以不仅与上接触板41而且与下接触板42材料锁合地连接，例如通过焊接、粘接或烧结。
如在图32和33中还示出的那样，可以可选地施加薄的导电的连接层80到以下复合结构6上：在所述复合结构中，上平衡片21的与半导体芯片1背离的一侧暴露，所述连接层将上平衡片21相互导电连接。连接层80可以例如以薄层技术实施，其方式是，借助沉积法例如PVD(＝Physical Vapor Depsition：物理气相沉积，例如溅射)、CVD(＝Chemical VaporDeposition：化学气相沉积)或电镀将连接层沉积在复合结构6上。连接层80可以具有例如钌或者由钌组成，和/或连接层80可以例如具有铝或由铝组成。连接层80此外在所阐述的压力接触的情况下完成润滑剂的功能，以便减小在压力接触时通常产生的机械应力并且因此在复合结构6中避免裂缝形成。
在根据图33的例子中，如果以足够挤压力使接触板41和42相对挤压，则上接触板41与连接层80可以形成电的纯压力接触。
图34示出根据图33和34的装置根据放大的区段仅仅示例性地根据在图16中示出的复合结构6在其装入到壳体中之后的改型，所述壳体具有上和下接触板41、42以及如上所述的介电的间隔环50。对于半导体芯片1中的每一个，上接触板41在其朝向复合结构6的一侧上具有自身的接触突出部411，如果以足够挤压力使接触板41和42相对挤压，则所述接触突出部在上平衡片21之一的与所涉及的半导体芯片1背离的一侧上压力接触所述上平衡片21。具有这样的接触突出部411的接触板41尤其可以用于所有如下复合结构6中：在所述复合结构中如果上平衡片21还没有或者没有完全由连接层80覆盖，则所述上平衡片21可自由进入。然而也可能的是，应用具有接触突出部411的接触板41结合复合结构6，在所述复合结构中，连接上平衡片21的连接层80覆盖上平衡片21。在这样的情况下，如果以足够挤压力使接触板41和42相对挤压，则在连接层80与接触突出部中的每一个之间构造(纯)压力接触。
如根据上述实施例所示的那样，控制电极布线结构70可以嵌入到填料4中并且埋入在其中。在此，控制电极布线结构70可以在其与半导体芯片1背离的一侧上由填料4的一个区段覆盖。
以上根据不同例子阐述如何可以构造或制造芯片复合结构，其中，多个半导体芯片1借助填料4相互材料锁合地连接。半导体芯片1可以例如分别具有可控的半导体构件，其中，在第一主电极11与第二主电极12之间构造电负载段，其中，通过电负载段的电流可以被控制、接通或关断，其方式是，施加控制信号(例如电控制电位)到控制电极13上。通过这种方式，并联连接的半导体芯片1或者在其中包含的并联连接的半导体构件可以同步和相位相同地连接。原则上，全部半导体芯片1可以相同地构造，但也可以应用不同构造的半导体芯片1。
适合的可控的半导体构件例如是具有电绝缘的栅极的场效应晶体管——例如MOSFET(MOSFET＝Metal Oxid Semiconductor Field Effect Transistor：金属氧化物半导体场效应晶体管)或者IGBT(IGBT＝Insulated Gate Bipolar Transistor：绝缘栅双极型晶体管)。在该情况下，栅极电极是控制电极13。在MOSFET的情况下，源极电极是第一主电极11，漏极电极是第二主电极12，并且在IGBT的情况下，发射极电极是第一主电极11而集电极电极是第二主电极12。
如此外在图35中所示的那样，可以将具有如上阐述的复合结构6的紧压包装单元如此压入在导电的上压力接触件81与导电的下压力接触件82之间，使得在上压力接触件81与上接触板41之间以及在下压力接触件82与下接触板42之间分别存在电的压力接触连接。
压力接触连接可以可选地为纯压力接触连接。随后可以将具有紧压包装单元、上压力接触件81和下压力接触件82的已制成的压力接触装置8电连接。例如，压力接触装置8可以与欧姆负载和/或感应式负载500(例如电动机)串联地连接在正供电电位V+与负供电电位V-之间。

Claims (19)

1.一种用于制造芯片复合结构的方法，所述方法具有：
分别通过使导电的第一平衡片(21)与半导体芯片(1)的第一主电极(11)材料锁合地且导电地连接来制造两个或更多个芯片组件(2)；
在所述芯片组件(2)之间的自由空间(211)中布置控制电极布线结构(70)；
在所述控制电极布线结构(70)与各个芯片组件(2)的半导体芯片(1)的控制电极(13)之间建立导电连接；
借助介电填料(4)使所述芯片组件(2)材料锁合地连接。
2.根据权利要求1所述的方法，其中，
借助所述填料(4)的第一部分(4a)使所述半导体芯片(1)相互材料锁合地连接，从而所述第一部分(4a)覆盖所述控制电极(13)；
在所述第一部分(4a)中分别在所述控制电极(13)的区域中产生开口，从而所述控制电极(13)在所述相应的开口中暴露；以及
借助所述控制电极布线结构(70)使所述控制电极(13)穿过所述开口地相互导电连接。
3.根据权利要求2所述的方法，其中，借助导电粘接剂(75)使所述控制电极布线结构(70)与所述控制电极(13)导电连接。
4.根据权利要求2或3所述的方法，其中，为了所述开口，借助以下中的至少一个局部地除去所述第一部分(4a)：激光束(401)；蚀刻剂(402)。
5.根据权利要求2至4中任一项所述的方法，其中，
使所述控制电极(13)直接在所述第一部分(4a)开口之后暴露；或者
在所述半导体芯片(1)的每一个中，使其控制电极(13)在所述控制电极的与所述半导体芯片(1)的半导体本体(10)背离的一侧上与导电接触件(23)材料锁合地以及导电地连接，其中，所述接触件(23)直接在所述第一部分(4a)开口之后暴露。
6.根据权利要求2至5中任一项所述的方法，其中，所述第一部分(4a)是酰亚胺或模制材料。
7.根据权利要求2至6中任一项所述的方法，其中，在借助所述控制电极布线结构(70)使所述控制电极(13)相互导电连接之后，将所述控制电极布线结构(70)嵌入到所述填料(4)的第二部分(4b)中并且在此由所述第二部分(4b)覆盖所述控制电极布线结构。
8.根据权利要求2至7中任一项所述的方法，其中，所述第二部分(4b)是模制材料。
9.根据权利要求1所述的方法，其中，所述控制电极布线结构(70)具有多个键合引线(72)以及一个或多个键合支承点元件(76)，其中，至少一个键合支承点元件(76)布置在所述芯片组件(2)之间的自由空间(211)中；以及使所述控制电极(13)中的每一个借助所述键合引线(72)之一与一个键合支承点元件(76)导电连接。
10.根据以上权利要求中任一项所述的方法，其中，
所述控制电极布线结构(70)具有第一键合引线(72)、第二键合引线(72)和键合支承点元件(76)；
所述第一键合引线(72)、所述键合支承点元件(76)和所述第二键合引线(72)串联电连接在所述控制电极(13)中的第一控制电极与所述控制电极(13)中的第二控制电极之间并且将所述控制电极(13)中的第一和第二控制电极相互导电连接；
使所述第一键合引线(72)和所述第二键合引线(72)分别直接键合到所述键合支承点元件(76)上。
11.根据权利要求10所述的方法，其中，
使所述第一键合引线(72)直接键合到所述控制电极(13)中的所述第一控制电极上或者直接键合到第一接触件(23)上，所述第一接触件布置在所述控制电极(13)中的所述第一控制电极的与所属的半导体本体(10)背离的一侧上并且与所述侧导电连接；
使所述第二键合引线(72)直接键合到所述控制电极(13)中的所述第二控制电极上或者直接键合到第二接触件(23)上，所述第二接触件布置在所述控制电极(13)中的所述第二控制电极的与所属的半导体本体(10)背离的一侧上并且与所述侧导电连接。
12.根据权利要求9至11中任一项所述的方法，其中，在借助所述介电填料(4)使所述半导体芯片(1)相互材料锁合地连接之前借助所述控制电极布线结构(70)使所述控制电极(13)电连接。
13.根据权利要求9至11中任一项所述的方法，其中，在通过所述介电填料(4)使所述半导体芯片(1)相互材料锁合地连接之后借助所述控制电极布线结构(70)使所述控制电极(13)电连接。
14.根据权利要求13所述的方法，其中，
在借助所述填料(4)使所述半导体芯片(1)相互材料锁合地连接之后由所述填料(4)覆盖所述控制电极(13)；
在借助所述控制电极布线结构(70)使所述控制电极(13)电连接之前，在所述填料(4)中分别在所述控制电极(13)的区域中产生开口，从而所述控制电极(13)在所述相应的开口中暴露；以及
借助所述控制电极布线结构(70)使所述控制电极(13)穿过所述开口地导电连接。
15.根据以上权利要求中任一项所述的方法，其中，所述第一平衡片(21)中的每一个在20℃的温度下具有小于11ppm/K或者小于7ppm/K的线性热膨胀系数。
16.根据以上权利要求中任一项所述的方法，其中，所述半导体芯片(1)中的每一个具有第二主电极(12)，在所述第二主电极上，使所述半导体芯片与导电的第二平衡片(22)材料锁合地且导电地连接。
17.根据以上权利要求中任一项所述的方法，其中，所述第二平衡片(22)中的每一个在20℃的温度下具有小于11ppm/K或者小于7ppm/K的线性热膨胀系数。
18.根据以上权利要求中任一项所述的方法，其中，所述控制电极布线结构(70)具有元件(76)，首先预制所述元件并且随后将所述元件布置在所述自由空间(211)中并且随后将所述元件与至少一个控制电极(13)导电连接。
19.根据权利要求18所述的方法，其中，将所述预制的元件构造为金属板；或
电路板；或
单侧或双侧导电地金属化的半导体衬底；或
单侧或双侧导电地金属化的功能半导体芯片；或
单侧或双侧导电地金属化的玻璃衬底；或
单侧或双侧导电地金属化的陶瓷衬底。
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