CN106252336A - 半导体装置、半导体***以及形成半导体装置的方法 - Google Patents

半导体装置、半导体***以及形成半导体装置的方法 Download PDF

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Publication number
CN106252336A
CN106252336A CN201610404516.1A CN201610404516A CN106252336A CN 106252336 A CN106252336 A CN 106252336A CN 201610404516 A CN201610404516 A CN 201610404516A CN 106252336 A CN106252336 A CN 106252336A
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semiconductor device
conductive plate
semiconductor
power semiconductor
encapsulating material
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CN106252336B (zh
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E·菲尔古特
J·赫格尔
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及半导体装置、半导体***以及形成半导体装置的方法。提供了一种半导体装置。该半导体装置可以包括：具有表面的导电板；多个功率半导体器件，其布置在导电板的表面上，其中，该多个功率半导体器件中的每个功率半导体器件的第一受控端均可以电耦合至导电板；多个导电块，其中，每个导电块与该多个功率半导体器件中的每个功率半导体器件的相应的第二受控端电耦合；以及封装材料，其封装该多个功率半导体器件，其中，导电板的表面的至少一个边缘区域可以未被封装材料所封装。

Description

半导体装置、半导体***以及形成半导体装置的方法
技术领域
概括地说，各个实施例涉及半导体装置、半导体***以及形成半导体装置的方法。
背景技术
常规的半导体装置(例如包括多个功率半导体器件(例如压接式封装阵列)的装置)可以通过至少部分地封装该多个功率半导体器件和导电板来形成，这可以形成常见的端子，例如，常见的受控端(例如在例如电介质封装材料中的常见的集电极接点)。该封装可以被布置为从五个面来包围该导电板，即在可以在其上布置有功率半导体器件的顶面上，以及在与顶面接触的侧面上。该导电板的底面可以未被封装材料所封装或至少部分地未被封装材料所封装。
这就是说可以创建可对外部环境开放的位于导电板与封装材料之间的界面。通过该界面，对半导体装置可能有害的湿气或其它物质会进入该半导体装置并到达功率半导体器件，从而损坏该半导体装置。
此外，该半导体装置可以为了其操作而被握持在握持装置中。在该握持装置附接到该半导体装置的面的情况下，它可能需要附接到该封装材料，这样可能表现出了该半导体装置的薄弱点。
发明内容
根据本发明的一个实施例，提供了一种半导体装置。所述半导体装置可以包括：具有表面的导电板；多个功率半导体器件，其布置在所述导电板的所述表面上，其中，所述多个功率半导体器件中的每个功率半导体器件的第一受控端均电耦合至所述导电板；多个导电块，每个导电块与所述多个功率半导体器件中的每个功率半导体器件的相应的第二受控端电耦合；以及封装材料，其封装所述多个功率半导体器件，其中，所述导电板的所述表面的至少一个边缘区域未被所述封装材料所封装。
根据本发明的一种有利的实施方式，所述半导体装置的与所述导电板相反的顶面的至少一部分与所述多个功率半导体器件中的每个功率半导体器件的所述相应的第二受控端电耦合。
根据本发明的一种有利的实施方式，所述半导体装置被配置为具有在所述顶面的所述至少一部分与所述导电板之间流动的电流。
根据本发明的一种有利的实施方式，所述半导体装置还包括：至少一个控制端，其用于控制所述多个功率半导体器件中的至少一个功率半导体器件的所述第一受控端与第二受控端之间的电流。
根据本发明的一种有利的实施方式，所述半导体装置还包括密封结构。
根据本发明的一种有利的实施方式，所述密封结构包括密封元件。
根据本发明的一种有利的实施方式，所述密封元件是密封环。
根据本发明的一种有利的实施方式，所述密封元件布置在所述导电板的所述表面的所述至少一个边缘区域上。
根据本发明的一种有利的实施方式，所述密封元件嵌入在所述封装材料中。
根据本发明的一种有利的实施方式，所述封装材料具有密封性。
根据本发明的一种有利的实施方式，所述半导体装置还包括布置在所述多个导电块上方和所述封装材料上方的导电层。
根据本发明的一种有利的实施方式，所述导电层、所述密封结构以及所述导电板被布置为形成所述多个半导体器件的气密性密封的至少一部分。
根据本发明的一种有利的实施方式，所述多个功率半导体器件包括多个IGBT。
根据本发明的一种有利的实施方式，所述多个功率半导体器件包括至少一个功率二极管。
根据本发明的一种有利的实施方式，所述导电板还包括与所述表面相反的第二表面以及连接所述表面和所述第二表面的侧面，并且所述第二表面和所述侧面未被所述封装材料所封装。
根据本发明的一种有利的实施方式，所述导电板和/或所述多个导电块包括以下导电材料组中的至少一种导电材料：钼；铜；以及碳。
根据本发明的一种有利的实施方式，所述半导体装置的所述顶面的所述至少一部分与所述导电板之间的连接面包括：增加所述半导体装置的所述顶面的所述至少一部分与所述导电板之间的表面距离的结构。
根据本发明的一个实施例，提供了一种半导体***，其包括上述半导体装置。
根据本发明的一个实施例，提供了一种形成半导体装置的方法，所述方法包括：将多个功率半导体器件布置在导电板的表面上；将所述多个功率半导体器件中的每个功率半导体器件的第一受控端电耦合至所述导电板；将多个导电块中的每个导电块与所述多个功率半导体器件中的每个功率半导体器件的相应的第二受控端相电耦合；以及利用封装材料对所述多个功率半导体器件进行封装，以使得所述导电板的所述表面的至少一个边缘区域未被所述封装材料所封装。
根据本发明的一种有利的实施方式，所述封装包括模制。
根据本发明的一种有利的实施方式，所述模制包括传送模制和压缩模制中的一种。
根据本发明的一种有利的实施方式，在所述传送模制期间，所述多个导电块中的每一个导电块的背向所述多个功率半导体器件中的相应的功率半导体器件的表面保持未被所述封装材料所封装。
根据本发明的一种有利的实施方式，还包括：将密封元件布置在所述至少一个边缘区域上。
根据本发明的一种有利的实施方式，所述密封元件是密封环。
根据本发明的一种有利的实施方式，还包括：将导电层布置在所述多个导电块上方和所述封装材料上方。
根据本发明的一种有利的实施方式，还包括：通过在所述导电层与所述密封环之间形成气密性密封连接并且通过将所述密封环压至所述至少一个边缘区域上来形成用于所述多个功率半导体器件的气密性密封。
附图说明
在附图中，相同的附图标记通常遍及不同的视图指代相同的部件。附图不必按比例绘制，相反的，重点通常放在说明本发明的原理。在以下的描述中，本发明的各个实施例将参考以下附图来进行描述，在附图中：
图1A至图1C示出了根据各个实施例的半导体装置，在图1B中示出了横截面图，并且在图1A和图1C中分别示出了半导体装置或其部分的透视图；
图2A至图2H示出了根据各个实施例的在其不同的制造阶段阶段期间的半导体装置，图2A至图2C示出了透视图，图2D至图2H示出了横截面图；
图3A和图3B示出了根据各个实施例的在其不同的制造阶段期间的半导体装置的透视图；
图4A至图4E示出了根据各个实施例的具有密封结构的半导体装置的透视图(图4A)以及横截面图(图4B至图4E)；
图5示出了根据各个实施例的半导体***，示出了顶部的分解图和底部的透视图；
图6示出了根据各个实施例的、描绘形成半导体装置的方法的图；以及
图7示出了根据各个实施例的、描绘形成半导体装置的方法的图。
具体实施方式
以下的详细描述引用附图，附图通过举例说明的方式示出了具体的细节和可以在其中实施本发明的实施例。
词语“示例性”在本文中用来表示“用作示例，实例或说明”。本文描述为“示例性”的任意实施例或设计不必被解释为比其它实施例或设计优选或具优势。
关于沉积材料形成在侧面或表面“上方”所使用的词语“上方”在本文中可以用来表示该沉积材料可以“直接形成在”所暗指的侧面或表面“上”，例如与所指的侧面或表面直接接触。关于沉积材料形成在侧面或表面“上方”所使用的词语“上方”在本文中可以用来表示该沉积材料可以“非直接形成在”所暗指的侧面或表面“上”，其中一个或多个额外的层布置在所暗指的侧面或表面与该沉积材料之间。
词语“环”应当被理解为是指以环状方式自身闭合的结构，但不必是圆形的(即包围圆形区域)或者是平面的。换句话说，该环可以包围任意形状的区域，例如圆形的、椭圆形的或多边形的(例如矩形的)的区域(其在空间中可以是平面的或弯曲的)。
本发明提供了装置的各个方面，并且本发明还提供了方法的各个方面。应当理解，装置的基本属性也适用于方法，反之亦然。因此，为了简洁起见，可以省略对这些属性的重复描述。
在各个实施例中，一种半导体装置可以包括多个功率半导体器件、多个导电块以及导电板。每个功率半导体器件均可以包括具有上侧和与该上侧相对的下侧的半导体主体、布置在下侧上的第一受控端以及布置在上侧上的第二受控端。此外，功率半导体器件可以包括控制端，该控制端可以布置在上侧并且借助于该第一受控端，可以控制该第一受控端和第二受控端之间的电流。
在此意义上的受控端应当被理解为表示端子，也称为电极，在电极之间，负载电流可以在半导体芯片的工作期间中流过半导体主体。
在各个实施例中，功率半导体器件彼此间可以通过封装材料(例如电介质封装材料)被材料接合，以形成固体复合物，其中，功率半导体器件和封装材料都可以是复合物的组成部分。这里，至于各功率半导体器件，相关的芯片组件的第一受控端的、第二受控端的侧面以及控制端的侧面分别可以不或至少不完全地被封装材料覆盖，该侧面背向该半导体主体。
在各个实施例中，上述问题可以通过对封装材料以如下方式进行布置来解决，即导电板的表面的至少一个边缘区域是未被封装材料所封装的。例如，导电板的边缘在表面上可以保持未被封装材料所封装，在该表面上可以布置多个功率半导体器件。
以这种方式，在各个实施例中，导电板可以在它的平面上突出超过封装材料。夹持装置可以附接到导电板的突出超过封装材料的部分。换句话说，夹持装置可以利用导电板，例如只利用导电板，来握持半导体装置，从而提供了附接至半导体装置的一部分(该部分可能不表现半导体装置的薄弱点)。
此外，在各个实施例中，密封结构可以布置在导电板的表面的至少一个边缘区域中。从而，封装材料和导电板之间的路径可以与外部密封隔离，该导电板连接外部与多个功率半导体器件。结合在封装材料和将外部与多个功率半导体器件连接的多个导电块(例如，导电层，例如布置在多个导电块上以及在封装材料上的金属层)之间的路径的密封，在各个实施例中可以提供多个功率半导体器件的气密性密封。
在各个实施例中，在导电板上的多个功率半导体器件的布置可以是这样的：使得可以省略将半导体装置(例如，通过锯切)分隔为更小的单元，从而节省了加工时间。
图1A至图1C示出了根据各个实施例的半导体装置19，图1B示出了横截面图，并且图1A、图1C分别示出了半导体装置19或其部分的透视图。
在各个实施例中，半导体装置19可以包括多个半导体器件10。半导体器件10中的每一个半导体器件均可以包括半导体主体。该半导体主体可以包括基础的半导体材料，其包含p导通和n导通半导体区以便实现集成在该半导体主体中的功率半导体元件。此外，该半导体芯片还可以根据需要具有多个电介质层、以及导电层，该导电层譬如是例如金属化物，或是由掺杂的多晶半导体材料构成的层(例如，多晶硅、硅化物层，或任意的电介质层，譬如是，例如氮化物层(例如氮化硅)或氧化物层(例如氧化硅)，或钝化层(例如酰亚胺层)。
基础的半导体材料可以是通常用于生产半导体元件的任何已知的基础半导体材料，例如任意元素半导体(例如硅、锗)、任意化合物半导体(例如硅上的氮化镓、II-VI族半导体(例如硒化锌或硫化镉)、III-V族半导体(例如磷化镓、砷化镓、磷化铟、锑化铟)或Ⅳ-Ⅳ族半导体，如碳化硅或硅锗)。
导电层的至少一部分可以形成为端子。功率半导体器件10中的每一个均可以包括布置在底侧的第一受控端，以及设置在顶侧的第二受控端。
功率半导体器件10可以包括例如二极管、或MOSFET、IGBT、IGFET(通常为此)、双极晶体管、晶闸管、或任何其它可控功率半导体元件。第一和第二受控端通常可以是任意的功率半导体器件的阴极和阳极、阳极和阴极、源极和漏极、源极和漏极、集电极和发射极或发射极和集电极。
如果功率半导体器件10是一个可控功率半导体器件10，也就是说功率半导体器件10具有诸如例如栅极端(例如MOSFET、IGBT、IGFET、晶闸管)或基极端(例如双极晶体管(不含IGBT))之类的控制端，则控制端可以额外地存在，其可以在位于顶侧，并且借助于该控制端，第一受控端和第二受控端之间的电流可以被控制。
在各个实施例中，多个功率半导体器件10可以包括仅一种类型的半导体器件，例如仅为IGBT或仅为MOSFET，例如在各个半导体器件10之间具有相同属性或变化的属性。
在各个实施例中，多个半导体器件10可以包括一种以上类型的半导体器件，例如IGBT和MOSFET的组合、上述半导体器件10中的任何半导体器件10的组合等。
在各个实施例中，多个导电块12可以位于背向该半导体主体的第二受控端中的每一个控制端的一侧上(即如图1B中示出的半导体器件10之上)，并且可以通过顶部连接层(未示出)来材料接合到相应的第二受控端。
在各个实施例中，多个导电块12中的每个导电块12可以例如使用拾取－放置工艺来被单独地放置在相应的功率半导体器件10上。
在各个实施例中，多个导电块12可以相互连接，例如连接为与多个功率半导体器件10的布置相匹配的阵列，并且多个导电块12可以被联合地放置在多个功率半导体器件10上(例如在共同的工艺中)。
在各个实施例中，可以例如通过单独地对一个或多个导电块12进行布置以及联合地对多个导电块12进行布置，来使用将多个导电块12放置在多个功率半导体器件上的两种方法的混合。
在各个实施例中，具有表面14t(其也可以称为顶面14t)、与表面14t相反的第二表面14b(其也可以称为底面14b)以及连接表面14t和第二表面14b的侧面14s的(单个)导电板14可以位于第一受控端的背向多个半导体主体的侧面，即位于如图1B所示的半导体器件10之下，并且可以通过底部连接层(未示出)来材料接合到第一受控端。
在各个实施例中，多个导电片可以可选地布置在控制端上，该导电片可以通过顶部连接层来粘合地并且导电地连接到控制端，其中，可以避免直接电连接或通过导电片与导电块12之间的顶部连接层的快捷连接。如果提供了这样的导电片，邻近的导电块12可以具有切除部12c(图1C)，导电片可以设置在切除部12c中。
导电板14和导电块12可以用于降低机械应力，该机械应力将在该半导体装置19经受由一对接触板(例如，包括铜或由铜构成)导致的压力接触连接时而发生，将在稍后解释(参见图5，接触板74t和74b)。接触板可以具有可以与半导体主体的热膨胀系数有很大不同的热膨胀系数。在不存在导电块12和导电板14时，接触板将分别与非常薄的第一和第二端直接接触。这可能会导致热机械应力(该热机械应力可能引起半导体器件10的电气属性的变化)或甚至导致半导体器件10的损坏。
在各个实施例中，多个导电块12以及导电片(如果存在的话)可以(在分别安装至第二受控端和控制端上之前，并且在安装后直接)具有在垂直方向上相对大的厚度，例如至少20mm、0.5mm、至少1mm或至少2mm，以允许多个导电块12以及该导电片(如果存在的话)接地，如将在稍后解释。在研磨是不必要的情况下，多个导电块12以及导电片(如果存在的话)可以具有较小的厚度(例如，最终厚度)，例如小于20mm、例如1.3mm或小于1.0mm、例如小于20μm。在导电块和/或片包括厚沉积铜或由厚沉积铜构成的情况下，该厚沉积铜的厚度可以是在从约5μm至约100μm的范围中(例如，从约10μm至约20μm)。在各个实施例中，每个导电块12可以由导电材料块(例如，金属块和厚沉积铜)构成。
在各个实施例中，每一个导电块12在水平方向(即垂直于其厚度的方向)上的尺寸可以是每个功率半导体器件10的水平尺寸的量级。如例如图2A所示，每个导电块12可以例如小于(例如略小于)与其连接的功率半导体器件10。在各个实施例中，每个导电块12可以具有大约与和其连接的功率半导体元件10相同的尺寸，或者导电块12可以是更大的。在各个实施例中，在水平方向上的尺寸(例如，最大尺寸)可以是在从约250μm至约30mm的范围中(例如约9.2mm)。
在各个实施例中，每个导电块12的顶面12t(见图2E)可以是非常平坦的。例如，顶面12t上没有点可以与理想平面偏离超过约10μm(例如其偏离小于8μm)。与每个导电块12的顶面12t相反的表面可以是类似地平坦的。此外，顶面12t和相反的表面彼此可以非常平行。在各个实施例中，两个表面之间的角度差可以足够小，以使得由该角度差所引起的在每个导电块12的各个位置处的厚度差可以小于约20μm(例如小于约10μm)。
在各个实施例中，多个导电块12的各个导电块12之间的厚度变化可以很小。与多个导电块12的平均厚度间的最大偏差可以例如小于约30μm(例如小于约25μm，例如小于约20μm)。在各个实施例中，可能期望多个导电块12中的各个导电块12之间的厚度变化，例如以补偿多个功率半导体器件10中的各个功率半导体器件10之间的厚度变化。在该情况下，导电块12的个体厚度(和各个功率半导体器件10的个体厚度，如果适用的话)可以被精确地获知，例如，通过确定，例如测量厚度以及根据厚度来排序导电块12(和各个功率半导体器件10，如果适用的话)。
在各个实施例中，导电板14在垂直方向上可以具有相对大的厚度，例如至少0.2mm、至少1mm或至少1.5mm。在导电板包括厚沉积铜或由厚沉积铜构成的情况下，厚沉积铜的厚度可以是在约从5μm至约100μm的范围中(例如从约10μm至约20μm)。
在各个实施例中，导电板14在水平方向(即垂直于其厚度的方向)上的尺寸可以比每个功率半导体器件10的水平尺寸的两倍更大，以使得多个功率半导体器件10可以被安装在导电板14上，该导电板14彼此相邻并且它们之间具有最小水平宽度W1(用来彼此电绝缘)。在各个实施例中，多个功率半导体器件10可以被布置成m×n的功率半导体器件10阵列，例如2×2的功率半导体器件10阵列、3×3的功率半导体器件10阵列，4×4功率半导体器件10的阵列或甚至更多。m和n可以是相同或不同的数字。在该情况下，导电板14可以分别大于功率半导体器件10的在平行于该阵列的行和列的方向的上水平尺寸的3倍或4倍。导电板14的水平尺寸可以例如是在从约0.5mm至约500mm的范围中(例如，从约10mm至约100mm，例如约65mm)。在其它实施例中，多个功率半导体器件10的布置可以具有任何形状和任何数目的功率半导体器件10，并且导电板14可以具有相应的形状和尺寸，即具有一个任意的(但适当的)形状的区域，该区域可以是例如多边形的、例如正方形或矩形区域、圆形或椭圆形的。
在各个实施例中，导电板14的表面14t可以是非常平坦的。例如，表面14t上没有点可以与理想平面偏离超过约10μm(例如其偏离小于8μm)。与导电板14的表面14t相反的第二表面14b可以是类似地平坦的。此外，表面14t和相反的表面14b彼此可以非常平行。在各个实施例中，两个表面之间的角度差可以足够小，以使得由该角度差所引起的在导电板14的各个位置处的厚度差可以是小于约30μm(例如小于约20μm，例如小于约10μm)。
每个导电块12在水平方向上可以具有任意的形状。在各个实施例中，其可以是多边形，例如矩形、正方形、具有圆角和切除部(如在图2A和图2B中示出的示例性的实施例)的基本上正方形、圆形、椭圆形或任何其它适当的形状。
在各个实施例中，多个导电块12和/或导电板14可以具有与该半导体主体的线性热膨胀系数尽可能接近的线性热膨胀系数，以便实现其线性热膨胀系数与半导体主体的低的线性热膨胀系数的相适应。举例而言，多个导电块12和/或导电板14在20℃的温度下可以具有小于11ppm/K或者甚至小于7ppm/K的线性热膨胀系数。在该情况下，多个导电块12和/或导电板14可以例如由以下材料中的一种构成或包括以下结构中的一种：钼；金属基复合材料(MMC)，例如AlSiC(铝碳化硅)；包括两个或更多个金属层的多层材料，例如具有层序列铜-钼-铜(Cu-Mo-Cu)的三层材料，例如，具有层厚度比例为1:4:1，这产生了Cu-Mo-Cu三层材料的大约为7.3ppm/K的膨胀系数。
在各个实施例中，多个导电块12和/或导电板14可以具有与第一受控端和第二受控端的线性热膨胀系数相同的线性热膨胀系数，例如多个导电块12和/或导电板14可以由与第一受控端和第二受控端相同的材料构成，例如铜。
通常，在各个实施例中，导电板14和/或多个导电块12可以包括以下各项或由以下各项构成：纯金属或金属合金(例如钼、铜、厚沉积铜、银、铝、金、铜-钼合金、铜-银合金、铜-锌合金，或铜-锡合金)，或金属和/或金属合金的组合(例如，如上所述的三层材料或涂覆有不同金属或金属合金的金属或金属合金(例如涂覆有钌和银的钼))的分层布置，或者导电板14和/或多个导电块12可以包括复合材料或由复合材料构成，该复合材料包括金属和非金属，其中非金属可以例如是或包括碳同素异形体(例如石墨、石墨烯、金刚石或碳纳米管)或者像例如碳化硅、氮化硅、硼、或氧化铝、氮化铝等的陶瓷。
在各个实施例中，导电板14和/或多个导电块12的材料的电导率可以高于约1×106S/m(例如高于约5×106S/m，例如高于约1×107S/m)。
在各个实施例中，导电板14和/或多个导电块12的材料的热导率可以高于约35W/mK(例如高于约100W/mK，例如高于约400W/mK)。
在各个实施例中，顶部连接层可以例如具体化为任意的焊料层，尤其也可具体化为扩散焊料层(例如，使用铜-锌膏或锡膏的扩散焊料)，具体化为包含烧结金属粉末(例如银粉末、铜粉末或银薄片，其中，银可以具有约61×106S/m的电导率和约430W/mK的热导率，而铜可以具有约58×106S/M的电导率和约400W/mK的热导率)的烧结层，或导电粘合剂层。独立地，底部连接层也可以具体化为任意的焊料层，尤其也可具体化为扩散焊料层，具体化为包含烧结金属粉末(如银粉末或银薄片)的烧结层，或导电粘合剂层。顶部连接层和底部连接层可以由相同的材料构成。可替代地，用于该两层的提及的材料的任意组合可以分别用于顶部连接层和底部连接层。
在各个实施例中，为了生成这些连接，可以例如通过丝网或模板印刷来向第一受控端和/或第二受控端和/或向导电板14和/或向多个导电块12施加用于形成顶部连接层和底部连接层(也被称为连接层)的基本材料(例如焊膏、扩散焊料、粘合剂膏或烧结材料)，或者可以以分别在多个导电块12与第二受控端之间以及在导电板14与第一受控端之间的预制焊料薄层(“预成型焊料”)的形式引入用于形成连接层的基本材料。在任意情况下，用于生成这些连接的焊膏或焊料薄层熔化并随后冷却，以使得在每种情况下，分别在多个导电块12与第二受控端之间以及在导电板14与第一受控端之间产生粘着连接。
在连接层包括烧结层或由烧结层构成的情况下，基本材料可以是膏(也被称为烧结膏)，其含有金属粉末(例如银粉末或银薄片)和溶剂。为了生成连接，可以例如通过丝网或模板印刷来例如向第一受控端和/或第二受控端和/或向导电板14和/或向多个导电块12施加烧结膏。形成自该膏的烧结膏层从而可以被布置在第二受控端与多个导电块12之间，并且可以与它们中的每一个进行接触。在连接层具体化为导电粘合剂层的情况下，基本材料可以具体化为导电粘合剂，其中所述层可以是基于该基本材料的。为了生成连接，可以例如通过丝网或模板印刷来例如向第一受控端和/或第二受控端和/或向导电板14和/或向多个导电块12施加粘合剂。形成自该粘合剂的顶部粘合层从而可以被布置在第二受控端与多个导电块12之间并且可以与它们中的每一个进行接触。作为随后的固化的结果，导电顶部连接层可以形成自顶部粘合剂层。与此相对应，形成自粘接剂的底部粘合层可以被布置在第一受控端与导电板14之间，并且可以与导电板14进行接触。作为随后的固化的结果，导电底部连接层可以形成自底部粘合剂层。
如果提供了导电片，则其可以是通过诸如已说明的用于多个导电块12与第二受控端之间的连接的连接技术中的任何连接技术来材料接合至控制端，这独立于被选择用于多个导电块12与第二受控端之间的连接的连接技术。
在各个实施例中，控制端互连结构16可以布置在固体复合物上或布置在固体复合物中，并且可以将功率半导体器件10的控制端彼此导电连接。在各个实施例中，封装材料18可以直接邻接该半导体主体(即半导体主体的半导体材料)，并且是材料接合到半导体主体。
在各个实施例中，封装材料18可以以如下方式来横向并周向以环状的方式包围每个功率半导体器件12：每个导电块12的背向相应的功率半导体器件10的侧面(也视为每个导电块12的上侧，其包括每个导电块12的顶面12t(参见图2E))可以不被封装材料18所覆盖或至少不完全地被封装材料18所覆盖。至少在对半导体装置19进行自顶面12t的一侧的研磨后，多个导电块12中的每个导电块的顶面12t因此可以至少部分地未被封装材料18所封装。半导体装置19的、顶面12t所在的一侧可以被称为半导体装置19的顶侧，并且相反的半导体装置19一侧可以被称为半导体装置19的底侧。
在各个实施例中，控制端互连结构16可以被应用于该复合物，并且可导电地将功率半导体器件的控制端10彼此连接。
在各个实施例中，为了制造半导体装置19，多个功率半导体器件10中的每一个均可以具有半导体主体并且如所说明的可以配备有导电块12并且可选地配备有导电片，然后，多个功率半导体器件10彼此并排地被放置到导电板14上。
在导电板14上的功率半导体器件10的放置可以被实施以使得它们位于相对于彼此预定义的位置上。功率半导体器件10可以使用如上所述的连接层来连接到导电板14，例如，固定在各自的预定义的位置上。
图2A至图2H示出了根据各个实施例的在不同的制造阶段的半导体装置。图2A至图2C示出了透视图，图2D至图2H示出了横截面图。图2A至2H中的半导体装置可以与图1A至图1C中的半导体装置19相同或相似。通过图2A至图2H可以观察到根据各个实施例的形成半导体装置19的方法。
在各个实施例中，如图2A和图2B所示，在所谓的第一附着工艺期间，多个功率半导体器件10可以在导电板14(其也可以被称为底板)的表面14t上被布置在相对于彼此的预定义的位置上。然后，功率半导体器件10(例如芯片或管芯)可以如上所述地使用连接层(例如，如上所述的烧结材料层、烧结膏)来连接(例如烧结、焊接、胶合等等)至导电板14并连接在它们各自预定的位置上，导电板14可以包括钼或如上所述的任何其它导电材料，或由钼或如上所述的任何其它导电材料构成。
在第二附着工艺期间，多个导电块12可以布置在多个功率半导体器件10上，多个导电块12可以包括钼或如上所述的任何其它导电材料，或由钼或如上所述的任何其它导电材料构成。导电块12可以布置在每个多个功率半导体器件10上。然后，导电块12如上所述地连接(例如，烧结、焊接、胶合等等)至半导体器件10。
在各个实施例中，如图2C所示，可以实施可选的所谓的第三附着工艺以布置上述的控制端互连结构16，其也可以称为栅极层。该栅极层可以例如是公共栅极层(该公共栅极层例如可以是以如下方式在封装半导体器件10之前进行布置的掩埋栅极层：该掩埋栅极层可以部分地(例如基本上完全地)掩埋入封装材料18内)或所谓的顶部栅极层(该顶部栅极层可以在封装半导体器件后被布置在封装材料18上)。控制端和顶部栅极层之间的导电连接可以例如通过在控制端与控制端互连结构16之间的封装材料18中形成导电通孔来实现，例如在施加封装材料18之前包含用来形成半导体装置19中的通孔的插针，并且然后去除在该些插针之上的封装材料18，以使得这些插针被暴露以用于导电接触，例如通过将要形成在封装材料18上的控制端互连结构来实现导电接触。多个控制端中的每个控制端可以如上所述地被连接(例如，使用烧结)至多个导电片中的导电片，导电片可以包括布置在多个控制端上方的钼和/或任何其它适当的导电材料(例如被描述为适用于导电板14和多个导电块12的材料)。
在各个实施例中，如图2D所示，在半导体装置19的将要与封装材料18直接接触的表面上，可以可选地施加(例如，沉积)粘合促进剂32。粘合促进剂32可以用于改进封装材料18与封装材料18可能要粘合至的材料(例如，导电板14的导电材料和多个导电块12的导电材料，以及多个功率半导体器件10(例如半导体主体和/或端子的金属)的材料)之间的粘合性。可以使用本领域中已知的任何合适的粘合促进剂32，例如，铬酸锌。
在各个实施例中，半导体装置19的未和封装材料18进行接触的表面或表面的部分可以未被粘合促进剂32所覆盖。在施加促进剂32期间，这些表面或表面的部分可以例如被掩模或覆盖。在图2D中，多个导电块12的顶面12t和多个导电板14的底面14b保持未被粘合促进32所覆盖。另外，在未被封装材料18所覆盖并且可以暴露于氧气(例如大气中的氧气)的表面或表面的部分上，至少一些粘合促进剂32(例如铬酸锌)可以反应以形成可以是电绝缘的氧化物。
如图2E中示出的，在各个实施例中，在功率半导体器件10和导电块12连接到了导电板14，以及可选地，布置了控制端互连结构16且施加了粘合促进剂32之后，可以将封装材料18施加在位于导电板14上的功率半导体器件10上方。如图2E所示的顶部面板中，封装材料标示为18a，其意在表达在这一阶段，封装材料可以与它的最终状态相当不同。当施加封装材料18a时，其可以例如包括以下各项或由以下各项构成：粉末、颗粒、微球粒、球粒、薄片，或者其可以是液体，而固化后，封装材料18可以是固体结构。
在各个实施例中，封装材料18、18a(其可以至少在固化状态是电介质)可以具有以下效果：功率半导体器件10彼此是固定地且材料接合，并且功率半导体器件10接合到导电板14。合适的封装材料的示例包括具有高交联程度的聚合物，例如环氧树脂、有机硅、氰酸酯、双马来酰亚胺(bismaleimids，BMI)或聚酰亚胺，或所述聚合物的混合物，例如，环氧有机硅或环氧基的聚酰亚胺或其它组合。在各个实施例中，封装材料18可以是包括模制组分(例如以上所述的)以及可以被例如均匀分布在模制组分中的填充组分的复合物。填充组分可以例如包括以下各项或由以下各项构成：二氧化硅或具有高导热性的颗粒，例如，氧化铝、氮化硼、氮化硅、氮化铝或者金刚石。填充组分可以有助于实现在小的空间尺度上的均匀的温度分布，并且可以从而减轻或避免封装材料18中的热应力。但是，对于所有的实施例中，原则上可以使用任何封装材料18a、18，只要它们在固化状态时是电介质。封装材料18、18a可以例如适用于压缩模制和/或传送模制，和/或至少固化的封装材料18可具有耐高温性。在各个实施例中，封装材料18可以是具有高介电强度的绝缘材料。换句话说，大的电压差(例如，几百或几千伏)可以被施加到导电板14和导电块12而不会损坏封装材料18，即不失去其绝缘性。
在各个实施例中，如图2E所示的第二面板，利用成型装置44b、44t、87(例如，印模)，封装材料18a可以被压靠着导电板14，以使得至少位于各相邻的功率半导体器件10之间的间隙以及位于相邻的导电块12之间的间隙可以被填充有封装材料18a、18。这个工艺可被称为压缩模制。对于压缩模制，颗粒或液体可以用作封装材料18a。由封装材料18形成的外部形状可以通过形成在成型装置44b、44t、87的顶部部分44t中的空腔44c来限定。顶部部分44t可以包括以下部分或由以下部分构成，例如，顶部空腔板44t2和夹持环44t1，例如树脂夹持环44t1，例如弹簧加载的夹持环。替代地，顶部空腔板44t2可以是弹簧加载的。一个或多个真空通道41可以布置在顶端空腔板44t1与树脂夹持环44t之间。真空通道41可以用于将真空应用于空腔44c，例如用于将脱离膜46布置在空腔44c的表面上。成型装置44b、44t、87的顶部部分44t，例如空腔44c和导电板14的表面14t的界面可以以如下方式成型：导电板14的边缘区14e保持未被封装材料18所覆盖。在各个实施例中，边缘区域14e中可以具有在从约200μm至约5mm范围中的厚度(例如约1mm或约2mm)。
在各个实施例中，封装材料18、18a可以布置在空腔44c中。分配在导电板14上的封装材料18a的体积可以是这样的：使得在模制期间，空腔44c将至少填充有封装材料18，从而还覆盖多个导电块12的顶面12t。
在各个实施例中，脱离膜46可以布置在成型装置44b、44t、87的顶部部分44t与封装材料18、18a之间。因此，可以避免在成型装置44t、44b、87的顶部部分44t与封装材料18之间的接触。因此，高粘合性的材料可以用作封装材料18。脱离膜46可以有助于成型装置44t的顶部部分44t、44b、87与封装材料18的分离。此外，用于清洗成型装置44t、44b、87的清洗时间间隔可能不是必须的。
在各个实施例中，可以形成空腔44c，以使得封装材料18、18a还可以放置在多个导电块12的顶面12t上。
在各个实施例中，封装材料18a然后可以被固化，以使得嵌入到封装材料18中的功率半导体器件10连同封装材料18、多个导电块12以及导电板14形成固体复合物。成型装置44b、44t、87在封装材料固化后从该复合物剥离。图2E中的第四面板示出了可以在各个实施例中实现的复合物。
在各个实施例中，复合物的顶覆盖层48(在第四面板中，虚线上方的部分)可以从该复合物中去除。换句话说，可以(例如，通过研磨、抛光和/或磨削(lapping))去除封装材料18的顶部以及可选地多个导电块12的顶部。从而，可以形成复合物的顶面19t，并且从而形成半导体装置19的顶面，这包括多个导电块12的顶面12t和封装材料18的顶面18t。
在各个实施例中，半导体装置19的顶面19t可以基本上平行于导电板14的表面14t和/或第二表面14b。在各个实施例中，多个导电块12的顶面12t和封装材料18的顶面18t可以彼此基本上齐平。
去除顶覆盖层48可以暴露多个导电块12，即暴露多个导电块12的顶面12t。换句话说，多个导电块12的背向半导体主体10的一侧可以不被封装材料18所覆盖或至少不完全被封装材料18所覆盖，以使得它们可以被电接触。
在各个实施例中，半导体装置19的与导电板14相反的顶面19t的至少一部分12t可以与多个功率半导体器件10中的每个功率半导体器件10的相应的第二受控端电耦合。因此，多个功率半导体器件10可以从相反的表面19t、14b电连接，这是因为表面19t、14b(在顶面19t的情形下，至少部分地在导电块的顶面12t处)可以是导电的并且导电连接至多个半导体器件的相应端。暴露顶面的导电部分(即多个导电块12的顶面12t)可以不必通过如图2E中所示的研磨来暴露，但还可以通过其它工艺来实现，例如使用图2F中所示的传送模制。
在各个实施例中，半导体装置19可以被配置为具有在顶面19t的至少一部分12t与导电板14(例如导电板的底面14b)之间流动的电流。该电流可以是主电流。基本上或完全在半导体装置19的两个(例如主)表面12t与14b之间流动的电流也可以称为垂直电流。
由于去除了顶覆盖层48，多个导电块12的厚度与其原始厚度相比可以被减小，例如，减小大约0.1mm。如果适用的话，导电片的厚度也可以以相较于其原始的厚度同样地被减小。
在图1的透视图中可以看出，多个导电块12可以被封装材料18以环状的方式围绕。这同样可以应用于多个功率半导体器件10，这从图1A可以观察到，图1A还示出了封装材料18去除后的半导体装置。
在各个实施例中，封装材料18可以首先用来将单独的功率半导体器件彼此固定地连接，然后其次也用来保证功率半导体器件10的绝缘强度。为确保在完成的半导体装置19中的直接相邻的功率半导体器件10之间的足够绝缘强度，封装材料19可以具有最小水平宽度W1，即平行于导电板14的表面14t和/或平行于导电块12、封装材料18和/或半导体装置19的顶面12t、18t、19t的在相邻的功率半导体器件10的横向边缘之间的最小宽度W1。在各个实施例中，该最小宽度W1可以至少为100μm(例如至少2mm或至少5mm)。
图2F中示出的用于形成半导体装置的工艺与图2E中的工艺可以在很大程度上是相似的或部分地相同。因此，将仅描述与图2E中示出的工艺的不同处。
在各个实施例中，具有多个功率半导体器件10、多个导电块12和(可选的)控制端互连结构16的导电板14可以布置在成型装置44b、44t、87中。在围绕多个半导体器件10的封装材料18的成型工艺期间，成型装置44b、44t、87可以保持静止。换句话说，在成型工艺期间，成型装置44b、44t、87可以不具有或不使用印模功能，但可以限定将通过封装材料18形成的形状。布置在多个导电块12与成型装置44b、44t、87的顶部部分之间的脱离膜46可以接触(例如可以被按压在)多个导电块12的顶面12t。
在各个实施例中，封装材料18a可以直到那时才被引入(例如，如图2F所示的由填充装置的柱塞55推入)，从而进入形成在成型装置44b、44t、87的顶部部分44t与导电板14之间的空腔44c，例如通过在成型装置44b、44t、87的顶部部分44t与成型装置的布置在导电板14上的部件87(所谓的顶部边缘栅极)之间的开口。随后，封装材料18可以被固化，由此可以形成固体的整体封装材料18。在去除成型装置44t、44b、87和部件87后，可以暴露导电板14的边缘14e，也就是说，其可以不被封装材料18所覆盖。该工艺可以被称为传送模制。在各个实施例中，球粒状封装材料18a可以用于传送模制。
在传送模制的情况下，分配在导电板14上的封装材料18a的体积也可以是这样的：使得在该模制期间，空腔44c将至少填充有封装材料18。困在空腔44c中的空气可以通过至少一个空气排放孔65(参见图3B)来排出，和/或可以用封装材料18a填充之前应用真空。
在各个实施例中，也可以使用真空来将脱离膜46和/或半导体装置19吸附至成型装置44b、44t、87。
术语“成型装置的顶部部分”等等用于描述如各附图中示出的方向。然而，可以例如反转成型装置44b、44t、87(以及其它用于封装的相关部分)的布置，换句话说，成型装置44b、44t、87的具有空腔的部分可以布置在其它部分之下，即作为底部空腔板..
在各个实施例中，封装材料18可以以如下方式来形成：没有封装材料18形成在多个导电块12的顶面12t上。在各个实施例中，例如，在脱离膜46是厚的(例如100μm以上)并且是软性的情况下，多个导电块12的顶面12t甚至可以被压入脱离膜46，以使得多个导电块12的顶面12t在模制后可以从封装材料18稍微突出。另外，多个导电块12的顶面12t可以例如是与封装材料18的顶面18t齐平。因此，对所得到的半导体装置进行研磨可以被废弃。这不仅可以节省加工时间，还可以允许使用涂覆的导电块12(其涂层仍在模制后可能仍然存在)，这是因为如图2E中所示的还可以包括导电块12一部分的顶覆盖层48不需要被去除。
在各个实施例中，例如在图2E和图2F中示出的，半导体装置19可以包括控制端互连结构16，控制端互连结构16可以用于导电地连接多个功率半导体器件10的控制端到彼此。控制端互连结构16可以通过各种技术来生成。控制端互连结构可以是导电的或至少部分导电的。
在各个实施例中，控制端互连结构16可以作为预制元件(例如，作为印刷电路板或线栅格)被放置在功率半导体器件10、导电块12、导电板14和封装材料18的复合物上，并且可选地材料接合到该复合物。在各个实施例中，控制端互连结构16的预制元件可以布置在多个导电块12的顶面12t的层级之下的层级。从而，在模制工艺之后，控制端互连结构16可以如图2E和图2F所示的被包围在封装材料18中。
在各个实施例中，控制端互连结构16可以构造在复合物上。
在各个实施例中，可以例如通过使用薄膜技术将导电材料(金属或掺杂的多晶半导体材料)沉积至该复合物来实现控制端互连结构16，例如，薄膜技术是通过溅射或通过电镀或非电镀来进行，例如化学和/或物理沉积方法(例如如物理气相沉积(PVD)或化学气相沉积(CVD))。完成的沉积控制端互连结构16可以例如具有在从低于1μm至约100μm范围内的厚度(例如，从约5μm至约20μm，或从约30μm至约100μm)。
在各个实施例中，导电材料的封闭层可以形成在该复合物上，然后被结构化，例如借助于掩模装置来光刻。在各个实施例中，掩模层可以首先形成在复合物上，然后对掩模层进行结构化以使得其具有开口，然后将导电材料沉积在结构化的掩模层上，以使得该导电材料可以在掩膜开口区域中形成在复合物上并且可以导电地连接控制端。
在控制端互连结构16被包围(例如通过封装材料18被包围)的情况下，为了能够与控制端电接触，可以暴露封装材料所覆盖的控制端。原则上，任何期望的技术可以用于此目的。这些技术之一可以是通过激光束来去除控制端之上的封装材料18至某一程度，以使得封装材料18可以具有切除部。
在各个实施例中，控制端和/或控制端互连结构16可以形成在封装材料18的顶部上。
在各个实施例中，电介质层可以可选地形成在控制端互连结构16上以便将控制端互联结构16与多个导电块12电隔离。可以通过任何适当的技术来施加这种电介质层。举例而言，电介质材料可以通过沉积(例如PVD或CVD或溅射)施加在控制端互连结构16上。将压印的电介质板或电介质膜放置或粘接接合到控制端互连结构16上同样是可能的。
电介质层可以形成为具有切除部的预制层，其中可以以如下方式将该预制层与控制端互连结构16一起施加至该复合物：该切除部布置在多个导电块12上，并且可以通过电介质层和控制端互连结构16来与导电块12进行接触(例如，通过导电层，例如金属层64(参见图3B)，和/或通过接触板74t(参见图5))。
在各个实施例中，可以有所不同地施加电介质层，例如将电介质层作为封闭层施加至具有控制端互连结构16的复合物，以使得该封闭层覆盖控制端互连结构16和多个导电块12，然后形成切除部(通过该切除部可以与导电块12和控制端互连结构16进行电接触)，或通过在复合物上形成已具有结构化形式的电介质层。
图2G中示出了形成半导体装置的工艺，该工艺与图2E或图2F中的工艺可以在很大程度上是相似的或部分地相同。因此，将仅描述与图2E或图2F中所示的工艺的不同处。
如可以在图2G的顶部面板中可以看出，电介质材料18也可以形成在多个导电块12上。随后，如图2G的第二面板所示出的，可以在电介质材料18中(例如通过激光烧蚀或蚀刻)形成多个空腔63。例如，可以在每个导电块12上形成一个空腔63。在水平方向上，空腔63可以与导电块12几乎一样大。空腔63可以填充有导电材料67，例如通过导电膏，例如烧结或胶水，电镀，等离子体尘埃，激光烧结或金属片。
在各个实施例中，导电材料67可以被布置为不仅填充空腔63，还形成位于封装材料18和填充有导电材料67的空腔63上的层。在这种情况下，导电材料67可以被认为是形成导电层，例如金属层64。导电材料67可以例如是如前述布置的导电膏。
图2H中示出了形成半导体装置的工艺，该工艺与图2G中的工艺可以在很大程度上是相似的或部分地相同。因此，将仅描述与图2G示出的工艺的不同处。
在各个实施例中，可以在各导电块12上的封装材料18中形成多个较小的空腔63，而不是在各导电块12上形成相对大的空腔63。
图3A和图3B示出了根据不同实施例的处于不同的制造阶段期间的半导体装置19的透视图。
在各个实施例中，图3A中示出的半导体装置19可以与前述的半导体装置19相似或相同。因此重复的描述可以被省略。
如图4A和图4B中所示，半导体装置19还可以设置有密封结构66、68b、68t。密封结构66、68b、68t可以是功率半导体装置19的气密性密封的一部分以避免潜在的有害物质，例如，避免湿气、液体和/或化学物质。
如图3B、图4A和图4B中所示，在各个实施例中，密封结构66、68b、68t可以包括密封元件66，例如，密封环。密封元件66可以布置在导电板14的表面14t上，例如布置在未被封装材料18所覆盖的边缘区域14e上。如图4B所示，密封元件66可以是与导电板14和封装材料18两者接触(例如物理接触)。从而，其中封装材料18可以接触导电板14的接触区域可以与外部(例如湿气、液体和/或化学物质)密封隔离。换句话说，尽管现有技术的半导体装置19可以提供封装材料18与导电板14之间的路径，例如湿气沿该路径可以进入半导体装置19(例如到达多个功率半导体器件)，根据各个实施例，半导体装置19可以使用密封元件来密封该路径。导电板14的水平地突出超过封装材料18的边缘14e(例如在边缘14e处的表面14t)，可以提供用于布置密封元件66的适当位置。通过将密封元件66布置在导电板14的边缘14e上，可以增加导电板14与多个导电块12之间的表面距离(以及因此增加漏电距离)。
此外，在各个实施例中，密封元件66可以通过密封结构66、68b、68t的握持部68t、68b而被压至合适的位置。在各个实施例中，握持部68b、68t可以包括顶部68t和底部68b。在各个实施例中，可以以如下方式形成并布置顶部68t和底部68b：使得它们可以彼此分离。这可以允许半导体装置19容易在握持部68b、68t中定位，并且可以进一步允许握持部68t、68b按压在密封元件66上。
在各个实施例中，密封元件66可以以环状方式来布置。如上所述，在图3B中示出的示例性实施例中，这可以是指在水平面上形成闭合结构(即不具有开口)的密封元件66。在各个实施例中，这可以通过将预成型的环形密封元件66(例如密封环)布置在半导体装置19的边缘区域14e上来实现。在各个实施例中，预成型的密封元件66在其被布置在半导体装置19的边缘区域14e上之前可以不是环状的。相反，例如细长的密封元件66可以布置在半导体装置19的边缘区14e上环绕封装材料18，其中密封元件66的第一端和第二端相重叠。然后，密封元件66在半导体装置19的操作期间可以充当环状(闭合的)密封元件66，例如，通过挤压密封元件66(例如，密封元件66的端部)，或者通过例如使用例如粘接剂来闭合密封元件66的端部。在各个实施例中，密封元件66可以形成在半导体装置19上。例如，合适的材料(例如有机硅)可以布置(例如以环状方式)在半导体装置19上，例如布置在半导体装置的边缘区域14e上。
在各个实施例中，密封元件66可以包括弹性材料或由弹性材料构成。此外，弹性材料可具有耐高温性。例如，它可以承受大约150℃以上，例如约200℃以上。
在各个实施例中，弹性密封元件66可以包括palex、高温硅橡胶、Ecraz、和
在各个实施例中，如图3B所示，半导体装置19还可以包括导电层，例如，金属层64。该导电层64可以布置在半导体装置19的顶面19t上方。从而，导电层可以对封装材料18与导电块12之间的连接区域进行密封，以使得没有湿气等可以通过这些连接区域进入。
在各个实施例中，导电层64可以具有可压缩性，换句话说，在压力施加至半导体19的情况下，导电层64可以充当补偿层。换句话说，导电层64可以充当一种缓冲件或缓冲区。例如，导电层64的可压缩性和厚度可以适合于在半导体装置19内或在两个以上的半导体装置19之间对厚度或高度变化进行补偿。这使得半导体装置19的较大的制造公差成为可能，同时仍然保证半导体装置19的功能。
在各个实施例中，导电层64(例如金属层64)可以包括银或由银构成。
在各个实施例中，握持部68t、68b可以朝向半导体装置19按压导电层64(例如，导电层64的边缘)。在各个实施例中，握持部68t、68b可以形成导电层64与密封元件66之间的连接。从而，多个功率半导体器件10可以被气密性地与环境密封。换句话说，环境中没有部分(例如有害的部分)可以进入半导体装置19，并继续向功率半导体器件10行进。在各个实施例中，可以在导电板14的第二表面14b上提供额外的导电层64b。
图4A至图4E示出了根据不同实施例的具有密封结构66、68b、68t的半导体装置19透视图(图4A)和横截面图(图4B到图4E)。
如图4A所示，在各个实施例中，密封结构66、68b、68t可以以如下方式来形成：使得包括多个半导体装置19的半导体***76可以被形成。每个半导体装置19的控制端互连结构16可以通过第二互连结构78导电地连接。
如图4B所示，其示出了在箭头77的方向上可见到的图4A中的半导体装置19的一部分的横截面图，可以在半导体装置19和密封结构66、68b、68t之间形成密封区69a、69b、69c，例如密封区域69a(在密封元件66与导电板14之间)，密封区域69b(在密封元件66与封装材料18之间)和密封区域69c(在顶部68t与导电层64)之间。密封区69a、69b、69c中的每一个可以是半导体装置19与它的环境(例如大气)密封隔离的区域。
图4C示出了根据各个实施例的半导体装置19的横截面图。其与图4B中的半导体装置19主要不同在于开口101自靠近半导体装置19边缘的顶面19t形成在封装材料18中。在各个实施例中，开口101可以形成为槽，例如围绕半导体装置19的槽。该槽可以增加导电块12(或，更一般地，半导体装置19的顶面19t上的导电部)与导电板14之间的表面距离(例如沿表面的最短距离，也被称为表面距离)，并且从而增加可能处于不同的电势的两个导电元件之间的漏电距离。这可以允许在电势和/或操作电压之间的差的增加。
在各个实施例中，如图4D所示，第二密封元件66b(例如密封环)可以布置在开口101中。与针对图4B所描述的密封功能相类似，第二密封元件66b可以产生密封元件66与封装材料18之间的密封区域69b。
在各个实施例中，如图4E所示，密封元件66和66b都可以被布置，从而形成密封区域69a(位于密封元件66与导电板14之间)、密封区域69b(位于密封元件66与封装材料18之间)和密封区域69c(位于顶部部分68t与导电层64之间)。
在各个实施例中(未示出)中，密封元件66和/或密封元件66b可以嵌入在封装材料18中。
图5示出了根据各个实施例的半导体***76，顶部的分解图和底部的透视图。
为了使半导体装置19能够进行如上所述的电气操作，半导体装置19可以以如下方式被夹持在导电的一对接触板74t、74b(例如，顶部接触板74t和底部接触板74b)之间：使得顶部压力接触板74t和多个导电块12之间存在压力接触而无需顶部压力接触板74t和多个导电块12进行粘性连接，以及使得底部接触板74b和导电板14之间存在压力接触而无需底部压力接触板74b和导电板14进行粘性连接。顶部压力接触板74t和底部压力接触板74b可以连接到电压源，以使得不同的电势可以存在于顶压接触板74t和底部压力接触板74b处。
在各个实施例中，多个半导体装置19可以组合到半导体***76中。图5中示出的半导体***76的组成在前面已经进行了描述。它们可以相互作用以提供压力接触，例如，通过接触板74t、74b来进行。
图6示出了根据各个实施例的、描述形成半导体装置的方法的流程图600。
在各个实施例中，该方法可以包括：将多个功率半导体器件布置在导电板的表面上(在601)。
该方法还可以包括：将多个功率半导体器件中的每个功率半导体器件的第一受控端电耦合至导电板(在602)，将多个导电块中的每个导电块与多个功率半导体器件中的每个功率半导体装置的相应的第二受控端电耦合(在603)；以及利用封装材料对多个功率半导体器件进行封装，以使得导电板的表面的至少一个边缘区域没有被封装材料所封装(在604)。
过程的各个实施例的细节已经在上面(例如在具有可视化该过程的上下文中)进行了描述，。
图7示出了根据各个实施例的形成半导体装置的方法700的流程图。各过程的细节可以如上文所述。
方法700可以包括材料准备(在701)，例如准备将要在该方法的过程期间使用的各种材料。该方法还可以包括第一附着工艺(在702)，在第一附着工艺期间，多个功率半导体器件可以附着(例如连接)到导电板(例如钼板)。该方法还可以包括第二管芯附着工艺(在703)，以用于将多个导电块与多个功率半导体器件进行连接。该方法还可以包括第三附着工艺，例如用于形成控制端互连结构(也被称为栅极层)的附着工艺(在704)以及将粘合促进剂施加到半导体装置的可以与封装材料接触的表面的可选工艺(在705)。该方法还可以包括形成封装(在706)，例如通过模制。该方法还可以包括可选的研磨工艺(在707)。为了质量控制，在各个实施例中，该方法可以包括测试工艺(在708)，例如电测试。该方法还可以包括所谓的标记/扫描/包装工艺(在709)，其可以包括光学检查和/或共焦扫描声学显微镜(Confocal Scanning Acoustic Microscopy，CSAM)检查，标记和包装。该方法还可以包括出货(在710)。
在各个实施例中，提供了一种半导体装置。所述半导体装置可以包括：具有表面的导电板；多个功率半导体器件，其设置在所述导电板的所述表面上，其中，所述多个功率半导体器件中的每个功率半导体器件的第一受控端均可以电耦合至所述导电板；多个导电块，其中，每个导电块可以与所述多个功率半导体器件中的每个功率半导体器件的相应的第二受控端电耦合；以及封装材料，其封装所述多个功率半导体器件，其中，所述导电板的所述表面的至少一个边缘区域可以未被封装材料所封装。
在各个实施例中，所述半导体装置的与所述导电板相反的顶面的至少一部分可以与所述多个功率半导体器件中的每个功率半导体器件的相应的第二受控端电耦合。
在各个实施例中，所述半导体装置可以被配置为具有在所述顶面的所述至少一部分与所述导电板之间流动的电流。
在各个实施例中，所述电流可以是主电流。
在各个实施例中，所述半导体装置还可以包括密封结构。
在各个实施例中，所述密封结构可以包括密封元件。
在各个实施例中，所述密封元件可以是密封环。
在各个实施例中，所述密封环可以被布置在所述导电板的所述表面的所述至少一个边缘区域上。
在各个实施例中，所述密封元件可以嵌入在所述封装材料中。
在各个实施例中，所述封装材料可以具有密封性。
在各个实施例中，所述封装材料可以包括有机硅或由有机硅构成。
在各个实施例中，所述密封结构可以包括弹性耐高温材料。
在各个实施例中，所述密封元件(例如密封环)可以由弹性耐高温材料构成。
在各个实施例中，所述半导体装置还可以包括：布置在所述多个导电块上方和所述封装材料上方的导电层。
在各个实施例中，所述导电层、所述密封结构以及所述导电板被布置为形成所述多个半导体器件的气密性密封的至少一部分。
在各个实施例中，所述半导体装置还可以包括：至少一个控制端，其用于控制所述多个功率半导体器件中的至少一个功率半导体器件的所述第一受控端与所述第二受控端之间的电流。
在各个实施例中，所述多个功率半导体器件可以包括多个IGBT。
在各个实施例中，所述多个功率半导体器件可以包括至少一个功率二极管。
在各个实施例中，所述导电板还可以包括与所述表面相反的第二表面以及连接所述表面和所述第二表面的侧面，并且其中，所述第二表面和所述侧面未被所述封装材料所封装。
在各个实施例中，所述导电板和/或所述多个导电块可以包括以下导电材料组中的至少一种导电材料：钼；铜；以及碳。
在各个实施例中，提供了一种半导体***。该半导体***可以包括多个上述的半导体装置。
在各个实施例中，所述半导体装置的所述顶面的所述至少一部分与所述导电板之间的连接面包括：增加所述半导体装置的所述顶面的所述至少一部分与所述导电板之间的表面距离的结构。
在各个实施例中，提供了一种形成半导体装置的方法。该方法可以包括：将多个功率半导体器件布置在导电板的表面上；将所述多个功率半导体器件中的每个功率半导体器件的第一受控端电耦合至所述导电板；将多个导电块中的每个导电块与所述多个功率半导体器件中的每个功率半导体器件的相应的第二受控端相电耦合；以及利用封装材料对所述多个功率半导体器件进行封装，以使得所述导电板的所述表面的至少一个边缘区域未被所述封装材料所封装。在各个实施例中，所述封装可以包括模制。
在各个实施例中，所述模制可以包括传送模制和压缩模制中的一种。
在各个实施例中，在所述传送模制期间，所述多个导电块中的每一个导电块的背向所述多个功率半导体器件中的相应的功率半导体器件的表面保持未被所述封装材料所封装。
在各个实施例中，该方法还可以包括：将密封元件布置在所述至少一个边缘区域上。
在各个实施例中，所述密封元件可以是密封环。
在各个实施例中，该方法还可以包括：将导电层布置在所述多个导电块上方和所述封装材料上方。
在各个实施例中，该方法还可以包括：通过在所述导电层与所述密封环之间形成气密性密封连接并且通过将所述密封环压至所述至少一个边缘区域上来形成用于所述多个功率半导体器件的气密性密封。
虽然已经参照特定的实施例对本发明进行了具体地示出和描述，但是本领域技术人员应当理解，在不脱离如所附权利要求书所定义的本发明的精神和范围的情况下，可以在其中进行形式和细节上的各种改变。因此，本发明的范围由所附的权利要求书指示，并且因此旨在涵盖落入权利要求书的等效的意义和范围内的所有改变。

Claims (26)

1.一种半导体装置，包括：
具有表面的导电板；
多个功率半导体器件，其布置在所述导电板的所述表面上，其中，所述多个功率半导体器件中的每个功率半导体器件的第一受控端均电耦合至所述导电板；
多个导电块，每个导电块与所述多个功率半导体器件中的每个功率半导体器件的相应的第二受控端电耦合；以及
封装材料，其封装所述多个功率半导体器件，其中，所述导电板的所述表面的至少一个边缘区域未被所述封装材料所封装。
2.根据权利要求1所述的半导体装置，
其中，所述半导体装置的与所述导电板相反的顶面的至少一部分与所述多个功率半导体器件中的每个功率半导体器件的所述相应的第二受控端电耦合。
3.根据权利要求2所述的半导体装置，
其中，所述半导体装置被配置为具有在所述顶面的所述至少一部分与所述导电板之间流动的电流。
4.根据权利要求1至3中任一项所述的半导体装置，还包括：
至少一个控制端，其用于控制所述多个功率半导体器件中的至少一个功率半导体器件的所述第一受控端与第二受控端之间的电流。
5.根据权利要求1至4中任一项所述的半导体装置，还包括密封结构。
6.根据权利要求5所述的半导体装置，其中，所述密封结构包括密封元件。
7.根据权利要求6所述的半导体装置，其中，所述密封元件是密封环。
8.根据权利要求6或7所述的半导体装置，其中，所述密封元件布置在所述导电板的所述表面的所述至少一个边缘区域上。
9.根据权利要求5至8中任一项所述的半导体装置，其中，所述密封元件嵌入在所述封装材料中。
10.根据权利要求1至9中任一项所述的半导体装置，其中，所述封装材料具有密封性。
11.根据权利要求1至10中任一项所述的半导体装置，还包括布置在所述多个导电块上方和所述封装材料上方的导电层。
12.根据权利要求11所述的半导体装置，其中，所述导电层、所述密封结构以及所述导电板被布置为形成所述多个半导体器件的气密性密封的至少一部分。
13.根据权利要求1至12中任一项所述的半导体装置，其中，所述多个功率半导体器件包括多个IGBT。
14.根据权利要求1至13中任一项所述的半导体装置，其中，所述多个功率半导体器件包括至少一个功率二极管。
15.根据权利要求1至14中任一项所述的半导体装置，
其中，所述导电板还包括与所述表面相反的第二表面以及连接所述表面和所述第二表面的侧面；并且
其中，所述第二表面和所述侧面未被所述封装材料所封装。
16.根据权利要求1至15中任一项所述的半导体装置，
其中，所述导电板和/或所述多个导电块包括以下导电材料组中的至少一种导电材料：
钼；
铜；以及
碳。
17.根据权利要求2至16中任一项所述的半导体装置，
其中，所述半导体装置的所述顶面的所述至少一部分与所述导电板之间的连接面包括：增加所述半导体装置的所述顶面的所述至少一部分与所述导电板之间的表面距离的结构。
18.一种半导体***，包括：多个根据权利要求1至17中任一项所述的半导体装置。
19.一种形成半导体装置的方法，所述方法包括：
将多个功率半导体器件布置在导电板的表面上；
将所述多个功率半导体器件中的每个功率半导体器件的第一受控端电耦合至所述导电板；
将多个导电块中的每个导电块与所述多个功率半导体器件中的每个功率半导体器件的相应的第二受控端电耦合；以及
利用封装材料对所述多个功率半导体器件进行封装，以使得所述导电板的所述表面的至少一个边缘区域未被所述封装材料所封装。
20.根据权利要求19所述的方法，其中，所述封装包括模制。
21.根据权利要求20所述的方法，其中，所述模制包括转送模制和压缩模制中的一种。
22.根据权利要求21所述的方法，其中，在所述转送模制期间，所述多个导电块中的每一个导电块的背向所述多个功率半导体器件中的相应的功率半导体器件的表面保持未被所述封装材料所封装。
23.根据权利要求19至22中任一项所述的方法，还包括：
将密封元件布置在所述至少一个边缘区域上。
24.根据权利要求23所述的方法，其中，所述密封元件是密封环。
25.根据权利要求18至24中任一项所述的方法，还包括：
将导电层布置在所述多个导电块上方和所述封装材料上方。
26.根据权利要求25所述的方法，还包括：
通过在所述导电层与所述密封环之间形成气密性密封连接并且通过将所述密封环压至所述至少一个边缘区域上来形成用于所述多个功率半导体器件的气密性密封。
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