CN107202948A - The circuit test plate of high test density - Google Patents
The circuit test plate of high test density Download PDFInfo
- Publication number
- CN107202948A CN107202948A CN201610156896.1A CN201610156896A CN107202948A CN 107202948 A CN107202948 A CN 107202948A CN 201610156896 A CN201610156896 A CN 201610156896A CN 107202948 A CN107202948 A CN 107202948A
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- China
- Prior art keywords
- insulating barrier
- those
- connector
- plate
- circuit
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07314—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Measuring Leads Or Probes (AREA)
Abstract
The present invention provides a kind of circuit test plate of high test density, include a substrate, one first insulating barrier, a wiring layer, one second insulating barrier, multiple conductive cones, the upper and lower surface of the substrate is respectively equipped with multiple bottom electrodes and multiple Top electrodes, and those bottom electrodes are electrically connected with those Top electrodes；The upper surface of the substrate sets first insulating barrier, the wiring layer is formed in first insulating barrier and by least one first connector electrical connections those Top electrodes, second insulating barrier is arranged at first insulating barrier, those conduction cones are formed at second insulating barrier with matrix arrangement and electrically connect the wiring layer by least one second connector, using the wiring layer, first connector, second connector line arrangement, electrical measurement electric power is provided to the conduction cone of part, electrical measurement density is lifted by the arrangement of those conduction cones.
Description
Technical field
The present invention is, on a kind of circuit test plate, to refer in particular to a kind of circuit test plate with high test density.
Background technology
The electrical measurement of circuit board to make one of base program of circuit board, for examine circuit board can work well, because
This needs correct and perfect instrument to support, and in electrical measurement, a circuit board is often stacked in a test of a measurement apparatus
On tool, the measurement apparatus transmits electric power to the measurement jig, measurement jig selectivity by power transmission to the circuit board
On electrode or tested point, to the circuit board carry out electrical measurement.It refer to shown in Fig. 5, current measurement jig 70 contains a bottom
Plate 71, two spring parts 72, a lifter plate 73, multiple pogo pins 74, a mask plate 75.The bottom plate 71 is formed with multiple shrinkage pools
76, those shrinkage pools 76 are evenly distributed in the surface of the bottom plate 71 with matrix arrangement, and the bottom plate 71 is fixed at two spring parts 72 interval
Surface, the lifter plate 73 is fixed on the top of two spring parts 72 and by two spring parts 72 relative to being moved down on the bottom plate 71
It is dynamic, corresponding multiple perforation 77 vertical with those shrinkage pools 76 are formed with the lifter plate 73.
Each pogo pin 74 has a probe 741 and a pars contractilis 742, and those pars contractilis 742 are respectively contained in those
The bottom of shrinkage pool 76, respectively the bottom of the probe 741 connect the top of the pars contractilis 742.
When using 70 pair of one circuit board under test 80 of the measurement jig to test, the mask plate 75 should be first prepared, in this
Multiple through holes 751 are formed on mask plate 75, the position of those through holes 751 corresponds to the multiple electrodes 81 of the circuit board under test 80
Or tested point.
The mask plate 75 is stacked to the lifter plate 73, and the circuit board under test 80 is placed on the mask plate 75, should
Mask plate 75, because of the spring part 72 of gravity compressed two, makes the lifter plate 73 be moved towards the bottom plate 71, now, had with the lifter plate 73
Its probe 741 of partial pogo pin 74 passes through the perforation 77 of the lifter plate 73 and the partial through holes 751 of the mask plate 75,
Those probes 741 are made to be respectively electrically connected to those electrodes 81 of the circuit board under test 80, because this of each pogo pin 74 is stretched
Contracting portion 742 is connected with a wire (not shown), and those wires transmit electric power to those pogo pins 74, when those probes 741 connect
Transmitted electric power when touching to those electrodes 81 to those electrodes 81, electrical measurement is carried out to the test circuit plate 80；Wherein, it is not electric with those
The part pogo pin 74 that pole 81 is arranged vertically, its probe 741, will not be with the circuit under test by the stop of the mask plate 75
Plate 80 is in contact, and can avoid occurring short circuit or false touch to remaining conduction region (such as conducting wire) of the circuit board under test 80.
However, the situation of short circuit is mutually touched, occurred in order to avoid those pogo pins 74, current lifter plate 73 needs
The spacing between pogo pin 203 is limited, i.e., must keep certain spacing between those perforation 77 so that those perforation
Adjacent probe first the distance between 741 can not shorten in 77, and the test density that result in current circuit test plate is relatively low, easily
All electrodes 81 or tested point of the circuit board under test 80 can not be contacted by occurring pogo pin 74, cause the place that be powered not
It is powered and occurs test leakage, or the mistake of testing result mistake is surveyed.
Refer to shown in Fig. 6 A, in order to solve the problem of test density is not enough, using the measurement jig of another structure,
In stacking an at least accessory plate 78 on the mask plate 75, an at least accessory plate 78 is formed with multiple perforations 781, those flexible spies
Pin 74 wears those perforations 781.When those pogo pins 74 are not tilted, the measurement spacing between those tops of pogo pin 74
For L1, when the spacing L2 to be measured between the electrode 81 of the circuit board under test 80 is less than measurement spacing L1, there will be the electricity of part
Pole 81 can not electrically connect the flexible pin 74, the problem of occurring test leakage or survey by mistake.
Refer to shown in Fig. 6 B, when moving horizontally the accessory plate 78, those perforations 781 on an at least accessory plate 78
Meeting horizontal displacement, when the offset distance of displacement exceedes the aperture of the perforation 781, the perforation 781 is in displacement process tight against the spy
Syringe needle 741 and promote the probe 741, tilt the probe 741, the position in the aperture of those perforations 781, size and
The offset distance of displacement determines the angle of inclination of the probe 741.If the offset distance of displacement is not less than the hole of the perforation 781
The pogo pin 74 in footpath, the perforation 781 will not produce inclination or angle of inclination is smaller, therefore part pogo pin 74 is protected
Hold vertical, part pogo pin 74 towards the direction of not inclined pogo pin 74 tilt when, the survey between those probes 741
Amount spacing L1 can shorten, and make the spacing L2 to be measured between the measurement spacing L1 and those electrodes 81 identical, and lifting test is close
Degree to carry out electrical measurement to circuit board under test 80.
Above-mentioned measurement jig tilts those pogo pins 74 by displacement accessory plate 78, although can reduce those probes
Measurement spacing L1 between 741, but during displacement, often occurs because angle of inclination is excessive and pogo pin 74
Length, elasticity it is different, occur to cannot connect to the electrode 81 of the circuit board under test 80 after pogo pin 74 is tilted, or only connect
The edge of the electrode 81 is contacted, causes test abnormal.In addition, pogo pin 74 has certain cost, excessive enters to probe
Line tilt can cause pogo pin 74 often to produce friction with mask plate 73 or accessory plate 78, destruction, abrasion pogo pin 74
Structure, the service life for shortening pogo pin 74 shortens, it is necessary to make a big purchase pogo pin 74 in large quantities, so that in the cost of measurement
Rise.
The content of the invention
Via described above it is known that the problem of current circuit board testing device has test density not enough, if
Tilt telescopic probe then can easily wear and tear, destroy probe structure or because curtailment causes with the electrode contact of circuit board not
Good is very that in view of this, present invention system provides a kind of circuit test plate of high test density, to improve to the problem of can not contacting
Problem above.
The technical way used in order to achieve the above object, is that the circuit test plate for making the high test density is included
Have：
One substrate, with a lower surface and a upper surface；
Multiple bottom electrodes, are formed at the lower surface of the substrate；
Multiple Top electrodes, are formed at the upper surface of the substrate and are electrically connected respectively with those bottom electrodes；
One first insulating barrier, is arranged at the upper surface of the substrate, and first insulating barrier has at least one first connector,
Respectively at least one first connector is electrically connected those corresponding Top electrodes；
One wiring layer, is formed at the surface of first insulating barrier and electrically connects at least one first connector, to electrically connect
Those Top electrodes；
One second insulating barrier, is arranged at the surface of first insulating barrier, and first insulating barrier is with least one second connection
Part, respectively second connector electrically connect the wiring layer；And
Multiple conductive cones, are formed at the surface of second insulating barrier and are electrically connected respectively at least one second connector,
The plurality of conductive cone is in electrical contact with a circuit board under test.
By above structure it is known that those conduction cones are for multiple tested points connection on a circuit board to be measured, the base
Those bottom electrodes of plate are connected for an outer lead, to transmit electric power to those Top electrodes, the Top electrode using the wiring layer,
At least one first connector, at least one second connector are selected power transmission to the part for having connected those tested points
Those conduction cones, the conductive cone of not connected tested point does not receive electric power then, and the present invention uses those conduction cones to be used as test
Probe, which conductive cone is provided using the wiring layer, at least one first connector, at least one second connector selection
Electric power, you can test the circuit board.The present invention replaces conventional probe, effectively lifting measurement density using conductive cone, in
In high density electrical testing, without flexure probe, testing procedure can be simplified, shorten the testing time, in addition, using the electricity of the present invention
Drive test test plate (panel) need not buy more probe, can not only reduce testing cost, more without installing, change probe the problem of.
Brief description of the drawings
Fig. 1 is the diagrammatic cross-section of the present invention；
Fig. 2 is the schematic perspective view of the present invention；
Fig. 3 is the diagrammatic cross-section of the conductive cone of the present invention；
Fig. 4 is the diagrammatic cross-section that electrical measurement is carried out using the present invention；
Fig. 5 is the diagrammatic cross-section of existing circuit testing jig；
Fig. 6 A are the diagrammatic cross-sections of its another embodiment of existing circuit testing jig；
Fig. 6 B are the operation charts of its another embodiment of existing circuit testing jig.
Reference
The lower surface of 10 substrate 11
The conducting piece of 12 upper surface 13
The Top electrode of 21 bottom electrode 22
The connection electrode of 23 wiring layer 24
The insulating barrier of 25 surface electrode 30 first
The first through hole of 31 first insulating surface 32
The insulating barrier of 33 first connector 40 second
The through hole of 41 second insulating surface 42 second
The conductive cone of 43 second connector 50
The strengthening layer of 51 conductive layer 52
The circuit board under test of 53 anti oxidation layer 60
The measurement jig of 61 tested point 70
The spring part of 71 bottom plate 72
The pogo pin of 73 lifter plate 74
The pars contractilis of 741 probe 742
The through hole of 75 mask plate 751
76 shrinkage pools 77 are perforated
The perforation of 78 accessory plate 781
The electrode of 80 circuit board under test 81
Embodiment
Refer to shown in Fig. 1 and Fig. 2, the present invention provides a kind of circuit test plate of high test density, includes：One substrate
10th, multiple bottom electrodes 21, multiple Top electrodes 22, one first insulating barrier 30, a wiring layer 23, multiple connection electrodes 24, one second
Insulating barrier 40, multiple surface electrodes 25, multiple conductive cones 50.
The substrate 10 is a ceramic substrate, and the substrate 10 has a lower surface 11 and a upper table relative with the lower surface 11
Face 12.
Those bottom electrodes 21 are formed at the lower surface 11 of the substrate 10, between those bottom electrodes 21 are arranged simultaneously in a matrix fashion
Every setting.Those Top electrodes 22 are formed at the upper surface 12 of the substrate 10, and each Top electrode 22 is hung down with each bottom electrode 21 respectively
Straight correspondence arrangement, wherein, the substrate 10 is respectively formed with multiple conducting pieces between those bottom electrodes 21 and those Top electrodes 22
13, each two ends of conducting shell 13 are electrically connected a bottom electrode 21 and a Top electrode 22.
First insulating barrier 30 covers upper surface 12 and those Top electrodes 22, and first insulating barrier 30 has one first insulation
Surface 31, at least a first through hole 32, at least one first connector 33.First insulating surface 31 refers to first insulating barrier 30
Upper surface；An at least first through hole 32 is abutted and right through first insulating barrier 30 and with those Top electrodes 22 of part
Together, at least a connection piece 33 is formed in an at least first through hole 32 and electrically connected with those part Top electrodes 22.
The wiring layer 23 and those connection electrodes 24 are formed at first insulating surface 31, and the wiring layer 23 is connected with those
Electrode 24 is electrically connected；Those connection electrodes 24 those connection electrodes 24 arranged in a straight line and partial with those Top electrodes 22 are with being somebody's turn to do
At least one first connector 33 is electrically connected, and makes the wiring layer 23 and those connection electrodes 24 via at least one first connector 33
Electrically connected with part Top electrode 22.Second insulating barrier 40 covers first insulating surface 31, the wiring layer 23 and those connections
Electrode 24, second insulating barrier 40 has one second insulating surface 41, at least at least one second through hole 42, one second connector
43.Second insulating surface 41 refers to the upper surface of second insulating barrier 40；At least one second through hole 42 is second exhausted through this
Edge layer 40 is simultaneously abutted and alignd with those connection electrodes 24 of part, at least one second connector 43 be formed at this at least one
Electrically connect in second through hole 42 and with those part connection electrodes 24.
Those surface electrodes 25 are formed at second insulating surface 41, and those surface electrodes 25 and those connection electrodes 24 are straight
Line is arranged, and those partial surface electrodes 25 electrically connect at least one second connector 43, make those surface electrodes of part
25 electrically connect via at least one second connector 43 with those part connection electrodes 24.
Those conduction cones 50 are respectively formed on those surface electrodes 25 and electrically connected with those surface electrodes 25, and those are led
Vertical direction of electricity 50 its shape of cone along second insulating surface 41 is in tapered.Refer to shown in Fig. 3, conduction cone 50 is further included
There are a conductive layer 51, strengthening layer 52, an anti oxidation layer 53.The strengthening layer 52 coats the conductive layer 51, and the anti oxidation layer 53 is coated
The strengthening layer 52；The hardness of the strengthening layer 52 is more than the conductive layer 51, to lift the intensity of conduction cone 50, the conduction is bored 50
With enough intensity to support circuit board to be measured；The oxide layer 53 coats the strengthening layer 52, the conductive layer 51, due to those
Conduction cone 50 is to electrically connect the tested point on circuit board under test, to avoid its electric conductivity from declining because of oxidation, therefore is utilized
The cushion that the anti-ization layer 53 is contacted as those conduction cones 50 with extraneous air, to prevent those conduction cones 50 from aoxidizing.
The material of the conductive layer 51 can be copper or its alloy；The material of the strengthening layer 52 can be nickel, cobalt, tungsten or its alloy；
The material of the anti oxidation layer 53 can be gold, tin or its alloy, in present embodiment, and the material of the strengthening layer 52 is nickel cobalt (alloy)
Or nickel tungsten, wherein, the ratio of nickel accounts for 97 95 percent to percent in the nickel cobalt (alloy) or the nickel tungsten
Between.
Refer to shown in Fig. 4, will when carrying out electrical testing to a circuit board under test 60 using the circuit test plate of the present invention
The circuit test plate is installed in a test device (not shown) and connects the conductive plate in the test device or multiple wires (not
Show), and the circuit board under test 60 is arranged on those conduction cones 50, by the tested point 61 (or electrode) of the test circuit plate 60
Those conduction cones 50 are contacted respectively.Test device utilizes those bottom electrodes of the conductive plate or those wires to the circuit test plate
21 transmission electric power, the circuit test plate is sent to by electric power.Wherein, the circuit test plate using the wiring layer 23, this at least
The configuration of one first connector 33, at least one second connector 43, the electric power of the measurement apparatus is transferred to by selection will
Contact those tested points 61 those conduction cone 50, to the slowdown monitoring circuit plate 60 is carried out electrically or circuit test, in order in response to
The position arrangement or variant of the different tested points 61 of circuit board under test 60, can change the wiring layer 23, at least one first connection
The layout of part 33, at least one second connector 43, adjusts the path of electric current, and which conductive cone 50 control electric power will be transmitted to,
Therefore, the wiring layer 23, at least one first connector 33, the layout and the circuit board under test of at least one second connector 43
The mutually correspondence of tested point 61 on 60.
The structure of the circuit test plate of the present invention can be using existing circuit-board processes manufacture at present, the wiring layer 23, should
At least one first connector 33, the configuration of at least one second connector 43 are then by 61 pairs of the electrode of the circuit board under test 60
It should be formed, the supplier of current circuit board is utilized current existing material, you can the height test for completing and obtaining the present invention is close
The circuit test plate of degree, makes the electrical measurement of circuit board more easy.
The present invention is not used existing pogo pin to connect the tested point 61 of circuit board under test 60, and test of the invention is close
Degree is not only restricted to the spacing limitation of existing pogo pin.The present invention only needs to avoid those surface electrodes under those conduction cones 50
25 contacts, can be with highdensity spread configuration conduction cone 50, and the circuit test plate of the present invention can be via existing electricity
Road plate technique is completed, therefore, the minimum spacing that the minimum spacing between those conduction cones 50 can be formed at present with circuit board industry
It is identical, will not occur the distance between tested point 61 on circuit board under test 60 and be less than between those conduction cones 50 of the present invention
Distance, even if line footpath, the line width of its circuit board of industry more do smaller at present, but the technology and circuit of the circuit test plate of the present invention
Plate manufacturing technology is identical, and its test density solves at present test density during for electrical measurement not enough with industrial technology Synchronous lifting
The problem of.
In summary, the circuit test plate of high test density of the invention, uses the wiring layer, at least one first connection
The configuration of part, at least one second connector, enables electric power to transmit to the test point for needing connection circuit board under test
Conduction cone, and because conductive cone can be with highdensity arrangement so that when carrying out electrical measurement using the present invention, there can be higher survey
Try density.In addition, the structure of the present invention can be completed using existing circuit-board processes, make the acquirement of circuit test plate simpler
It is single, and when carrying out electrical measurement using the present invention, without device, change probe, electrical measurement efficiency can be lifted, the material of electrical measurement can be also reduced
Expecting the spacing between cost, and conductive cone can complete that electrode spacing is identical with current circuit board industry, make test of the invention
Density can increase with the progress of circuit board industry, even for line footpath it is less and less, make the higher and higher electricity of precision
Road plate carries out electrical measurement, can all smoothly complete, and improves the defect that tradition carries out electrical measurement using probe.
The internal structure of the present invention is disclosed via present invention, has absolutely proved internal structure, action specification and effect,
It is in fact to have possessed the important document applied for a patent；Wherein, content of the present invention, only as the explanation of embodiment, is not limited with this
Fixed scope of protection of the present invention, any local change, the structure changed, still falls within the scope of protection of the invention.
Claims (10)
1. a kind of circuit test plate of high test density, it is characterised in that described circuit test plate is included：
One substrate, with a lower surface and a upper surface；
Multiple bottom electrodes, are formed at the lower surface of the substrate；
Multiple Top electrodes, are formed at the upper surface of the substrate and are electrically connected respectively with the multiple bottom electrode；
One first insulating barrier, is arranged at the upper surface of the substrate, first insulating barrier is with least one first connection
Part, each at least one first connector is electrically connected corresponding the multiple Top electrode；
One wiring layer, is formed at the surface of first insulating barrier and electrically connects at least one first connector, with electrical connection
The multiple Top electrode；
One second insulating barrier, is arranged at the surface of first insulating barrier, first insulating barrier is with least one second connection
Part, each second connector electrically connects the wiring layer；And
Multiple conductive cones, are formed at the surface of second insulating barrier and are electrically connected each at least one second connector,
The multiple conductive cone is in electrical contact with a circuit board under test.
2. the circuit test plate of high test density according to claim 1, it is characterised in that each conductive cone is further included
Have：
One conductive layer；
One strengthening layer, is coated in the conductive layer；
One anti oxidation layer, is coated in the strengthening layer.
3. the circuit test plate of high test density according to claim 2, it is characterised in that the material of the conductive layer is
Copper or its alloy.
4. the circuit test plate of high test density according to claim 2, it is characterised in that the material of the strengthening layer is
Nickel, cobalt, tungsten or its alloy.
5. the circuit test plate of high test density according to claim 2, it is characterised in that the anti oxidation layer material is
Gold, tin or its alloy.
6. the circuit test plate of the high test density according to any claim in claim 1 to 5, it is characterised in that
The substrate is ceramic substrate.
7. the circuit test plate of the high test density according to any claim in claim 1 to 5, it is characterised in that
Multiple surface electrodes, at least one second company described in the multiple surface electrode electrical connection are formed in the surface of second insulating barrier
Fitting, and each conductive cone is respectively arranged on the multiple surface electrode.
8. the circuit test plate of high test density according to claim 7, it is characterised in that the wiring layer has been further included
Multiple connection electrodes, at least one first connector, at least one second connector described in the multiple connection electrode electrical connection.
9. the circuit test plate of high test density according to claim 8, it is characterised in that the multiple connection electrode,
The multiple surface electrode, the multiple Top electrode, the multiple bottom electrode are to be vertically arranged.
10. the circuit test plate of the high test density according to any claim in claim 1 to 5, it is characterised in that
First insulating barrier covers the upper surface of the substrate and the multiple Top electrode, the second insulating barrier covering described first
The surface of insulating barrier and the wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610156896.1A CN107202948B (en) | 2016-03-18 | 2016-03-18 | The circuit test plate of high test density |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610156896.1A CN107202948B (en) | 2016-03-18 | 2016-03-18 | The circuit test plate of high test density |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107202948A true CN107202948A (en) | 2017-09-26 |
| CN107202948B CN107202948B (en) | 2019-09-24 |
Family
ID=59904308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610156896.1A Active CN107202948B (en) | 2016-03-18 | 2016-03-18 | The circuit test plate of high test density |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107202948B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108709909A (en) * | 2018-06-25 | 2018-10-26 | 中国地质大学（武汉） | A kind of electrode assembly based on EIT non-destructive testing cement base tablets |
| CN110426536A (en) * | 2019-07-29 | 2019-11-08 | 重庆伟鼎电子科技有限公司 | PCB conductive fabric measurement circuit plate |
| CN111014057A (en) * | 2019-12-05 | 2020-04-17 | 临海市锦铮机械有限公司 | Brain wave sensor resistance automatic detection machine |
| CN117288824A (en) * | 2023-11-23 | 2023-12-26 | 有研(广东)新材料技术研究院 | Test system based on silicon nanowire field effect sensor |
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| JP2002310933A (en) * | 2001-04-17 | 2002-10-23 | Nidec-Read Corp | Apparatus and method for inspection of circuit board as well as electro-optical element |
| CN1452231A (en) * | 2002-04-18 | 2003-10-29 | 三菱电机株式会社 | Testing board for testing semiconductor |
| CN1985180A (en) * | 2004-07-15 | 2007-06-20 | Jsr株式会社 | Device and method for inspection of circuit board |
| CN201681141U (en) * | 2010-04-02 | 2010-12-22 | 徐宇震 | Combined density tester for printed circuit board |
| JP2015195272A (en) * | 2014-03-31 | 2015-11-05 | 新光電気工業株式会社 | Semiconductor device and semiconductor manufacturing method |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002310933A (en) * | 2001-04-17 | 2002-10-23 | Nidec-Read Corp | Apparatus and method for inspection of circuit board as well as electro-optical element |
| CN1452231A (en) * | 2002-04-18 | 2003-10-29 | 三菱电机株式会社 | Testing board for testing semiconductor |
| CN1985180A (en) * | 2004-07-15 | 2007-06-20 | Jsr株式会社 | Device and method for inspection of circuit board |
| CN201681141U (en) * | 2010-04-02 | 2010-12-22 | 徐宇震 | Combined density tester for printed circuit board |
| JP2015195272A (en) * | 2014-03-31 | 2015-11-05 | 新光電気工業株式会社 | Semiconductor device and semiconductor manufacturing method |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108709909A (en) * | 2018-06-25 | 2018-10-26 | 中国地质大学（武汉） | A kind of electrode assembly based on EIT non-destructive testing cement base tablets |
| CN108709909B (en) * | 2018-06-25 | 2023-06-30 | 中国地质大学（武汉） | Electrode device based on EIT nondestructive test cement-based flat plate |
| CN110426536A (en) * | 2019-07-29 | 2019-11-08 | 重庆伟鼎电子科技有限公司 | PCB conductive fabric measurement circuit plate |
| CN111014057A (en) * | 2019-12-05 | 2020-04-17 | 临海市锦铮机械有限公司 | Brain wave sensor resistance automatic detection machine |
| CN117288824A (en) * | 2023-11-23 | 2023-12-26 | 有研(广东)新材料技术研究院 | Test system based on silicon nanowire field effect sensor |
| CN117288824B (en) * | 2023-11-23 | 2024-03-19 | 有研(广东)新材料技术研究院 | Test system based on silicon nanowire field effect sensor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107202948B (en) | 2019-09-24 |
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