CN107195681A - A kind of two-dimensional semiconductor negative capacitance FET and preparation method - Google Patents
A kind of two-dimensional semiconductor negative capacitance FET and preparation method Download PDFInfo
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- CN107195681A CN107195681A CN201710388117.5A CN201710388117A CN107195681A CN 107195681 A CN107195681 A CN 107195681A CN 201710388117 A CN201710388117 A CN 201710388117A CN 107195681 A CN107195681 A CN 107195681A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
- H01L21/441—Deposition of conductive or insulating materials for electrodes
- H01L21/445—Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
Abstract
The invention discloses a kind of two-dimensional semiconductor negative capacitance FET and preparation method.Device architecture is followed successively by substrate, two-dimensional semiconductor, metal source and drain electrodes, ferroelectricity gate dielectric and metal gate electrode with negative capacitance effect from bottom to top.Transition-metal dichalcogenide two-dimensional semiconductor is prepared on substrate first, metal source and drain electrodes are prepared with electron beam lithography combination stripping technology, the ferroelectric thin film with negative capacitance effect is prepared on this structure, it is last to prepare metal gate electrode on the thin film, form the two-dimensional semiconductor negative capacitance fieldtron structure of ferroelectricity regulation and control.Other two-dimensional semiconductor negative capacitance fieldtron structures are different from, the metal ferroelectricity semiconductor structure can realize high performance negative capacitance fieldtron.Electrical testing result shows that the subthreshold swing of such devices is much smaller than 60mV/dec, breaches the Boltzmann limit, the features such as such two-dimensional semiconductor negative capacitance fieldtron is provided simultaneously with extremely low power dissipation, high-speed turnover.
Description
Technical field
The present invention relates to a kind of low dimension semiconductor electronic device of low-power consumption, refer specifically to a kind of regulate and control based on ferroelectric material
Two-dimensional semiconductor material negative capacitance FET and preparation method.
Background technology
With the development of integrated circuit technique, the technology has been widely used for each electronic product, due to integrated level
Improve constantly, while electronic product performance is improved, reduction power consumption is also the inexorable trend of electronic product development.Mole fixed
Under the traction of rule, traditional FET device size is constantly reduced, integrated level is improved constantly, so that the work(of chip
Consumption is continuously increased.However, spreading conduction mechanism because conventional field effect transistor is based on hot carrier, cause it can not overcome glass
The subthreshold swing (SS) of the graceful limit of Wurz, i.e. device can not break through 60mV/dec at room temperature.If therefore can not develop new
Mechanism and measure further reduce device subthreshold swing, integrated circuit, which will be unable to follow Moore's Law, to be continued to develop, more
It is important that its power consumption also can not be reduced further.Salahuddin and Datta were once pointed out, traditional field is replaced using ferroelectric material
Grid dielectric material in effect transistor, can effectively improve the surface potential of semiconductor channel in device, be larger than outer
Plus gate voltage, that is, realize voltage amplification effect.The voltage amplification effect is the negative capacitance effect that make use of ferroelectric material.Subthreshold value
The calculation formula of the amplitude of oscillation is：SS=dVG/d(logISD)=(dVG/dψS)/dψS/d(logISD)=(1+CS/Cins)(kT/q)
Ln10, wherein VGFor gate voltage, ISDFor source-drain current, ψSFor semiconductor channel surface potential, CSFor channel semiconductor electric capacity, Cins
For gate dielectric capacitance, k is Boltzmann constant, and T is temperature, and q is electron charge.From the formula, (kT/q) ln10
It is about 60mV/dec at room temperature, if therefore so that SS is critically depend on (1+C less than 60mV/decS/Cins) item.And it is traditional
C in field-effect transistorSAnd CinsAll it is on the occasion of causing (1+CS/Cins) it also can not can not just be less than 60mV/ less than 1, SS forever
dec.And the negative capacitance effect of ferroelectric material can make ferroelectric capacitor be negative value, i.e. CF<0.Therefore ferroelectric material is replaced into traditional grid
Dielectric substance, that is, use CFTo replace Cins, you can realize (1+CS/CF)<1, SS is less than 60mV/dec at room temperature.
In recent years, two-dimensional material is attracted attention due to its unique physical characteristic, and it is brilliant to be widely used field-effect
The research and development of body tube device.Graphene is the origin of two-dimensional material research and represents material, and zero band gap yet with graphene is special
Point causes it can not apply in logic electronics device.And with molybdenum disulfide (MoS2) be representative Transition-metal dichalcogenide
Band gap with 1-2eV, is that it is applied in logic electronics device there is provided good basis.Transition-metal dichalcogenide is same
Sample has low-dimensional characteristic, can greatly reduce device size, such as individual layer MoS2Thickness be only 0.7nm, Desai et al. just profits
Use MoS2Current FET device [Science smallest size of in the world is successfully prepared with nano wire (1nm)
354,99(2016)].And MoS2Mobility up to tens to cm up to a hundred2·V-1·s-1[Nature Nanotechnology
6,147(2011)].The excellent properties of above-mentioned two-dimensional semiconductor provide opportunity for it in the application of future logic electronic device.
The grid dielectric material of FET device based on two-dimensional semiconductor material is mostly silica
(SiO2), alundum (Al2O3) (Al2O3) and hafnium oxide (HfO2) etc..Its operation principle still spreads conduction mechanism for hot carrier.
Such devices are although realize small yardstick, but the power consumption that high integration triggers still can not be solved, and device subthreshold swing is still
60mV/dec can not be broken through, the problem that power consumption-performance-yardstick is mutually restricted equally is faced.For the foregoing reasons, for two dimension half
Application of the conductor material in logic electronics device, it is not only real in the urgent need to by the improvement in terms of structure and working mechanism
Existing small size device, device subthreshold swing can be more reduced to the full extent, the power consumption of final reduction device.
To solve the above problems, the present invention proposes a kind of two-dimensional semiconductor negative capacitance FET and preparation method.Should
Polyvinylidene fluoride ferroelectric polymers is replaced traditional grid dielectric material by device, utilizes polyvinylidene fluoride ferroelectric polymers
Negative capacitance effect, prepare two-dimensional material negative capacitance FET device.The two-dimensional material negative capacitance fieldtron
When source-drain current changes 4 orders of magnitude, subthreshold swing can as little as 24.3mV/dec.McGuire et al. was reported in 2016
The FET device [Applied Physics Letters 109,093101 (2016)] of similar structures.But with them
Structure it is different, the two-dimensional semiconductor material negative capacitance fieldtron that we are proposed is metal-ferroelectricity-semiconductor structure,
Simultaneously in polyvinylidene fluoride ferroelectric polymers thickness as little as 50nm, device still possesses the subthreshold value pendulum less than 60mV/dec
Width.
The content of the invention
The present invention proposes a kind of two-dimensional semiconductor negative capacitance FET and preparation method, is that two-dimensional material field-effect is brilliant
Body tube device is in future supper-fast, low-power logic field of electronic devices application blaze the trail.
Foregoing invention replaces ferroelectric material the conventional gate dielectric material in two-dimensional material FET device, profit
Regulate and control two-dimensional semiconductor material with the negative capacitance effect of ferroelectric material, form two-dimensional semiconductor negative capacitance fieldtron, can be real
Existing small size, supper-fast, low-power consumption logic electronics device.
The present invention refers to a kind of two-dimensional semiconductor negative capacitance FET and preparation method, it is characterised in that device architecture is certainly
It is lower and the last time is：
- substrate 1,
- oxide skin(coating) 2,
- two-dimensional semiconductor material 3,
- metal source 4, metal-drain 5,
- ferroelectricity the gate dielectric layer 6 with negative capacitance effect
- metal gate electrode 7,
Wherein substrate 1 is the silicon substrate of heavy doping, 0.3-0.5 millimeters of thickness；
Wherein oxide skin(coating) 2 is silica, 285 ± 5 nanometers of thickness；
Wherein two-dimensional semiconductor material 3 is Transition-metal dichalcogenide, thickness molecule from 1 layer to 10 layers；
Wherein metal source 4, metal-drain 5 are chromium and gold electrode, and chromium thickness is 5-10 nanometers, and golden thickness is received for 30-50
Rice；
Wherein the ferroelectricity gate dielectric layer 6 with negative capacitance effect is polyvinylidene fluoride ferroelectric polymer film, thickness
For 50-300 nanometers；
Wherein metal gate electrode 7 is aluminum metal electrode, and thickness is 9-12 nanometers.
The present invention refers to a kind of two-dimensional semiconductor negative capacitance FET and preparation method, it is characterised in that prepared by device include
Following steps：
1) prepared by oxide skin(coating)
Oxide skin(coating) silica is prepared by thermal oxidation method on heavily doped silicon substrate, thickness is 285 ± 5 nanometers.
2) Transition-metal dichalcogenide two-dimensional semiconductor is prepared and shifted
Transition-metal dichalcogenide two-dimensional semiconductor material is transferred to by oxide skin(coating) using mechanical stripping transfer method
Silica surface.
3) preparation of Transition-metal dichalcogenide two-dimensional semiconductor source-drain electrode
Using electron beam lithography, metal source 4 is prepared with reference to thermal evaporation metal and stripping technology, drain electrode 5 forms the back of the body
Grid structural transition metal chalcogenide compound two-dimensional material fet structure device；Electrode is chromium, gold, and thickness is respectively that 5-10 receives
Rice, 30-50 nanometers.
4) prepared by the polyvinylidene fluoride ferroelectricity gate dielectric layer with negative capacitance effect
On the backgate device prepared the polyvinylidene fluoride ferroelectricity with negative capacitance effect is prepared with spin coating method
Polymer poly vinylidene fluoride (P (VDF-TrFE)) ferroelectricity gate dielectric layer, and annealing 4-6 is small at a temperature of 110 DEG C -140 DEG C
When ensure ferroelectric thin film crystallization property and negative capacitance characteristic, should with negative capacitance effect polyvinylidene fluoride ferroelectricity grid electricity be situated between
50-300 nanometers of the thickness of matter layer film.
5) preparation of metal gate electrode
Metal gate electrode 7 is prepared on the ferroelectricity gate dielectric layer 6 with negative capacitance effect, is combined by thermal evaporation metal
Negtive photoresist ultraviolet photolithographic and argon ion etching method obtain the electrode pattern of special pattern structure.Metal gate electrode material is aluminium, thick
Spend for 9-12 nanometers.
Polyvinylidene fluoride ferroelectric polymers polyvinylidene fluoride (P (VDF-TrFE)) has this conclusion of negative capacitance effect
Early have been found to, the wink of the polarised direction upset 180 degree of the P (VDF-TrFE) after being polarized generally occurs for the negative capacitance effect
Between, the surface potential Ψ that may be such that two-dimensional semiconductor material in a flash at thisSMore than applied gate voltage VG.The voltage amplification effect
The carrier concentration and type of two-dimensional semiconductor raceway groove can be made to produce quick change, i.e. device within the very short time by opening
State is changed into OFF state, or is changed into ON state by OFF state.Due to the low-dimensional characteristic of two-dimensional material, device can be not only effectively reduced
Size, can also make device bias in less source and drain (<Normal work under 0.2V).The voltage's distribiuting signal of device operationally
Figure is as shown in Fig. 2 when source and drain bias is 0.1V, two-dimensional semiconductor channel material is molybdenum disulfide, P (VDF-TrFE) thickness
Shown in transfer characteristic curve such as Fig. 3 (a) and 3 (b) during for 50nm and 200nm, two-dimensional semiconductor channel material is two selenizing molybdenums,
Shown in transfer characteristic curve such as Fig. 3 (c) when P (VDF-TrFE) thickness is 300nm.
The advantage of patent of the present invention is：The present invention is based on two-dimensional semiconductor material FET device structure, profit
With polyvinylidene fluoride ferroelectric material polyvinylidene fluoride (P (VDF-TrFE)) negative capacitance effect, P (VDF-TrFE) is replaced
Grid dielectric material in conventional two-dimensional material field-effect transistor, prepares two-dimensional material negative capacitance fieldtron.Due to P
(VDF-TrFE) negative capacitance effect can produce enlarge-effect to additional grid voltage, further enhance to two-dimensional semiconductor material
The regulation and control of middle carrier and energy band, so as to greatly reduce the subthreshold swing of device, improve the switching rate of device, reduce
The overall power of device.In addition, device is also equipped with, high on-off ratio, stability are good, simple in construction, the features such as easily prepare.
Brief description of the drawings
Fig. 1 is two-dimensional semiconductor negative capacitance field-effect tube structure schematic cross-section.
In figure：1 substrate, 2 oxide skin(coating)s, 3 two-dimensional semiconductor materials, 4 metal sources, 5 metal-drains, 6 have negative capacitance
Ferroelectricity gate dielectric layer, 7 metal gate electrodes of effect.
Voltage's distribiuting schematic diagram when Fig. 2 two-dimensional semiconductor negative capacitances FET works.
In figure：(a) two-dimensional semiconductor negative capacitance field-effect tube structure schematic cross-section；(b) voltage of device operationally
Distribution schematic diagram, wherein VGGate voltage, VSDSource and drain bias voltage, ΨSTwo-dimensional semiconductor channel surface potential, CFWith negative capacitance
Ferroelectricity gate dielectric capacitance, the C of effectSTwo-dimensional semiconductor channel capacitance.
Fig. 3 two-dimensional semiconductor material negative capacitance FET application examples.
In figure：(a) it is 0.1V in source and drain bias, two-dimensional semiconductor channel material is molybdenum disulfide (MoS2), P (VDF-
TrFE transfer characteristic curve when thickness) is 50nm；(b) it is 0.1V in source and drain bias, two-dimensional semiconductor channel material is
MoS2, transfer characteristic curve when P (VDF-TrFE) thickness is 200nm；(c) it is 0.1V, two-dimensional semiconductor in source and drain bias
Channel material is two selenizing molybdenum (MoSe2), transfer characteristic curve when P (VDF-TrFE) thickness is 300nm.
Embodiment
Example 1：
The example 1 of the present invention is elaborated below in conjunction with the accompanying drawings：
The present invention have developed two-dimensional semiconductor negative capacitance FET.Utilize P (VDF-TrFE) ferroelectric polymer material
Negative capacitance effect produces amplification effect to additional grid voltage, strengthens the regulation and control to two-dimensional semiconductor material carrier and energy band, so that
The subthreshold swing of FET device can be effectively reduced, device upset speed is improved, reduces the overall work(of device
Consumption.
Comprise the following steps that：
1. substrate is selected
From 0.5 millimeter of thickness heavily-doped p-type silicon as substrate.
2. it is prepared by medium of oxides layer
By thermal oxidation method in surface of silicon, oxidation prepares 285 ± 5 nano thickness silica.
3. two-dimensional semiconductor material is prepared and transfer
With adhesive tape by Transition-metal dichalcogenide MoS2Crystal carry out mechanical stripping, after transfer them to SiO2/ Si substrates
On, MoS2Thickness selects 1 molecular layer.
4. it is prepared by source electrode, drain electrode
Source electrode, drain electrode figure are prepared using electronic beam photetching process；Metal electrode, chromium are prepared using thermal evaporation techniques
5 nanometers, 30 nanometers of gold；With reference to stripping means, stripping metal film obtains source electrode, drain electrode, and channel width is 1 micron.
5. it is prepared by the ferroelectricity gate dielectric layer with negative capacitance effect
On the backgate device prepared P (VDF-TrFE) ferroelectricity grid with negative capacitance effect are prepared with spin coating method
Dielectric layer, and annealing ensures P (VDF-TrFE) crystallization property and negative capacitance characteristic, P (VDF- for 4 hours at a temperature of 130 DEG C
TrFE) thickness of ferroelectricity functional layer film is 50 nanometers.
6. it is prepared by metal gate electrode
9 nano metal aluminium are prepared by thermal evaporation techniques first on ferroelectricity gate dielectric layer, then using negtive photoresist ultraviolet light
Carve and argon ion etching method obtains special pattern structure electrode figure.
7. electrical testing
Apply small constant 0.1V bias voltage, detection two-dimensional semiconductor MoS between source electrode and drain electrode2Raceway groove electricity
Stream, gate voltage scanning range is -13V to 13V, and gate voltage scanning direction is negative to arrive again from negative to positive.The transfer of measurement device is special
Property, wherein subthreshold swing is 51.2mV/dec, shown in such as Fig. 3 (a).It can be seen that, the source and drain bias voltage of the device is less than
0.2V, while subthreshold swing is less than 60mV/dec.As a result illustrate that a kind of two-dimensional semiconductor negative capacitance FET of the invention is adopted
With two-dimensional semiconductor material MoS2During for raceway groove, it is possible to achieve negative capacitance FET function, device can be effectively reduced sub-
The threshold value amplitude of oscillation, improves devices switch speed, reduces device power consumption.
Example 2：
The example 2 of the present invention is elaborated below in conjunction with the accompanying drawings：
The present invention have developed two-dimensional semiconductor negative capacitance FET.Utilize P (VDF-TrFE) ferroelectric polymer material
Negative capacitance effect produces amplification effect to additional grid voltage, strengthens the regulation and control to two-dimensional semiconductor material carrier and energy band, so that
The subthreshold swing of FET device can be effectively reduced, device upset speed is improved, reduces the overall work(of device
Consumption.
Comprise the following steps that：
5. substrate is selected
From 0.5 millimeter of thickness heavily-doped p-type silicon as substrate.
6. it is prepared by medium of oxides layer
By thermal oxidation method in surface of silicon, oxidation prepares 285 ± 5 nano thickness silica.
7. two-dimensional semiconductor material is prepared and transfer
With adhesive tape by Transition-metal dichalcogenide MoS2Crystal carry out mechanical stripping, after transfer them to SiO2/ Si substrates
On, MoS2Thickness selects 5 molecular layers.
8. it is prepared by source electrode, drain electrode
Source electrode, drain electrode figure are prepared using electronic beam photetching process；Metal electrode, chromium are prepared using thermal evaporation techniques
8 nanometers, 40 nanometers of gold；With reference to stripping means, stripping metal film obtains source electrode, drain electrode, and channel width is 1 micron.
5. it is prepared by the ferroelectricity gate dielectric layer with negative capacitance effect
On the backgate device prepared P (VDF-TrFE) ferroelectricity grid with negative capacitance effect are prepared with spin coating method
Dielectric layer, and annealing ensures P (VDF-TrFE) crystallization property and negative capacitance characteristic, P (VDF- for 5 hours at a temperature of 135 DEG C
TrFE) thickness of ferroelectricity functional layer film is 200 nanometers.
8. it is prepared by metal gate electrode
10 nano metal aluminium are prepared by thermal evaporation techniques first on ferroelectricity gate dielectric layer, then using negtive photoresist ultraviolet light
Carve and argon ion etching method obtains special pattern structure electrode figure.
9. electrical testing
Apply small constant 0.1V bias voltage, detection two-dimensional semiconductor MoS between source electrode and drain electrode2Raceway groove electricity
Stream, gate voltage scanning range is -30V to 30V, and gate voltage scanning direction is negative to arrive again from negative to positive.The transfer of measurement device is special
Property, wherein subthreshold swing is 29.6mV/dec, shown in such as Fig. 3 (b).It can be seen that, the source and drain bias voltage of the device is less than
0.2V, while subthreshold swing is less than 60mV/dec.As a result illustrate that a kind of two-dimensional semiconductor negative capacitance FET of the invention is adopted
With two-dimensional semiconductor material MoS2During for raceway groove, it is possible to achieve negative capacitance FET function, device can be effectively reduced sub-
The threshold value amplitude of oscillation, improves devices switch speed, reduces device power consumption.
Example 3：
The example 3 of the present invention is elaborated below in conjunction with the accompanying drawings：
The present invention have developed a kind of two-dimensional semiconductor negative capacitance FET.Utilize P (VDF-TrFE) ferroelectric polymers material
The negative capacitance effect of material produces amplification effect to additional grid voltage, strengthens the regulation and control to two-dimensional semiconductor material carrier and energy band,
So as to be effectively reduced the subthreshold swing of FET device, device upset speed is improved, the whole of device is reduced
Body power consumption.
Comprise the following steps that：
1. substrate is selected
From 0.5 millimeter of thickness heavily-doped p-type silicon as substrate.
2. it is prepared by medium of oxides layer
By thermal oxidation method in surface of silicon, oxidation prepares 285 ± 5 nano thickness silica.
3. two-dimensional semiconductor material is prepared and transfer
With adhesive tape by Transition-metal dichalcogenide MoSe2Crystal carry out mechanical stripping, after transfer them to SiO2/ Si is served as a contrast
On bottom, MoSe2Thickness selects 10 molecular layers.
4. it is prepared by source electrode, drain electrode
Source electrode, drain electrode figure are prepared using electronic beam photetching process；Metal electrode, chromium are prepared using thermal evaporation techniques
10 nanometers, 50 nanometers of gold；With reference to stripping means, stripping metal film obtains source electrode, drain electrode, and channel width is 5 microns.
5. it is prepared by the ferroelectricity gate dielectric layer with negative capacitance effect
On the backgate device prepared P (VDF-TrFE) ferroelectricity grid with negative capacitance effect are prepared with spin coating method
Dielectric layer, and annealing ensures P (VDF-TrFE) crystallization property and negative capacitance characteristic, P (VDF- for 6 hours at a temperature of 140 DEG C
TrFE) thickness of ferroelectricity functional layer film is 300 nanometers.
6. it is prepared by metal gate electrode
12 nano metal aluminium are prepared by thermal evaporation techniques first on ferroelectricity gate dielectric layer, then using negtive photoresist ultraviolet light
Carve and argon ion etching method obtains special pattern structure electrode figure.
7. electrical testing
Apply small constant 0.1V bias voltages, detection two-dimensional semiconductor MoSe between source electrode and drain electrode2Raceway groove electricity
Stream, the scanning range of gate voltage is -40V to 40V, and gate voltage scanning direction is negative to arrive again from negative to positive.The transfer of measurement device
The subthreshold swing of characteristic, wherein transfer characteristic curve is 24.3mV/dec, shown in such as Fig. 3 (c).It can be seen that, the device
Source and drain bias voltage is less than 0.2V, while subthreshold swing is less than 60mV/dec.As a result a kind of two-dimensional semiconductor of the invention is illustrated
Negative capacitance FET uses two-dimensional semiconductor material MoSe2, can during for raceway groove, it is possible to achieve negative capacitance FET function
Device subthreshold swing is effectively reduced, devices switch speed is improved, device power consumption is reduced.
Claims (2)
1. a kind of two-dimensional semiconductor negative capacitance FET, device architecture is followed successively by from bottom to top：Substrate (1), oxide skin(coating)
(2), Transition-metal dichalcogenide two-dimensional semiconductor material (3), metal source (4), metal-drain (5), with negative capacitance effect
The ferroelectricity gate dielectric layer (6) and metal gate electrode (7) answered, it is characterised in that：
Described substrate (1) is the silicon substrate of heavy doping；
Described oxide skin(coating) (2) is silica, 285 ± 5 nanometers of thickness；
Described two-dimensional semiconductor material (3) is Transition-metal dichalcogenide, 1 layer to 10 layers molecule of thickness；
Described metal source (4) and metal-drain (5) are chromium and gold electrode, and lower floor's chromium thickness is 5-10 nanometers, and upper strata gold is thick
Spend for 30-50 nanometers；
The described ferroelectricity gate dielectric layer (6) with negative capacitance effect is polyvinylidene fluoride ferroelectric polymer film, thickness
For 50-300 nanometers；
Described metal gate electrode (7) material is metallic aluminium, and thickness is 9-12 nanometers；
Added bias voltage is less than 0.2V between described metal source (4) and metal-drain (5), and subthreshold swing is less than
60mV/dec。
2. a kind of method for preparing two-dimensional semiconductor negative capacitance FET as claimed in claim 1, it is characterised in that including with
Lower step：
1) oxide skin(coating) (2) is prepared on substrate (1) by thermal oxidation method；
2) Transition-metal dichalcogenide two-dimensional semiconductor (3) is transferred to by oxide skin(coating) (2) using mechanical stripping transfer method
Surface；
3) electron beam lithography is used, metal source (4) is prepared with reference to thermal evaporation metal and stripping technology, is drained (5), is formed
Back grid structure Transition-metal dichalcogenide two-dimensional semiconductor fet structure device；
4) the polyvinylidene fluoride ferroelectricity with negative capacitance effect is prepared with spin coating method on the backgate device prepared to gather
Compound polyvinylidene fluoride ferroelectricity gate dielectric layer (6), and annealed 4-6 hours at a temperature of 130 DEG C -140 DEG C, it is ensured that ferroelectric thin
The crystallization property and negative capacitance characteristic of film；
5) metal gate electricity is prepared using electron beam evaporation alloying technology on the ferroelectricity gate dielectric layer (6) with negative capacitance effect
Pole (7), special pattern structure gate electrode figure is obtained with reference to negtive photoresist ultraviolet photolithographic technology, argon ion etching technology.
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