CN107644878B - Phase inverter and preparation method thereof - Google Patents
Phase inverter and preparation method thereof Download PDFInfo
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- CN107644878B CN107644878B CN201610591444.6A CN201610591444A CN107644878B CN 107644878 B CN107644878 B CN 107644878B CN 201610591444 A CN201610591444 A CN 201610591444A CN 107644878 B CN107644878 B CN 107644878B
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Abstract
The invention discloses a kind of phase inverters, include transistor and resistance, wherein, transistor includes: electric double layer gate dielectric layer, the gate electrode positioned at the side of electric double layer gate dielectric layer, and at least one lateral regulation end, channel, source electrode and drain electrode positioned at the other side of electric double layer gate dielectric layer, wherein, channel respectively with source electrode, drain contact；Also, lateral regulation end not with channel, source electrode and drain electrode in electrical communication；And one end of resistance and drain electrode are in electrical communication, and the other end is for applying supply voltage VDD；The gate electrode of transistor is as input terminal, and drain electrode is used as output end, and source electrode ground connection, at least one laterally regulates and controls end for applying fixed-bias transistor circuit Vm, fixed-bias transistor circuit VmFor adjusting the threshold voltage of transistor.The present invention can greatly reduce the operating voltage of phase inverter, reduce manufacturing cost, and can be realized the balance noise margin of phase inverter, improve the electrology characteristic of phase inverter.
Description
Technical field
The present invention relates to microelectronics technologies, and in particular to one kind have structure improved low-work voltage phase inverter and
Its production method.
Background technique
In recent years, logic circuit is widely used in various semiconductor integrated circuit, for example, dynamic random access memory
Device (Dynamic Random Access Memory, DRAM), static random access memory (Static Random Access
Memory, SRAM) and liquid crystal display (Liquid Crystal Display, LCD) etc..Wherein, phase inverter is logic circuit
Basis.
Conventional complementary type Metal-oxide-semicondutor (Complementary metal-oxide-semiconductor,
CMOS) phase inverter generallys use the realization of silicon channel, forms p-type channel by adulterating group-III element (such as boron) in silicon, or
N-type channel is formed by adulterating group-v element (such as phosphorus) in silicon.Due to mature si-substrate integrated circuit technology, this kind of phase inverter
It has been widely used in a large amount of electronic products.Further, in view of the comprehensive advantage of oxide semiconductor material, with its work
The star for just becoming electronics and information industry for the oxide thin film transistor of active channel layer, it is aobvious in transparent flexible plate of new generation
Show or the fields such as wearable, portable electronic product have extremely strong application prospect.
Although the better performances of oxide thin film transistor, field-effect electron mobility is up to 10~100cm2/ Vs, so
And still lack the matched oxide thin film transistor with p-type electric-conducting characteristic.Specifically, the p-type reported at present
The oxide thin film transistor not only poor (hole mobility < 1cm of device performance2/ Vs), stability is to be improved, and technique
Also relative complex.Therefore the electric property of the CMOS inverter circuit based on total oxygen compound is by extreme influence.Although people adopt
Some CMOS inverter circuits have been made in conjunction with N-shaped oxide transistor with p-type organic transistor, but p-type organic transistor
The problem of be the also smaller (< 1cm of mobility2/ Vs), stability is also poor.In view of this, people, which also use two kinds, has different thresholds
The N-shaped oxide thin film transistor of threshold voltage designs inverter circuit.
But the transistor that uses of above-mentioned phase inverter generallys use traditional gate dielectric membrane, unit-area capacitance compared with
It is small, usually less than tens nF/cm2, the operating voltage of device is larger (usually > 5V), therefore there are works for the inverter circuit designed
Make the relatively large disadvantage of voltage.In addition, the manufacture craft of this phase inverter needs multiple photolithographic masking steps, there are complexities
The shortcomings that height, high process cost.Disadvantages mentioned above limits above-mentioned phase inverter answering in low-power consumption and portable electronic product
With.
For example, the double gate type thin film transistors of tradition generally use up-down structure, that is, combine bottom-gate transistor and top-gated crystal
Pipe Yu Yiti, key position are needed using " bottom gate/gate medium/channel/gate medium/top-gated " this at least 5 layers of structure, channel layer
Two sides need in addition to be in electrical contact using conductive layer.This structure needs multistep photolithographic masking process, and process flow is complicated, often
Step is required to stringent Alignment Process, with high costs.
Summary of the invention
The purpose of the present invention is being directed to the deficiency of above-mentioned inverter technology status, propose a kind of low-work voltage phase inverter and
It makes new process, and phase inverter is low to the performance requirement of the transistor as driving unit, by the regulating effect of lateral electrodes,
Effectively realize the improvement of phase inverter electric property.The manufacture craft is simple and easy, can greatly reduce being fabricated to for phase inverter
This, is suitable for large area continuous production.
In one aspect of the invention, a kind of phase inverter is provided, includes: transistor and resistance, wherein
Transistor includes: electric double layer gate dielectric layer, the gate electrode positioned at the side of electric double layer gate dielectric layer, and is located at double
The lateral regulation end of at least one of the other side of electric layer gate dielectric layer, channel, source electrode and drain electrode, wherein channel respectively with source electrode,
Drain contact；Also, lateral regulation end not with channel, source electrode and drain electrode in electrical communication；And
In electrical communication, the other end is for applying supply voltage VDD for one end of resistance and drain electrode；
The gate electrode of transistor is as input terminal, and drain electrode is used as output end, and source electrode ground connection, at least one laterally regulates and controls end use
In application fixed-bias transistor circuit Vm, fixed-bias transistor circuit Vm is for adjusting the threshold voltage of transistor.
In a preference of the invention, transistor is bottom-gate-type transistor, wherein the conductive layer in insulating substrate is made
For positioned at the bottom gate thin film of electric double layer gate dielectric layer side.
In a preference of the invention, lateral regulation end is used for by adjusting fixed-bias transistor circuit Vm and bottom gate thin film
The input voltage of upper application realizes the control to the electric conductivity of channel by the electric double layer effect of electric double layer gate dielectric layer.
In a preference of the invention, channel layer is independently selected from the following group: indium zinc oxide, indium gallium zinc oxygen, indium tungsten oxygen
Compound, also, channel layer is with a thickness of 10nm~100nm.
In a preference of the invention, source electrode, drain electrode, lateral regulation end or bottom gate thin film are independently selected from the following group:
InZnO film, Ag film, Au film, Cu film, InSnO film.
In a preference of the invention, gate dielectric layer uses the solid electrolyte with electric double layer regulating effect, and
Independently selected from the following group: loose oxide dielectric film, sodium alginate film, chitosan film.
In a preference of the invention, the solid electrolyte with electric double layer regulating effect is independently selected from the following group:
Loose silicon oxide film and loose aluminum oxide film.
In a preference of the invention, the unit-area capacitance of the solid electrolyte with electric double layer regulating effect is
0.1~100 μ F/cm2.
In a preference of the invention, the quantity at the lateral regulation end that the transistor includes is 1-4.
In a preference of the invention, the area at the lateral regulation end is 0.1 times~the 10 of the channel area
Times.
In a preference of the invention, the spacing of the lateral regulation end and the channel is the 0.5 of channel dimensions
Times~10 times.
In another aspect of the invention, a kind of production method of phase inverter is provided comprising the steps of:
Step 1: insulating substrate is provided,
Step 2: forming bottom gate thin film on the surface of insulating substrate；
Step 3: electric double layer gate dielectric layer is formed on the surface of bottom gate thin film；
Step 4: patterned channel layer, patterned source electrode and drain electrode, Yi Jizhi are formed on electric double layer gate dielectric layer
A few patterned lateral regulation end, wherein channel respectively with source electrode, drain contact, it is lateral regulate and control end not with channel, source electrode
In electrical communication with drain electrode；
Step 5: one end of a resistance and drain electrode are connected.
In another aspect of the invention, a kind of electronic product is additionally provided, which includes above-mentioned phase inverter.
It should be understood that above-mentioned each technical characteristic of the invention and having in below (eg embodiment) within the scope of the present invention
It can be combined with each other between each technical characteristic of body description, to form a new or preferred technical solution.As space is limited, exist
This no longer tires out one by one states.
Detailed description of the invention
Fig. 1 is inverter structure schematic diagram according to an embodiment of the invention；
Fig. 2 a-2c is the electrology characteristic test result of prepared phase inverter according to the present invention；
Fig. 3 is the flow diagram of phase inverter production method according to an embodiment of the invention；
Fig. 4 is the circuit diagram of phase inverter according to the present invention.
In the drawings, 1: insulating substrate；2: bottom gate thin film；3: electric double layer gate dielectric layer；4a and 4b: first and second sides
To regulation end；5a: drain electrode；5b: source electrode；6: resistance；7: channel.VDD: the supply voltage of application；VIn: the electricity that input terminal applies
Pressure；VOut: the voltage of output end detection；Vm: the bias that regulation end applies.
Specific embodiment
The present inventor after extensive and in-depth study, has found to use electric double layer in the gate dielectric layer of the transistor of phase inverter
Solid electrolyte can reduce the operating voltage of phase inverter and have high voltage gain, significantly at the same time, in transistor
It the upper lateral regulation end of setting can be with the electric property of Effective Regulation transistor, so that regulation is anti-by regulating and controlling the application of end bias
The electric property of phase device.Therefore low-work voltage phase inverter proposed by the present invention and preparation method thereof, obtain low-work voltage,
High voltage gain simultaneously, further reduces cost of manufacture, biochemistry sensing, Low Power Consumption Portable electronic product and
Bionic product scope has broad application prospects.
The typical technical solution of the present invention includes:
For deposition conductive layer as bottom gate thin film, what is deposited in the bottom gate thin film has electric double layer regulation on an insulating substrate
The solid electrolyte of effect is as gate medium, and the patterned semiconductive thin film deposited on the gate medium is as thin film transistor (TFT)
Channel layer；The source of suitable position deposition, drain electrode on channel layer, while synchronous deposition mutually make by the patterned conductive layer of connection
Laterally to regulate and control end.The source electrode of thin film transistor (TFT) is grounded, by the drain electrode and resistor in series of transistor, in the another of resistor
Apply supply voltage V on endDD, using the gate electrode of transistor as input terminal, using the drain electrode of transistor as output end, while
The one or more being arranged on transistor applies fixed-bias transistor circuit on lateral regulation end, for regulating and controlling the electric property of phase inverter, from
And it obtains one and possesses structure improved low-work voltage phase inverter.
Phase inverter
The present invention provides a kind of phase inverters, include: transistor and resistance, wherein
Transistor includes: electric double layer gate dielectric layer, the gate electrode positioned at the side of electric double layer gate dielectric layer, and is located at double
The lateral regulation end of at least one of the other side of electric layer gate dielectric layer, channel, source electrode and drain electrode, wherein channel respectively with source electrode,
Drain contact；Also, lateral regulation end not with channel, source electrode and drain electrode in electrical communication；Also,
In electrical communication, the other end is for applying supply voltage V for one end of resistance and drain electrodeDD；
The gate electrode of transistor is as input terminal, and drain electrode is used as output end, and source electrode ground connection, at least one laterally regulates and controls end use
In application fixed-bias transistor circuit Vm, fixed-bias transistor circuit VmFor adjusting the threshold voltage of transistor.
In the present invention, fixed-bias transistor circuit VmFor regulating and controlling the electric property of transistor, more particularly regulate and control transistor
Threshold voltage, to further realize the balance noise margin of phase inverter.In other words, laterally regulation end is used to fix by adjusting
Bias VmAnd the input voltage applied in bottom gate thin film is realized by the electric double layer effect of electric double layer gate dielectric layer to channel
Electric conductivity control.
In order to make it easy to understand, the structural principle of phase inverter of the present invention is further illustrated below.Fig. 4 is a kind of reverse phase of the present invention
The circuit diagram of device example.It should be understood that protection scope of the present invention is not limited by the principle.
In the present invention, the thickness of channel layer is not particularly limited, usually 10nm~100nm.
Gate dielectric layer uses the solid electrolyte with electric double layer regulating effect, and can be independently selected from the following group: loose
Oxide dielectric film, sodium alginate film, chitosan film.More specifically, the solid electrolyte with electric double layer regulating effect
It can be independently selected from the following group: loose silicon oxide film and loose aluminum oxide film.
In the present invention, the unit-area capacitance of the above-mentioned solid electrolyte with electric double layer regulating effect is 0.1~100
μF/cm2。
In the present invention, input voltage VInRange can be -1V~3V, supply voltage VDDRange can be 0V~
3V。
In the present invention, the electric double layer solid electrolyte being related to has with properties, under the action of external electric field, solid-state electricity
Ion present in matter is solved to electrolyte/electrode interface or electrolyte/channel interface migration, and then in electrode side or channel one
Side induces one layer and electrical opposite, the identical carrier Guinier-Preston zone of the quantity of electric charge of ion, generates interface pair to induce in interface
Charge layer, the thickness of this interface electric double layer is minimum (~1nm), unit-area capacitance greatly (0.1~100 μ F/cm2),
Therefore this solid electrolyte has extremely strong electrostatic ability of regulation and control, the oxide using this solid electrolyte as gate medium
The operating voltage of thin film transistor (TFT) is minimum (< 2V).
Further, lateral regulation end is provided on bottom gate type oxide thin film transistor (TFT), it is inclined by laterally regulating and controlling end
The setting of pressure, the device performance of Effective Regulation thin film transistor (TFT), to facilitate the balance noise margin for realizing phase inverter.
In the present invention, laterally regulation end quantity is not particularly limited, and from practical application angle, quantity can be 1
~10, preferably 1-4；The area at lateral regulation end is not particularly limited, and from practical application angle, area should be channel
0.1 times of area~50 times should be 0.5 times~10 times of channel area as preferred area；Between lateral regulation end and channel
Away from being also not particularly limited, this is the electric double layer regulating effect based on electric double layer gate medium, from practical application angle, spacing
It should be 0.1 times~1000 times, preferably 0.5 times~10 times of channel dimensions.
It should be pointed out that in other preferences of the invention, it, can under conditions of being provided with multiple lateral regulation ends
To select one of them or several lateral regulation ends to apply fixed-bias transistor circuit.
In the present invention, insulating substrate is not particularly limited.Preferred insulating substrate includes (but being not limited to): being deposited with
Thermal oxide SiO2Monocrystalline substrate, glass substrate, plastic supporting base, paper substrate, ceramic substrate.
In the present invention, solid electrolyte is not particularly limited.The preferred solid state electrolysis with electric double layer regulating effect
Matter can be loose oxide dielectric film, sodium alginate film, chitosan film, or combinations thereof, preferably loose SiO2Film and
Loose Al2O3Film.
In the present invention, it is preferred to channel layer include (but being not limited to): indium-zinc oxide laminated film (InZnO), indium
Gallium zinc oxide laminated film (InGaZnO), indium tungsten oxide film (IWO), or combinations thereof.
In preference, source electrode, drain electrode, lateral regulation end or bottom gate thin film can be independently selected from the following groups: InZnO is thin
Film, Ag film, Au film, Cu film, InSnO film.
In the present invention, it is used using electron conducting oxide semiconductive thin film as thin film transistor (TFT) (TFTs) channel
Solid electrolyte with electric double layer regulating effect makes N-shaped oxide TFTs as gate medium.
According to the present invention, by the change of channel conductivity (or change of the resistance value of resistance), supply voltage is realized
VDDThe change of the method for salary distribution on resistance and channel.Therefore the resistance of channel becomes with gate electrode bias (or input voltage)
The region of change directly affects the voltage transfer curve of phase inverter, and there are voltages to change threshold voltage on phase inverter voltage transfer curve
(VInv), if VInv=VDD/ 2, that is, it can reach balance noise margin condition.But if channel resistance with gate electrode bias (or
Input voltage) changed region is bad, then it cannot achieve balance noise margin condition.Therefore lateral tune of the invention is combined
End technology is controlled, channel resistance may be implemented and change the Effective Regulation in region with gate electrode bias (or input voltage), thus
Realize balance noise margin condition.
Production method
The present invention also provides the production methods of phase inverter, it is comprised the steps of:
Step 1: insulating substrate is provided,
Step 2: forming bottom gate thin film on the surface of insulating substrate；
Step 3: electric double layer gate dielectric layer is formed on the surface of the bottom gate thin film；
Step 4: patterned channel layer, patterned source electrode and drain electrode are formed on the electric double layer gate dielectric layer, with
And at least one patterned lateral regulation end, wherein the channel respectively with the source electrode, the drain contact, the side
To regulation end not with the channel, the source electrode and drain electrode in electrical communication；
Step 5: one end of a resistance and the drain electrode are connected.
In the present invention, the manufacturing equipment that can select this field routine selects above-mentioned suitable material, by existing
Method prepares the phase inverter of the invention.Representative preparation method include (but being not limited to): sedimentation, sputtering method,
Thermal evaporation, or combinations thereof.
Using
Phase inverter of the invention can be applied to various different occasions.
The present invention provides a kind of electronic product, the electronic product includes phase inverter of the present invention.
Typically, the electronic product includes: various kinds of sensors (such as biochemical sensor), low-power consumption or portable
Electronic product and bionic product.
Main advantages of the present invention include:
1) present invention is using the solid electrolyte with electric double layer regulating effect as gate medium, unit-area capacitance pole
Greatly, therefore there are extremely strong electrostatic modulating properties, the operating voltage of oxide thin film transistor can be greatly reduced, so as to
To obtain the phase inverter of low-work voltage.
2) due to the super-strong capacitance coupling effect of solid electrolyte, while the source, drain electrode low to alignment request of element manufacturing
The process costs of element manufacturing can be greatly reduced with synchronization gain with lateral regulation end, continuously be given birth to suitable for large area
It produces.
3) lateral regulation end is provided on bottom gate type oxide thin film transistor (TFT), by laterally regulating and controlling setting for end bias
It sets, the device performance of Effective Regulation thin film transistor (TFT), therefore the electric property of phase inverter can be by laterally regulating and controlling end bias
It is arranged to regulate and control, to facilitate the balance noise margin for realizing phase inverter.
4) since the operating voltage of inverter circuit is low, biggish phase inverter voltage can be obtained under lower operating voltage
Gain, and the voltage transition region of voltage transmission curve characteristic is narrow, is conducive to improve phase inverter dynamic electrical characteristics.
5) in the present invention, transistor uses bottom grating structure combination side grid structure, and lateral regulation end can be synchronous with source electrode
Deposition, reduces the requirement of Alignment Process, and laterally the electric property of Effective Regulation bottom-gate-type transistor is capable of at regulation end, and
This function cannot achieve using the thin film transistor (TFT) of traditional gate medium.
Therefore, low-work voltage phase inverter production method provided by the invention significantly reduces the work of inverter circuit
Voltage improves the electrology characteristic of phase inverter, and manufacture craft is simple, low in cost, portable in biochemistry sensing, low-power consumption
The fields such as formula electronic product and bionic product have very wide application prospect.
Present invention will be further explained below with reference to specific examples.It should be understood that these embodiments are merely to illustrate the present invention
Rather than it limits the scope of the invention.In the following examples, the experimental methods for specific conditions are not specified, usually according to conventional strip
Part or according to the normal condition proposed by manufacturer.Unless otherwise stated, otherwise percentage and number are weight percent and weight
Number.
Embodiment: phase inverter 1
According to the phase inverter of the present embodiment, include: transistor and resistance, wherein
Transistor includes: electric double layer gate dielectric layer, the gate electrode positioned at the side of electric double layer gate dielectric layer, and is located at double
The lateral regulation end of at least one of the other side of electric layer gate dielectric layer, channel, source electrode and drain electrode, wherein channel respectively with source electrode,
Drain contact；Also, lateral regulation end not with channel, source electrode and drain electrode in electrical communication；Also,
In electrical communication, the other end is for applying supply voltage V for one end of resistance and drain electrodeDD；
The gate electrode of transistor is as input terminal, and drain electrode is used as output end, and source electrode ground connection, one of lateral regulation end is for applying
It is fixed bias Vm, fixed-bias transistor circuit VmFor adjusting the threshold voltage of transistor.
Specifically, fixed-bias transistor circuit VmFor regulating and controlling the electric property of transistor, more particularly regulate and control the threshold of transistor
Threshold voltage, to further realize the balance noise margin of phase inverter.In other words, laterally regulation end is fixed inclined for passing through adjusting
Press VmAnd the input voltage applied in bottom gate thin film is realized by the electric double layer effect of electric double layer gate dielectric layer to channel
The control of electric conductivity.
In the present embodiment, channel layer can be independently selected from the following group: indium zinc oxide, indium gallium zinc oxygen, indium tungsten oxide, and
And channel layer is with a thickness of 10nm~100nm.
Source electrode, drain electrode, lateral regulation end or bottom gate thin film can be independently selected from the following groups: InZnO film, Ag film, Au
Film, Cu film, InSnO film.
Gate dielectric layer uses the solid electrolyte with electric double layer regulating effect, and can be independently selected from the following group: loose
Oxide dielectric film, sodium alginate film, chitosan film.More specifically, the solid electrolyte with electric double layer regulating effect
It can be independently selected from the following group: loose silicon oxide film and loose aluminum oxide film.
The unit-area capacitance of the above-mentioned solid electrolyte with electric double layer regulating effect is 0.1~100 μ F/cm2。
Input voltage VInRange can be -1V~3V, supply voltage VDDRange can be 0V~3V.
In the present embodiment, the electric double layer solid electrolyte being related to has with properties, under the action of external electric field, solid-state
Ion present in electrolyte is migrated to electrolyte/electrode interface or electrolyte/channel interface, and then in electrode side or channel
Side induces one layer and electrical opposite, the identical carrier Guinier-Preston zone of the quantity of electric charge of ion, generates interface to induce in interface
Electric double layer, the thickness of this interface electric double layer is minimum (~1nm), unit-area capacitance greatly (0.1~100 μ F/
cm2), therefore this solid electrolyte has extremely strong electrostatic ability of regulation and control, using this solid electrolyte as gate medium
The operating voltage of oxide thin film transistor is minimum (< 2V).
In the present embodiment, lateral regulation end is provided on bottom gate type oxide thin film transistor (TFT).
By taking channel length and channel width are respectively 80 μm and 1mm as an example, the quantity that can choose lateral regulation end is 1
A, the size at lateral regulation end is 150 μ m 1mm, and the spacing that lateral regulation end distance drains is 300 μm.
Embodiment: phase inverter 2
The phase inverter of the present embodiment is essentially identical with above-described embodiment, repeats no more, and the difference between them is, this reality
The phase inverter of example is applied using bottom-gate-type transistor.
More specifically, as shown in Figure 1, the phase inverter of the present embodiment includes transistor and resistance 6, wherein
Transistor includes: electric double layer gate dielectric layer 3, the bottom gate thin film 2, Yi Jiwei positioned at the side of electric double layer gate dielectric layer
In the other side of electric double layer gate dielectric layer 3 the first side to regulation end 4a and the second side to regulation end 4b, channel layer 7, source electrode 5b
With drain electrode 5a, wherein channel layer 7 is contacted with source electrode 5b, drain electrode 5a respectively；Also, the first and second sides are equal to regulation end 4a, 4b
Not in electrical communication with channel layer 7, source electrode 5b and drain electrode 5a；Also,
In electrical communication, the other end is for applying supply voltage V by one end of resistance 6 and drain electrode 5aDD；
The bottom gate thin film 2 of transistor is used as input terminal, and drain electrode 5a is used as output end, and source electrode 5b is grounded, and the first side is to regulation
End 4a is for applying fixed-bias transistor circuit Vm, fixed-bias transistor circuit VmFor adjusting the threshold voltage of transistor.Have preferably in of the invention other
In example, the second side can also be used for fixed-bias transistor circuit V in application to regulation end 4bm。
In the present embodiment, fixed-bias transistor circuit VmFor regulating and controlling the electric property of transistor, specifically, being regulation transistor
Threshold voltage, to further realize the balance noise margin of phase inverter.In other words, the first and second sides to regulation end
4a, 4b are used for by adjusting fixed-bias transistor circuit VmAnd the input voltage applied in bottom gate thin film 2, pass through electric double layer gate dielectric layer 3
Electric double layer effect, realize the control to the electric conductivity of channel layer 7.
In the present embodiment, channel layer 7 can be independently selected from the following group: indium zinc oxide, indium gallium zinc oxygen, indium tungsten oxide,
Also, channel layer is with a thickness of 10nm~100nm.Source electrode 5b, drain electrode 5a, the first and second sides are electric to regulation end 4a, 4b or bottom gate
It pole 2 can be independently selected from the following group: InZnO film, Ag film, Au film, Cu film, InSnO film.Electric double layer gate dielectric layer
3 using the solid electrolytes with electric double layer regulating effect, and can be independently selected from the following group: loose oxide dielectric film,
Sodium alginate film, chitosan film.More specifically, can be independently selected from the following group: loose silicon oxide film and loose aluminium oxide
Film.The unit-area capacitance of the above-mentioned solid electrolyte with electric double layer regulating effect is 0.1~100 μ F/cm2.Input electricity
Press VInRange can be -1V~3V, supply voltage VDDRange can be 0V~3V.
In the present embodiment, fixed-bias transistor circuit VmThe first side is applied to regulation end 4a.In bottom-gate-type transistor, bottom gate thin film
The bias applied on 2, which is realized to the control of 7 electric conductivity of channel layer, to be realized by the electric double layer effect of electric double layer gate medium 3, when
Apply fixed-bias transistor circuit V on regulation end 4a in the first sidemWhen, the intensity of this electric double layer effect is effectively changed, therefore bottom gate
The performance of thin film transistor (TFT) is drifted about.
In the present embodiment, by the way that bottom gate type oxide thin film transistor (TFT) is connected with resistance 6, an ohmic load is obtained
Type phase inverter, and bottom gate type oxide thin film transistor (TFT) uses the solid electrolyte with electric double layer regulating effect as double electricity
Layer gate dielectric layer 3.Wherein, the source electrode 5b ground connection of transistor, drain electrode 5a connect with one end of resistance 6, apply on the other end of resistance 6
Power up voltage VDD, it regard the bottom gate thin film 2 of transistor as input terminal, using the drain electrode 5a of transistor as output end, meanwhile,
The first and second sides are provided on transistor to regulation end 4a, 4b, for regulating and controlling the electric property of phase inverter.
The structure of the bottom gate type oxide thin film transistor (TFT) of the present embodiment, can form in the following manner:
Conductive layer is deposited in insulating substrate 1, as bottom gate thin film 2.Hereafter, deposition has double electricity in insulating substrate 1
The solid electrolyte of layer regulating effect is as electric double layer gate dielectric layer 3.Then, figure is deposited on the electric double layer gate dielectric layer 3
The semiconductive thin film of change, as thin film transistor channel layer 7.Hereafter, source electrode 5b and drain electrode are deposited in the suitable position of channel layer 7
5a, meanwhile, deposit mutually disconnected conductive layer as the first and second sides to regulation end 4a, 4b.
Embodiment: the production method 1 of phase inverter
As shown in figure 3, the phase inverter production method of the present embodiment comprises the steps of:
Step 101: insulating substrate is provided,
Step 102: forming bottom gate thin film on the surface of insulating substrate；
Step 103: electric double layer gate dielectric layer is formed on the surface of bottom gate thin film；
Step 104: patterned channel layer, patterned source electrode and drain electrode are formed on electric double layer gate dielectric layer, and
At least one patterned lateral regulation end, wherein channel respectively with source electrode, drain contact, it is lateral regulate and control end not with channel, source
Pole and drain electrode are in electrical communication；
Step 105: one end of a resistance and drain electrode are connected.
In above-mentioned steps, channel layer can be independently selected from the following group: indium zinc oxide, indium gallium zinc oxygen, indium tungsten oxide, and
And channel layer is with a thickness of 10nm~100nm.Source electrode, drain electrode, lateral regulation end or bottom gate thin film are independently selected from the following group: InZnO
Film, Ag film, Au film, Cu film, InSnO film.Gate dielectric layer uses the solid state electrolysis with electric double layer regulating effect
Matter, and independently selected from the following group: loose oxide dielectric film, sodium alginate film, chitosan film, more specifically, can be only
It is on the spot selected from the group: loose silicon oxide film and loose aluminum oxide film.The above-mentioned solid state electrolysis with electric double layer regulating effect
The unit-area capacitance of matter is 0.1~100 μ F/cm2。
Embodiment: the production method 2 of phase inverter
Referring to Fig. 1, in the present embodiment, insulating substrate 1 uses glass substrate, and the conductive layer as bottom gate thin film 2 uses indium
Tin-oxide (InSnO), electric double layer gate dielectric layer 3 select chitosan film, source-drain electrode 5a and 5b and the first and second sides to
Regulate and control end 4a, 4b and use InZnO film, channel layer 7 uses InZnO film, and the resistance value of resistance 6 is 4M Ω.
The production method of phase inverter includes the following steps:
Step 1: insulating substrate 1 strictly being cleaned, it is clear that insulating substrate 1 is successively immersed alcohol, deionized water ultrasound
It washes 10 minutes, then uses deionized water repeated flushing, finally dried up with nitrogen gun stand-by.
Step 2: InSnO conductive membrane layer being deposited on 1 surface of insulating substrate using magnetron sputtering technique, as film crystal
The bottom gate thin film 2 of pipe；
Step 3: using solwution method, chitosan solution is spun on to the InSnO conductive film being deposited with as bottom gate thin film 2
Insulating substrate 1 on, up to chitosan film after drying, the electric double layer gate dielectric layer 3 as thin film transistor (TFT).
Step 4: using magnetron sputtering technique, be deposited on the substrate as 3 chitosan film of electric double layer gate dielectric layer
Deposit patterned InZnO channel layer 7, patterned source-drain electrode 5a and 5b, patterned first and second side to regulation end
4a and 4b.
Step 5: the resistance that a resistance value is 4M Ω being connected by conducting wire on drain electrode 5a.
Step 6: applying input voltage V in bottom gate thin film 2In, apply fixed-bias transistor circuit on resistance 6 as supply voltage
VDD, apply fixed-bias transistor circuit V on laterally regulation end 4am, output voltage V is detected on drain electrode 5aOut, so that obtaining one has
The inverter circuit at lateral regulation end, the performance of phase inverter can pass through VmBias is regulated and controled.
Embodiment: the production method 3 of phase inverter
Referring to Fig. 1, in the present embodiment, insulating substrate 1 uses paper substrate, and the conductive layer as bottom gate thin film 2 uses indium
Tin-oxide (InSnO), electric double layer gate dielectric layer 3 use loose SiO2Film, source-drain electrode (5a and 5b) and first and second
Lateral regulation end 4a, 4b use InZnO film, and channel layer 7 uses InZnO film, and the resistance value of resistance 6 is 10M Ω.
The production method of phase inverter includes the following steps:
Step 1: SiO is deposited on paper2Film carries out dividing processing, and acquisition is deposited with SiO2The paper of film is made
For insulating substrate 1.
Step 2: using magnetron sputtering technique, InSnO conductive membrane layer is deposited on 1 surface of insulating substrate, as film crystalline substance
The bottom gate thin film 2 of body pipe；
Step 3: using Plasma Enhanced Chemical Vapor Deposition, use silane and oxygen for reaction gas, the bottom of as
One layer of loose SiO is deposited on the InSnO conductive layer of gate electrode 22Film 3, as electric double layer gate dielectric layer 3.
Step 4: using magnetron sputtering technique, be deposited with the loose SiO as electric double layer gate dielectric layer 32The insulation of film 3
Deposited on substrate 1 patterned InZnO channel layer 7, patterned source-drain electrode 5a and 5b, patterned first and second side to
Regulate and control end 4a, 4b.
Step 5: the resistance that a resistance value is 10M Ω being connected by conducting wire on drain electrode 5a.
Step 6: applying input voltage V in bottom gate thin film 2In, apply fixed-bias transistor circuit on resistance 6 as supply voltage
VDD, apply fixed-bias transistor circuit V on laterally regulation end 4am, output voltage V is detected on drain electrode 5aOut, so that obtaining one has
The inverter circuit at lateral regulation end, the performance of phase inverter can pass through VmBias is regulated and controled.
Embodiment: the production method 4 of phase inverter
Referring to Fig. 1, in the present embodiment, insulating substrate 1 uses plastic supporting base, the conductive layer as bottom gate thin film 2 using gold,
Electric double layer gate dielectric layer 3 uses loose Al2O3Film, source-drain electrode 5a and 5b and the first and second sides are used to regulation end 4a, 4b
Ag film, channel layer 7 use InGaZnO film, and the resistance value of resistance 6 is 6M Ω.
The production method of phase inverter includes the following steps:
Step 1: insulating substrate 1 strictly being cleaned, successively immerses the substrate in alcohol, deionized water is cleaned by ultrasonic 10 points
Then clock uses deionized water repeated flushing, finally dried up with nitrogen gun stand-by.
Step 2: using thermal evaporation techniques, deposit Au film layer on 1 surface of insulating substrate, the bottom gate as thin film transistor (TFT)
Electrode 2；
Step 3: Plasma Enhanced Chemical Vapor Deposition is used, using trimethyl aluminium and oxygen as reaction gas, institute
It states trimethylaluminum gas and reaction cavity is brought into as carrier gas using Ar, deposited on the Au conductive membrane layer as bottom gate thin film 2
One layer of loose aluminum oxide film, as electric double layer gate dielectric layer 3；
Step 4: using magnetron sputtering technique, be deposited with the loose aluminium oxide as electric double layer gate dielectric layer 3
(Al2O3) film insulating substrate 1 on deposit patterned InGaZnO channel layer 7；
Step 5: use thermal evaporation techniques, deposited on channel layer 7 patterned Ag film as source, drain electrode 5a and
5b, while in loose aluminium oxide (Al2O3) the isolated graphical Ag film mutually not in electrical communication of synchronization gain on film, as the
One and second side to regulation end 4a and 4b；
Step 6: the resistance that a resistance value is 6M Ω being connected by conducting wire on drain electrode 5a.
Step 7: applying input voltage V in bottom gate thin film 2In, apply fixed-bias transistor circuit on resistance 6 as supply voltage
VDD, apply fixed-bias transistor circuit V on laterally regulation end 4am, output voltage V is detected on drain electrode 5aOut, so that obtaining one has
The inverter circuit at lateral regulation end, the performance of phase inverter can pass through VmBias is regulated and controled.
Test case
Below by taking Fig. 2 a-2c as an example, illustrate the test result of phase inverter of the invention.
Fig. 2 a-2c shows the electrology characteristic test result of phase inverter of the invention, and wherein electric double layer gate dielectric layer 3 is poly- for shell
Sugared film has extremely strong electric double layer regulating effect, therefore the bottom gate type oxide transistor prepared can be in lower voltage
Work (< 2V) under range, at the same by the first or second laterally regulate and control end 4a, 4b apply appropriate fixed-bias transistor circuit when, transistor
Threshold voltage can be by Effective Regulation, therefore the electric property of phase inverter can also be obtained by the way that this lateral regulation end is arranged
Effective Regulation.By laterally regulating and controlling the application of end bias, the phase inverter with balance noise margin is obtained.
In Fig. 2 a-2c, supply voltage VDDIt is set as 1V, load resistance is 4M Ω, input voltage VinScanning range-
0.6V~1V.As lateral regulation end voltage VmWhen being set as 1V, the transformation threshold voltage V of phase inverter voltage transmission curveInvFor
~-0.1V, the requirement of balance noise margin has not been reached yet in phase inverter at this time.As lateral regulation end voltage VmWhen being set as -2V,
The transformation threshold voltage V of phase inverter voltage transmission curveInvFor~0.5V (=VDD/ 2), phase inverter has reached balance noise at this time
The requirement of tolerance.Fig. 2 c, which gives, works as VmWhen being set as -2V, VOutWith VInVariation relation figure and VInWith VOutVariation relation
Figure, it will again be seen that working as VmWhen being set as -2V, phase inverter has reached the requirement of balance noise margin.Fig. 2 b gives voltage
Gain results, voltage gain is by VoutTo VinDerivation obtains, as | dVout/dVin|.Work as VmWhen being set as 1V, voltage gain is about
8.3；Work as VmWhen being set as -2V, voltage gain is about 9.5.It can be seen that phase inverter through the invention, can effectively reach
Noise margin is balanced, the lateral regulation end bias V in the present invention is thus also shownmThe beneficial effect of application.
Comparative example
When electric double layer gate dielectric layer 3 is changed to gate dielectric membrane (i.e. non-the consolidating with ionic conduction characteristic of high-compactness
State electrolyte, such as: thermal oxide SiO2Or densification Al2O3Film etc.) when, thin film transistor (TFT) (< 3V) nothing under lower voltage range
Method realizes effective transistor electricity performance, and grid voltage fails to the regulation of channel layer conductive capability, that is, in fixed channel
Under source, drain electrode bias condition, channel current does not change with the change of grid voltage.Simultaneously in prior art and technology
Under the conditions of, the lateral leadin of the thin film transistor (TFT) made on fine and close gate dielectric membrane laterally regulates and controls electrode 4, when laterally regulating and controlling
When applying different fixed-bias transistor circuits on electrode 4, the Effective Regulation to bottom gate thin film transistor performance cannot achieve.
Application prospect
Phase inverter of the invention is also significantly reduced and is produced into while obtaining low-work voltage, high voltage gain value
This, has important application prospect in fields such as biochemistry sensing, Low Power Consumption Portable electronic product and bionic products.
In claims and specification of this patent, relational terms such as first and second and the like are used merely to
It distinguishes one entity or operation from another entity or operation, without necessarily requiring or implying these entities or behaviour
There are any actual relationship or orders between work.Moreover, the terms "include", "comprise" or its any other variant
It is intended to non-exclusive inclusion, so that including that the process, method, article or equipment of a series of elements not only includes
Those elements, but also including other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic element of person's equipment.In the absence of more restrictions, the element limited by sentence " including one ", it is not excluded that
There is also other identical elements in the process, method, article or apparatus that includes the element.The claim of this patent
In book and specification, if it is mentioned that execute certain behavior according to certain element, then refer to the meaning for executing the behavior according at least to the element
Think, which includes two kinds of situations: executing the behavior according only to the element and the row is executed according to the element and other elements
For.
Although being shown and described to the present invention by referring to certain preferred embodiments of the invention, this
The those of ordinary skill in field should be understood that can to it, various changes can be made in the form and details, without departing from the present invention
Spirit and scope.
Claims (11)
1. a kind of phase inverter is, characterized by comprising: transistor and resistance, wherein
The transistor includes: electric double layer gate dielectric layer, the gate electrode positioned at the side of the electric double layer gate dielectric layer, Yi Jiwei
At least one lateral regulation end, channel, source electrode and drain electrode in the other side of the electric double layer gate dielectric layer, wherein the ditch
Road respectively with the source electrode, the drain contact；Also, the lateral regulation end not with the channel, the source electrode and leakage
Pole is in electrical communication；And
In electrical communication, the other end is for applying supply voltage V for one end of the resistance and the drain electrodeDD；
The gate electrode of the transistor is as input terminal, and the drain electrode is used as output end, the source electrode ground connection, described at least one
Lateral regulation end is for applying fixed-bias transistor circuit Vm, the fixed-bias transistor circuit VmFor adjusting the threshold voltage of transistor.
2. phase inverter as described in claim 1, which is characterized in that the transistor is bottom-gate-type transistor, wherein insulation lining
Conductive layer on bottom is as the bottom gate thin film for being located at electric double layer gate dielectric layer side.
3. phase inverter as claimed in claim 2, which is characterized in that the lateral regulation end is used for inclined by adjusting the fixation
Press VmAnd the input voltage applied in the bottom gate thin film is realized by the electric double layer effect of the electric double layer gate dielectric layer
Control to the electric conductivity of the channel.
4. phase inverter as described in claim 1, which is characterized in that the channel layer is independently selected from the following group: indium zinc oxide, indium
Gallium zinc oxygen, indium tungsten oxide, also, the channel layer is with a thickness of 10nm~100nm.
5. phase inverter as described in claim 1, which is characterized in that the source electrode, drain electrode, lateral regulation end are independently selected under
Group:
InZnO film, Ag film, Au film, Cu film, InSnO film.
6. phase inverter as claimed in claim 2 or claim 3, which is characterized in that the bottom gate thin film is independently selected from the following group:
InZnO film, Ag film, Au film, Cu film, InSnO film.
7. phase inverter as described in claim 1, which is characterized in that the gate dielectric layer is used with electric double layer regulating effect
Solid electrolyte, and independently selected from the following group: loose oxide dielectric film, sodium alginate film, chitosan film.
8. phase inverter as claimed in claim 7, which is characterized in that the solid electrolyte with electric double layer regulating effect
Independently selected from the following group: loose silicon oxide film and loose aluminum oxide film.
9. phase inverter as claimed in claim 8, which is characterized in that the solid electrolyte with electric double layer regulating effect
Unit-area capacitance be 0.1~100 μ F/cm2。
10. a kind of production method of phase inverter, which is characterized in that comprise the steps of:
Step 1: insulating substrate is provided,
Step 2: forming bottom gate thin film on the surface of insulating substrate；
Step 3: electric double layer gate dielectric layer is formed on the surface of the bottom gate thin film；
Step 4: patterned channel layer, patterned source electrode and drain electrode, Yi Jizhi are formed on the electric double layer gate dielectric layer
A few patterned lateral regulation end, wherein the channel respectively with the source electrode, the drain contact, the lateral tune
Control end not with the channel, the source electrode and drain electrode in electrical communication；
Step 5: one end of a resistance and the drain electrode are connected.
11. a kind of electronic product, which is characterized in that the electronic product includes such as reverse phase as claimed in any one of claims 1 to 5
Device.
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| CN109360857A (en) * | 2018-08-15 | 2019-02-19 | 南昌工程学院 | A kind of degradable self-supporting film transistor device and preparation method thereof |
| CN109950321B (en) * | 2019-03-25 | 2022-02-11 | 暨南大学 | P-type field effect transistor based on tungsten oxide and preparation method thereof |
| CN113013253B (en) * | 2021-02-24 | 2022-06-28 | 中国科学院宁波材料技术与工程研究所 | P-type thin film transistor, preparation method thereof and phase inverter |
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| CN101681927A (en) * | 2007-05-18 | 2010-03-24 | 佳能株式会社 | Inverter manufacturing method and inverter |
| CN203826387U (en) * | 2014-03-28 | 2014-09-10 | 长安大学 | GaN-based ultrathin barrier enhancement/depletion-mode inverter and ring oscillation |
| CN104835835A (en) * | 2015-03-18 | 2015-08-12 | 南京华印半导体有限公司 | Solid electrolyte film transistor and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101681927A (en) * | 2007-05-18 | 2010-03-24 | 佳能株式会社 | Inverter manufacturing method and inverter |
| CN203826387U (en) * | 2014-03-28 | 2014-09-10 | 长安大学 | GaN-based ultrathin barrier enhancement/depletion-mode inverter and ring oscillation |
| CN104835835A (en) * | 2015-03-18 | 2015-08-12 | 南京华印半导体有限公司 | Solid electrolyte film transistor and manufacturing method thereof |
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