CN107039242B - Core-shell heterostructure germanium-silicon nanowire and controllable preparation method and application thereof - Google Patents

Core-shell heterostructure germanium-silicon nanowire and controllable preparation method and application thereof Download PDF

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CN107039242B
CN107039242B CN201710140216.1A CN201710140216A CN107039242B CN 107039242 B CN107039242 B CN 107039242B CN 201710140216 A CN201710140216 A CN 201710140216A CN 107039242 B CN107039242 B CN 107039242B
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silicon
germanium
nanowire
core
silicon nanowire
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CN107039242A (en
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夏金松
李毅
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Wuhan Crystal Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02603—Nanowires
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium

Abstract

The invention discloses a core-shell heterostructure germanium-silicon nanowire and a controllable preparation method and application thereof, wherein the position and the size of the nanowire are defined by high-precision electron beam lithography and dry etching, so that the problem of random nucleation growth in the traditional growth method is avoided; the invention introduces a method for reducing the silicon nanowire by using high-temperature silicon oxide, and further reduces the transverse size of the germanium-silicon nanowire; by adjusting the deposition rate ratio of germanium to silicon, the germanium component can be adjusted randomly within the range of 0-100%, and the faster the deposition rate of silicon is, the lower the germanium component is; conversely, the higher the germanium composition; the controllable preparation method of the core-shell heterostructure germanium-silicon nanowire provided by the invention has the advantages of good controllability, simple process steps, high repeatability and the like, and has good application prospects in the directions of nanowire junction-free transistor devices, silicon-based light emitting devices, single-electron device devices and the like in the field of semiconductor manufacturing.

Description

Core-shell heterostructure germanium-silicon nanowire and controllable preparation method and application thereof
Technical Field
The invention relates to the technical field of semiconductor device nano processing, in particular to a core-shell heterostructure germanium-silicon nanowire and a controllable preparation method and application thereof.
Background
Germanium-silicon nanowires have two-dimensional quantum-confined nanoscale structures, and are gradually becoming a research hotspot in the field of integrated optoelectronics in recent years. The germanium-silicon nanowire has the advantages of unique light emission and light absorption characteristics of communication bands, quantum confinement effect, coulomb blocking effect, good carrier mobility, compatibility with a CMOS (complementary metal oxide semiconductor) process and the like, and has very wide application prospect. For example, the germanium-silicon nanowire can be used for manufacturing an on-chip integrated light source, a photodetector and a single-electron transistor, and can also be used for manufacturing a junction-free nanowire transistor, an integrated array sensor and other key devices in the future integrated optoelectronic field.
The preparation of the traditional germanium-silicon nanowire depends on a vapor phase epitaxy deposition method. Under the catalysis of the nano-gold particles, the growth of the nano-wire is realized by controlling the proportion of the silane and the germane and the reaction temperature. The method is characterized in that the cross section size of the nanowire is determined by the size of gold particles, and the high-quality germanium-silicon multilayer nested coaxial heterogeneous nanowire structure can be realized. The germanium-silicon nanowire grows upwards in a vertical mode, the growth direction and the position are random, and therefore the grown germanium-silicon nanowire is not compatible with the planar process of semiconductor micro-nano processing easily.
In a word, although the existing growth preparation processes of germanium-silicon nanowires are developed relatively mature, the fully controllable preparation of the germanium-silicon nanowires cannot be realized, the key parameters such as the position, the size, the components and the like of each nanowire cannot be accurately controlled, and great process difficulty is brought to the processing of semiconductor devices based on the germanium-silicon nanowires.
Disclosure of Invention
In view of the above, the present invention provides a controllable preparation method of a core-shell heterostructure germanium-silicon nanowire, which can accurately control the size and position of the nanowire, effectively reduce the lateral dimension and improve the germanium component, and has the advantages of good controllability, simple process steps, high repeatability, and convenience in accurately preparing a semiconductor device based on the germanium-silicon nanowire.
The technical scheme of the invention is realized as follows: on one hand, the invention provides a controllable preparation method of a core-shell heterostructure germanium-silicon nanowire, which comprises the following steps,
a. cleaning the silicon substrate;
b. coating a layer of electronic resist on the surface of the silicon substrate, and exposing a required silicon nanowire structural pattern on the electronic resist by an electronic beam lithography technology;
c. transferring the structure diagram of the silicon nanowire onto a silicon substrate by adopting dry etching to obtain a sample;
d. removing the residual electronic resist on the sample;
e. oxidizing and annealing, so that oxygen reacts with the silicon to form silicon oxide;
f. removing the silicon oxide formed by oxidation in the step e, suspending the middle part of the silicon nanowire, and cleaning the sample;
g. wrapping a layer of germanium-silicon alloy outside the silicon nanowire obtained in the step f to form a germanium-silicon nanowire core-shell heterostructure;
h. and removing the germanium-silicon alloy deposited on the oxygen burying layer to obtain the core-shell heterostructure germanium-silicon nanowire.
On the basis of the above technical solution, preferably, the SOI silicon substrate is adopted in the step a, and includes a silicon substrate, a buried oxide layer, and a top silicon three-layer structure from bottom to top.
On the basis of the above technical solution, preferably, the electronic resist in step b is SAL601, HSQ, PMMA or ZEP 520.
On the basis of the above technical solution, preferably, the cross-sectional shape of the silicon nanowire structural pattern in the step b is a barbell shape with a thin middle and thick two ends.
On the basis of the above technical solution, preferably, CCl is adopted for the dry etching in the step c4、BC13、CHF3、SF6Or C4F8Reactive Ion Etching (RIE), Inductively Coupled Plasma (ICP) etching or Electron Cyclotron Resonance (ECR) etching method is adopted for etching gas.
On the basis of the above technical scheme, preferably, the oxidation in the step e adopts dry oxygen oxidation or wet oxidation, the annealing is performed in a nitrogen environment, and the oxidation and annealing temperatures are 700 ℃ to 1200 ℃.
On the basis of the above technical solution, preferably, in step f and step h, hydrofluoric acid is used to etch away the oxidized silicon oxide and the germanium-silicon alloy deposited on the buried oxide layer.
On the basis of the above technical scheme, preferably, in the step e, the germanium-silicon alloy is wrapped by adopting a molecular beam epitaxial growth method MBE or an ultrahigh vacuum vapor deposition method UHV-CVD.
In a second aspect, the invention provides a core-shell heterostructure germanium-silicon nanowire prepared by the method of the first aspect of the invention.
In a second aspect, the core-shell heterostructure germanium-silicon nanowire prepared by the method of the first aspect of the invention is applied to a semiconductor device.
Compared with the prior art, the core-shell heterostructure germanium-silicon nanowire and the controllable preparation method and application thereof have the following beneficial effects:
(1) the position and the size of the nanowire are defined by adopting high-precision electron beam lithography and dry etching, so that the problem of random nucleation growth in the traditional growth method is avoided; the invention introduces a method for reducing the silicon nanowire by using high-temperature silicon oxide, and further reduces the transverse size of the germanium-silicon nanowire; by adjusting the deposition rate ratio of germanium to silicon, the germanium component can be adjusted randomly within the range of 0-100%, and the faster the deposition rate of silicon is, the lower the germanium component is; conversely, the higher the germanium composition;
(2) as optimization, silicon oxide on the surface of the silicon nanowire must be completely corroded by hydrofluoric acid, so that the prepared core-shell heterostructure germanium-silicon nanowire has high lattice quality, and the periphery of the silicon nanowire is wrapped by germanium-silicon alloy;
(3) in general, the controllable preparation method of the core-shell heterostructure germanium-silicon nanowire provided by the invention has the advantages of good controllability, simple process steps, high repeatability and the like, and has good application prospects in the directions of nanowire junction-free transistor devices, silicon-based light emitting devices, single-electron device devices and the like in the field of semiconductor manufacturing.
Drawings
FIG. 1 is a flow chart of an implementation of a controllable preparation method of a core-shell heterostructure germanium-silicon nanowire of the present invention;
FIG. 2-1 is a schematic view of the SOI substrate structure of example 1;
FIG. 2-2 is a schematic left-view structural diagram of the sample obtained in step a of example 1;
FIGS. 2 to 3 are schematic left-view structural diagrams of samples obtained in step b of example 1;
FIGS. 2 to 4 are schematic left-view structural diagrams of samples obtained in step c of example 1;
FIGS. 2 to 5 are schematic top views of the structures of the samples obtained in step d of example 1;
FIGS. 2 to 6 are schematic front views of the structures of the samples obtained in step d of example 1;
FIGS. 2 to 7 are schematic left-view structural diagrams of the samples obtained in step e of example 1;
FIGS. 2 to 8 are schematic front views of the structures of the samples obtained in step f of example 1;
FIGS. 2-9 are schematic front views of the structures of the samples obtained in step g of example 1;
FIGS. 2 to 10 are schematic front views of the samples obtained in step h of example 1.
Detailed Description
The technical solutions of the present invention will be described clearly and completely below with reference to embodiments of the present invention, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Example 1
Preparing core-shell heterostructure germanium-silicon nanowires with different sizes on an SOI substrate.
As shown in fig. 2-1, the SOI substrate selected in this embodiment is sequentially composed of a silicon substrate (not shown), a buried oxide layer with a thickness of 2000nm, and a top silicon layer with a thickness of 70nm from bottom to top, and the substrate is cleaned by an RCA process.
Step a, as shown in fig. 2-2, coating HSQ paste with a concentration of 3.6% on the SOI substrate at 4000rpm, and baking for 4min at 150 ℃ using a hot plate.
And step b, as shown in fig. 2-3, forming a barbell-shaped silicon nanowire structural pattern with a cross section shape of a thin middle part and thick two ends in the HSQ by adopting electron beam direct writing exposure and development. Referring to fig. 2 to 5, the designed widths of the middle portions of the silicon nanowire structure patterns are 30nm, 40nm, 50nm and 60nm, respectively, and the silicon nanowire structure patterns of each width have different lengths of 0.5 μm, 1 μm, 1.5 μm and 2 μm, respectively. The area of the square blocks at the two end parts of the pattern of the silicon nanowire structure is 20 x 20 mu m2. The electron beam exposure adopts an EBPG5000+ electron beam lithography system of VISTEC company, and adopts 100KeV accelerating voltage, 130pa electron beam current and 800 mu C/cm2Exposure dose. Development was carried out with ZX238 developer for 180s at room temperature.
Step C, as shown in FIGS. 2-4, using the HSQ electronic resist pattern as a mask, using C4F8/SF6Etching gas and Inductively Coupled Plasma (ICP) etching method are used for etching the top silicon of the SOI substrate to the etching depth of 65nm, so that the pattern is transferred to the top layer of the SOI substrateOn silicon.
And d, removing the residual electronic resist on the sample to obtain the sample shown in figures 2-5 and 2-6.
And e, putting the sample in a high-temperature tube furnace at 900 ℃, introducing oxygen to oxidize the surface of the sample, and introducing nitrogen to anneal the surface of the sample, wherein the oxidation time is 30min, and the annealing time is 20 min. The tube furnace was then cooled to room temperature to obtain the samples shown in FIGS. 2-7.
And f, soaking the SOI substrate in a hydrofluoric acid solution, corroding silicon oxide on the surface of the silicon nanowire, and suspending the middle part of the silicon nanowire to obtain a sample shown in the figures 2-8. The soaking time is not suitable to be too long so as to prevent the buried oxide layer below the square blocks used for supporting at the two ends of the silicon nanowire from being completely corroded. The silicon oxide on the surface of the silicon nanowire must be completely corroded by hydrofluoric acid, so that the prepared core-shell heterostructure germanium-silicon nanowire has high lattice quality, and the periphery of the silicon nanowire is wrapped by the germanium-silicon alloy.
And g, cleaning the substrate by using an RCA (Rolling circle amplification) process, then sending the SOI substrate into a molecular beam epitaxial growth system, firstly growing 10nm silicon at 450 ℃ to serve as a buffer layer, then epitaxially growing a Ge0.1Si0.9 quantum well with the thickness of 15nm, and finally covering 5nm silicon to obtain the sample shown in the figures 2-9. The molecular beam epitaxy system used was the Eva-32 molecular beam epitaxy system from Riber, France.
And h, soaking the grown SOI substrate in hydrofluoric acid solution to strip the germanium-silicon alloy directly grown on the buried oxide layer, thereby obtaining the sample shown in the figures 2-10. Similarly, the soaking time is not suitable to be too long, so as to prevent the buried oxide layer below the square blocks used for supporting at the two ends of the silicon nanowire from being completely corroded.
Through the steps, the germanium-silicon nanowire with the core-shell heterostructure can be prepared.
Example 2
Preparing core-shell heterostructure germanium-silicon nanowires with different sizes on an SOI substrate.
The SOI substrate selected in this embodiment is sequentially composed of a silicon substrate, a buried oxide layer with a thickness of 2000nm, and a top silicon layer with a thickness of 70nm from bottom to top, and the substrate is cleaned by an RCA process.
Step a, coating HSQ glue with the concentration of 3.6% on the SOI substrate, wherein the coating rotating speed is 4000rpm, and drying for 4min at 150 ℃ by adopting a hot plate.
And b, forming a barbell-shaped silicon nanowire structural pattern with a cross section shape of a thin middle part and thick two ends in the HSQ by adopting electron beam direct writing exposure and development. The design widths of the middle portions of the silicon nanowire structure patterns are 30nm, 40nm, 50nm and 60nm, respectively, and the silicon nanowire structure patterns of each width have different lengths of 0.5 μm, 1 μm, 1.5 μm and 2 μm, respectively. The area of the square blocks at the two end parts of the pattern of the silicon nanowire structure is 20 x 20 mu m2. The electron beam exposure adopts an EBPG5000+ electron beam lithography system of VISTEC company, and adopts 100KeV accelerating voltage, 130pa electron beam current and 800 mu C/cm2Exposure dose. Development was carried out with ZX238 developer for 180s at room temperature.
Step c, using HSQ electronic resist pattern as mask and CCl4Etching gas and Electron Cyclotron Resonance (ECR) etching methods are used for etching the top silicon of the SOI substrate to the etching depth of 65nm, and therefore the pattern is transferred to the top silicon of the SOI.
And d, removing the residual electronic resist on the sample.
And e, placing the sample in a high-temperature tube furnace at 700 ℃, introducing oxygen to oxidize the surface of the sample, and introducing nitrogen to anneal the surface of the sample, wherein the oxidation time is 30min, and the annealing time is 20 min. The tube furnace was then cooled to room temperature.
And f, soaking the SOI substrate in a hydrofluoric acid solution, corroding silicon oxide on the surface of the silicon nanowire, and suspending the middle part of the silicon nanowire.
And g, cleaning the substrate by using an RCA (radio-controlled amplification) process, then sending the SOI substrate into a molecular beam epitaxial growth system, firstly growing 10nm silicon at 450 ℃ to serve as a buffer layer, then epitaxially growing a Ge0.1Si0.9 quantum well with the thickness of 15nm, and finally covering with 5nm silicon. The molecular beam epitaxy system used was the Eva-32 molecular beam epitaxy system from Riber, France.
And h, soaking the grown SOI substrate in hydrofluoric acid solution to strip the germanium-silicon alloy directly grown on the oxygen burying layer.
Through the steps, the germanium-silicon nanowire with the core-shell heterostructure can be prepared.
Example 3
Preparing core-shell heterostructure germanium-silicon nanowires with different sizes on an SOI substrate.
The SOI substrate selected in this embodiment is sequentially composed of a silicon substrate, a buried oxide layer with a thickness of 2000nm, and a top silicon layer with a thickness of 70nm from bottom to top, and the substrate is cleaned by an RCA process.
Step a, coating HSQ glue with the concentration of 3.6% on the SOI substrate, wherein the coating rotating speed is 4000rpm, and drying for 4min at 150 ℃ by adopting a hot plate.
And b, forming a barbell-shaped silicon nanowire structural pattern with a cross section shape of a thin middle part and thick two ends in the HSQ by adopting electron beam direct writing exposure and development. The design widths of the middle portions of the silicon nanowire structure patterns are 30nm, 40nm, 50nm and 60nm, respectively, and the silicon nanowire structure patterns of each width have different lengths of 0.5 μm, 1 μm, 1.5 μm and 2 μm, respectively. The area of the square blocks at the two end parts of the pattern of the silicon nanowire structure is 20 x 20 mu m2. The electron beam exposure adopts an EBPG5000+ electron beam lithography system of VISTEC company, and adopts 100KeV accelerating voltage, 130pa electron beam current and 800 mu C/cm2Exposure dose. Development was carried out with ZX238 developer for 180s at room temperature.
Step c, using HSQ electronic resist pattern as mask, adopting BC13Etching gas, Reactive Ion Etching (RIE) method and etching depth of the top silicon of the SOI substrate are 65nm, so that the pattern is transferred to the top silicon of the SOI.
And d, removing the residual electronic resist on the sample.
And e, placing the sample in a high-temperature tube furnace at 1200 ℃, introducing oxygen to oxidize the surface of the sample, and introducing nitrogen to anneal the surface of the sample, wherein the oxidation time is 30min, and the annealing time is 20 min. The tube furnace was then cooled to room temperature.
And f, soaking the SOI substrate in a hydrofluoric acid solution, corroding silicon oxide on the surface of the silicon nanowire, and suspending the middle part of the silicon nanowire.
And g, cleaning the substrate by using an RCA (radio-controlled amplification) process, then sending the SOI substrate into a molecular beam epitaxial growth system, firstly growing 10nm silicon at 450 ℃ to serve as a buffer layer, then epitaxially growing a Ge0.1Si0.9 quantum well with the thickness of 15nm, and finally covering with 5nm silicon. The molecular beam epitaxy system used was the Eva-32 molecular beam epitaxy system from Riber, France.
And h, soaking the grown SOI substrate in hydrofluoric acid solution to strip the germanium-silicon alloy directly grown on the oxygen burying layer.
Through the steps, the germanium-silicon nanowire with the core-shell heterostructure can be prepared.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (8)

1. A controllable preparation method of a germanium-silicon nanowire with a core-shell heterostructure is characterized by comprising the following steps: which comprises the following steps of,
a. cleaning a silicon substrate, wherein the silicon substrate adopts an SOI silicon substrate and comprises a silicon substrate, a buried oxide layer and a top silicon three-layer structure from bottom to top;
b. coating a layer of electron beam resist on the surface of the silicon substrate, and exposing a required silicon nanowire structural pattern on the electron beam resist by using an electron beam lithography technology;
c. transferring the structure diagram of the silicon nanowire onto a silicon substrate by adopting dry etching to obtain a sample;
d. removing the residual electron beam resist on the sample;
e. oxidizing and annealing, so that oxygen reacts with the silicon to form silicon oxide;
f. e, corroding the silicon oxide formed by oxidation in the step e by using hydrofluoric acid, suspending the middle part of the silicon nanowire, and cleaning the sample;
g. wrapping a layer of germanium-silicon alloy outside the silicon nanowire obtained in the step f to form a germanium-silicon nanowire core-shell heterostructure;
h. and corroding the germanium-silicon alloy deposited on the oxygen burying layer by adopting hydrofluoric acid to obtain the core-shell heterostructure germanium-silicon nanowire.
2. The controllable preparation method of the core-shell heterostructure germanium-silicon nanowire according to claim 1, characterized in that: the electron beam resist in the step b adopts SAL601, HSQ, PMMA or ZEP 520.
3. The controllable preparation method of the core-shell heterostructure germanium-silicon nanowire according to claim 1, characterized in that: and c, the cross section of the silicon nanowire structure graph in the step b is in a barbell shape with a thin middle part and thick two ends.
4. The controllable preparation method of the core-shell heterostructure germanium-silicon nanowire according to claim 1, characterized in that: the dry etching in the step c adopts CCl4、BC13、CHF3、SF6Or C4F8Reactive Ion Etching (RIE), Inductively Coupled Plasma (ICP) etching or Electron Cyclotron Resonance (ECR) etching method is adopted for etching gas.
5. The controllable preparation method of the core-shell heterostructure germanium-silicon nanowire according to claim 1, characterized in that: and e, oxidizing in the step e by adopting dry oxygen oxidation or wet oxidation, annealing in a nitrogen environment, and oxidizing and annealing at 700-1200 ℃.
6. The controllable preparation method of the core-shell heterostructure germanium-silicon nanowire according to claim 1, characterized in that: and g, wrapping the germanium-silicon alloy by adopting a molecular beam epitaxial growth method MBE or an ultrahigh vacuum vapor deposition method UHV-CVD.
7. A core-shell heterostructure SiGe nanowire prepared by the method of any one of claims 1 to 6.
8. The application of the core-shell heterostructure silicon germanium nanowire prepared by the method according to any one of claims 1 to 6 in a semiconductor device.
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