CN113594006B

CN113594006B - Vacuum channel transistor and manufacturing method thereof

Info

Publication number: CN113594006B
Application number: CN202110865729.5A
Authority: CN
Inventors: 母志强; 刘强; 俞文杰
Original assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Current assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Priority date: 2021-07-29
Filing date: 2021-07-29
Publication date: 2022-08-30
Anticipated expiration: 2041-07-29
Also published as: CN113594006A

Abstract

The invention provides a manufacturing method of a vacuum channel transistor, which at least comprises the following steps: forming a stacked structure on a first silicon substrate, the stacked structure including a first dielectric layer, a polysilicon layer, and a second dielectric layer; patterning the stacked structure to form a patterned region including a cavity and a trench, wherein the first silicon substrate is exposed at a bottom of the trench; forming sidewalls of a third dielectric in the patterned region; positioning a growing nanowire within the trench formed with third dielectric sidewalls, the nanowire extending from the first silicon substrate toward the cavity and protruding into the cavity; bonding the second dielectric layer to a second silicon substrate. The invention also provides a vacuum channel transistor comprising a nanowire through the first dielectric layer into a vacuum cavity. The manufacturing method is compatible with the manufacturing process of the existing integrated circuit, and the vacuum transistor with the accurately adjustable distance between the source electrode and the drain electrode can be obtained through the manufacturing method.

Description

Vacuum channel transistor and manufacturing method thereof

Technical Field

The present invention relates to a semiconductor device structure and a method for fabricating the same, and more particularly, to a vacuum transistor and a method for fabricating the same.

Background

As integrated circuit fabrication technology enters the 5nm technology node, the continued scaling of feature sizes of semiconductor devices has driven physical limits in size. Limited by the carrier mobility in solid state silicon-based devices, which are inherently affected by lattice scattering or impurities, silicon-based devices are no longer able to meet the increasing demands in terms of high frequency or fast response. The vacuum condition enables ballistic transport of electrons without collision or scattering, which results in faster carrier transport, compared to the case in solid state devices.

Since the first time it was proposed, the mechanisms that have been used to implement Nanoscale Vacuum Channel Transistors (NVCTs) include field emission, two-dimensional electron gas emission in Schottky (Schottky) diodes, and thermal electron emission from low-dimensional carbon materials, among others. Among them, some vacuum transistor devices formed of low dimensional materials, such as Spindt type vertical nano-vacuum transistors and all-around gate nano-vacuum channel transistors, have attracted much attention due to their characteristics of high driving current and radiation immunity.

However, the fabrication process of the above-mentioned vacuum transistor device is complicated, and has a problem of being difficult to be compatible with the existing integrated circuit fabrication technology. Therefore, in order to overcome the technical defects of the prior art, a novel vacuum channel transistor and a manufacturing method thereof need to be provided.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a vacuum channel transistor and a method for fabricating the same, which are used to solve the problems of the conventional vacuum channel transistor, such as complicated fabrication process, and difficulty in being fully compatible with the conventional integrated circuit fabrication technology.

To achieve the above and other related objects, the present invention provides a method for fabricating a vacuum channel transistor, the method comprising: forming a laminated structure on a first silicon substrate, the laminated structure comprising a first dielectric layer, a polysilicon layer and a second dielectric layer, the second dielectric layer being located on the polysilicon layer; patterning the laminated structure to form a patterned region including a cavity and a trench at the bottom, the patterned region being formed to penetrate the laminated structure so that the first silicon substrate is exposed at the bottom of the trench; forming sidewalls of a third dielectric in the patterned region; locating a growing nanowire within the trench formed with third dielectric sidewalls, the nanowire extending from the first silicon substrate toward the cavity and protruding into the cavity; bonding the second dielectric layer to the second silicon substrate at one side of the cavity to form an SOI substrate containing the nanowire; patterning the first silicon substrate and the polysilicon layer; and respectively forming a source electrode contact on the first patterned silicon substrate, forming a drain electrode contact on the second silicon substrate, and manufacturing a grid electrode contact of a grid electrode on the patterned polycrystalline silicon layer.

Optionally, forming sidewalls of the third dielectric in the patterned region further comprises: depositing the third dielectric on a surface of the stacked structure and in the patterned area; and removing the third dielectric medium on the surface of the laminated structure and at the bottom of the groove by an etching process so as to expose the first silicon substrate at the bottom of the patterning area.

Optionally, the second dielectric layer is any one of silicon oxide and silicon nitride, or a double-layer structure of silicon oxide and silicon nitride.

Optionally, the first dielectric layer is a silicon oxide layer, the first dielectric layer being disposed between the polysilicon layer and the first silicon substrate such that the trench of the patterned region is defined by the first silicon substrate and sidewalls of the first dielectric.

Optionally, the width of the groove is equal to the width of the cavity.

Optionally, a width of the trench is smaller than a width of the cavity such that a gap is formed between the nanowire within the cavity and a sidewall of the third dielectric.

Optionally, the nanowire is a silicon nanowire, a germanium nanowire or a silicon germanium nanowire grown from the first silicon substrate by an epitaxial process.

Optionally, a distance between a tip of the nanowire and the second silicon substrate is less than 100 nm.

Optionally, the third dielectric is any one of silicon oxide and silicon nitride, or a double-layer structure of silicon oxide and silicon nitride.

Optionally, the manufacturing method further comprises: before the first silicon substrate is patterned, the first silicon substrate is thinned by adopting a back grinding technology or an ion implantation stripping technology, and the thickness of the thinned first silicon substrate is less than or equal to 1 mu m.

In another aspect, the present invention also provides a wrap gate type vacuum channel transistor, including: the semiconductor device comprises a silicon substrate, a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein a drain electrode is formed on the silicon substrate, a drain electrode contact is formed on the drain electrode, a laminated structure containing a vacuum cavity is further formed on the silicon substrate, the laminated structure comprises a first dielectric layer, a polycrystalline silicon layer and the second dielectric layer, and the third dielectric layer is formed on the side wall of the vacuum cavity; the top layer silicon is provided with a source electrode, a source electrode contact is formed on the source electrode, the source electrode further comprises a nanowire which penetrates through the first dielectric layer from the top layer silicon and enters the vacuum cavity, and a vacuum channel is formed between the top end of the nanowire and the source electrode; and a gate surrounding the polysilicon layer of the vacuum cavity and a gate contact on the polysilicon layer, wherein a bias voltage is applied to the gate to achieve regulation of electron density and barrier for electron emission in the nanowire by varying the strength of the electric field between the source and the drain.

Optionally, the length of the vacuum channel is less than 100 nm.

Optionally, the nanowires comprise silicon nanowires, germanium nanowires or silicon germanium nanowires.

Optionally, a gap is formed between the nanowire and a sidewall of the vacuum cavity.

As described above, the method for manufacturing a vacuum channel transistor of the present invention has the following advantages: positioning and growing the nanowire from the first silicon substrate, and accurately controlling the growth height of the nanowire through an epitaxial process; bonding the laminated structure containing the nanowires with a second silicon substrate by using a bonding technology, so that a source contact can be formed on the second silicon substrate, and further, the distance between the source and the drain of the final device can be accurately controlled by controlling the growth height of the nanowires; meanwhile, the manufacturing method can be completely compatible with the existing integrated circuit manufacturing technology, and has the prospect of large-scale mass production. On the other hand, the vacuum channel transistor provided by the invention has a structure similar to an MOS transistor, has an electron transport speed superior to that of the conventional semiconductor transistor, is completely immune to radiation, and has remarkable advantages in the fields of aerospace, national defense and the like.

Drawings

FIG. 1 is a schematic diagram of a method for fabricating a vacuum channel transistor according to the present invention.

Fig. 2 is a schematic cross-sectional view of a stacked structure for fabricating a vacuum channel transistor according to the present invention.

Fig. 3A, 4A, 5A, 6A, 7A and 8A are schematic structural diagrams illustrating stages of fabricating a vacuum channel transistor according to a first embodiment of the present invention.

Fig. 3B, fig. 4B, fig. 5B, fig. 6B, fig. 7B and fig. 8B are schematic structural diagrams illustrating stages of fabricating a vacuum channel transistor according to a second embodiment of the present invention.

Description of the element reference

110 first silicon substrate

120 laminated structure

122 first dielectric layer

124 polysilicon layer

126 second dielectric layer

130 patterned region

132 cavity

134 groove

140 nanowire

150 third dielectric

160 second silicon substrate

230 patterned area

232 cavity

234 groove

236 step structure

310 silicon substrate

332 vacuum cavity

360 top layer silicon

370 source electrode

380 grid

390 drain electrode

S110 to S180

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for matching with the disclosure of the specification, so as to be understood and read by those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modification, ratio relationship change, or size adjustment should still fall within the scope of the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "upper", "lower", "above", "below", "middle" and "one" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the corresponding terms may be changed or adjusted without substantial technical change.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

Compared with the conventional solid-state transistor in which the carrier migration is restricted by a drift-diffusion mechanism, the surrounding gate type vacuum channel transistor comprises the channel in a vacuum state, electrons emitted from the source electrode move to the drain electrode without being hindered along the surface of the channel, so that the transport speed of the electrons is greatly improved, and the capacitance between the gate electrode and the source electrode is reduced.

In the fabrication process of planar Nano Vacuum Channel Transistors (NVCTs), electron beam lithography is typically used to form the emitter and/or collector of the micro-needle structure. The manufacturing method of the vacuum channel transistor provided by the invention adopts the nano wire to replace a micro needle structure, and the nano wire with adjustable height is positioned and grown from the silicon substrate, so that the distance between the source electrode and the drain electrode in the manufactured vacuum channel transistor can be accurately controlled.

The vacuum channel transistor of the present invention has a structure similar to a field effect transistor (MOSFET) that relies on the mechanism of field emission and/or F-N tunneling to achieve electron emission under vacuum conditions. Electron emission from the emitter to the vacuum is susceptible to a strong electric field, and when a strong electric field is applied to the emitter, the height and width of the potential barrier on the emitter surface (i.e., the top of the nanowire) are reduced, so that channeling can be easily generated. Due to this channel effect, electrons are transported from the top of the nanowire to the vacuum. In the vacuum channel transistor, a potential difference is arranged between a source electrode and a drain electrode, and a grid electrode is provided with grid voltage with controllable variation range; when the gate voltage is increased above the turn-on voltage, the vacuum energy bends downward to cause electrons to tunnel through a narrow potential barrier, causing vacuum electron emission.

Specific embodiments of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that several details or components of one embodiment may be applied to another embodiment without departing from the spirit and concept of the invention.

The present invention provides a method for manufacturing a vacuum channel transistor, which will be described in detail below with reference to fig. 1, and the characteristics of the steps at each stage of manufacturing the vacuum channel transistor will be described with reference to the structure shown in fig. 2 and fig. 3A to 8A.

In step S110, a first silicon substrate 110 is provided, and a stacked structure 120 is formed on the first silicon substrate. Referring to fig. 2, there is shown a schematic cross-sectional view of a stacked structure for fabricating a vacuum channel transistor according to the present invention. As shown in fig. 2, the stacked structure 120 may include a first dielectric layer 122, a polysilicon layer 124, and a second dielectric layer 126 sequentially formed on the first silicon substrate 110 as an example, and the first dielectric layer 122 may be a silicon oxide layer. The process for forming the silicon oxide layer may include, but is not limited to, a thermal oxidation process, a chemical vapor deposition process, or the like. Optionally, after growing the silicon oxide layer using a thermal oxidation process, the silicon oxide layer may be annealed under an inert gas to reduce the concentration of trapped charges and/or the concentration of dangling bonds at the interface. The deposition process of the second dielectric layer to be formed may be determined according to its material and/or composition, which includes but is not limited to: a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, atomic layer deposition, or the like. Preferably, the second dielectric layer may be any one of silicon oxide and silicon nitride, or a double-layer structure of silicon oxide and silicon nitride.

After step S110, in step S120, the stacked structure 120 is patterned to obtain a patterned region 130. As shown in fig. 3A, the patterned region 130 may be formed to penetrate the stack structure 120 and include a cavity 132 and a trench 134 stacked one on another. The photolithography process may include coating a photoresist on the surface of the stacked structure 120 by a spin coating method, and then exposing the photoresist using a mask and developing the exposed photoresist. The photolithography process used in this embodiment is a process known to those skilled in the art, and the specific steps thereof are not described herein. After the photolithography process, the stack structure 120 may be etched according to a pattern defined in the photoresist to form the cavity 132. Subsequently, the photolithography, exposure, development, and etching processes may be repeated to form the trench 134. The trench is defined by sidewalls of the first dielectric and the first silicon substrate together. In this embodiment, the width of the cavity is equal to the width of the trench, and thus the patterned region may be formed by one patterning. Alternatively, the formed stacked structure may be cleaned before the patterning process.

In step S130, referring to fig. 4A, a third dielectric 150, which may be any one of silicon oxide and silicon nitride, or a double-layer structure of silicon oxide and silicon nitride, is deposited on the surface of the stacked structure and in the patterned region. By way of example, examples of processes that may be used to deposit the third dielectric include, but are not limited to, a chemical vapor deposition process, an atomic layer deposition process, or the like. In embodiments where the third dielectric is silicon oxide, the silicon oxide may also be grown using a thermal oxidation process; alternatively, the grown silicon oxide may be annealed after a thermal oxidation process.

In step S140, the third dielectric on the surface of the stacked structure and at the bottom of the patterned region is removed by an etching process. As an example, the patterned region may be etched by dry etching, such that the third dielectric on the surface of the stacked structure and at the bottom of the patterned region is removed to expose the first silicon substrate at the bottom of the patterned region, while leaving the third dielectric 150 covering the sidewalls of the patterned region, as shown in fig. 5A.

In step S150, a nanowire 140 is grown in the trench 134 with the third dielectric on the sidewall. Specifically, the nanowires 140 may be grown from the exposed first silicon substrate along the sidewalls of the third dielectric to protrude into the cavities 132. Referring to fig. 6A, in the case where the width of the cavity 132 is equal to the width of the trench 134, the grown nanowire 140 is in contact with the third dielectric sidewall. An epitaxial process may be used to grow nanowires 140, which may be silicon nanowires, germanium nanowires, or silicon germanium nanowires, within the cavities 132. By way of example, the epitaxial process used to positionally grow the nanowires may include, but is not limited to, a chemical vapor deposition process, a molecular beam epitaxy process, or the like. Unlike conventional metal-based microneedle emitters, the nanowires are grown in the trenches 134 in a position similar to the existing solid-state semiconductor device fabrication process and thus compatible with the integrated circuit fabrication process.

Bonding a second silicon substrate 160 with the stacked structure 120 at step S160; specifically, a second silicon substrate 160 may be bonded to a second dielectric surface of the stacked structure 120 to form an SOI substrate containing nanowires 140. As an example, the second silicon substrate 160 may be bonded with the patterned second dielectric layer under vacuum conditions. In the example where the second dielectric is silicon oxide, the second silicon substrate 160 and the second dielectric 126 may be subjected to surface cleaning and then directly bonded at normal temperature. Optionally, the bonding process may further include performing an annealing process on the formed SOI substrate to reduce defects at the interface and enhance the strength of the interfacial chemical bond. The annealing process may be generally performed at a temperature of 900-1200 deg.c for 5-15 hours under the condition of an inert atmosphere. The inert atmosphere may be one or more of nitrogen or argon. The height of the nanowires can be controlled according to the desired transistor performance to obtain a vacuum device with adjustable distance between the source and the drain. As an example, the distance between the top end of the nanowire and the second silicon substrate is less than 100 nm.

Subsequently, referring to fig. 7A, the formed SOI substrate is turned upside down so that the first silicon substrate is positioned on the patterned stacked structure 120. Optionally, in step S170, the first silicon substrate 110 containing the nanowires 140 is thinned. Processes for thinning the first silicon substrate include, but are not limited to: one of a back grinding method or ion implantation lift-off. As an example, hydrogen ions and/or rare gas ions may be implanted into the first silicon substrate 110 to form an ion implanted layer, followed by lift-off along the ion implanted layer to achieve thinning of the first silicon substrate. The thinned first silicon substrate can have a thickness of less than or equal to 1 μm.

In step S180, the first silicon substrate 110 and the stacked structure 120 may be patterned in sequence to partially expose the polysilicon layer 124 and the second silicon substrate 160. A source contact may be formed on the patterned first silicon substrate, a drain contact may be formed on the second silicon substrate, and a gate contact may be formed on the exposed polysilicon layer, respectively, to complete the fabrication of a vacuum channel transistor.

In the second embodiment, the method for manufacturing the vacuum channel transistor can obtain the stacked structure 120 as in the step S110. In a second embodiment, the stacked structure 120 may be patterned to form a patterned region 230 that extends through the stacked structure, the patterned region including a cavity 232 and a trench 234. As shown in fig. 3B, the cavity is surrounded by polysilicon sidewalls and second dielectric sidewalls, and the trench 234 is defined by the first silicon substrate together with the sidewalls of the first dielectric. A similar process as described in step S120 may be used to form the patterned region 230, except that the width of the trench 234 is smaller than the width of the cavity 232 in the second embodiment, so that a step structure 236 is formed at the bottom of the cavity.

In a second embodiment, a third dielectric 150 is deposited on the surface of the stacked structure and in the patterned area, as shown in fig. 4B. The step of depositing a third dielectric covering the surface of the stacked structure, and the sidewalls and bottom of the patterned region, including the side and upper surfaces of the step structure 236, may be performed as in the aforementioned step S130.

In a second embodiment, the third dielectric is removed from the surface of the stacked structure and from the bottom of the patterned region by an etching process. Referring to fig. 5B, in addition to the third dielectric at the bottom of trench 234, the third dielectric at the bottom of the cavity may also be removed to expose the upper surface of step structure 236.

In a second embodiment, a nanowire 140 is grown in-situ within the trench 234. As an example, the nanowire 140 may be grown along sidewalls of the third dielectric within the trench by an epitaxial process. In the second embodiment, due to the exposed upper surface of the step structure being the first dielectric, particularly silicon oxide, when the nanowire is epitaxially grown from the first silicon substrate toward the cavity 232 and protrudes into the cavity, the nanowire 140 continues to grow in the predetermined direction without forming on the upper surface of the step structure 236, so that a gap is formed between the nanowire 140 and the sidewall of the third dielectric, as shown in fig. 6B. By varying the width of the trench at the bottom of the patterned region, the width of the grown nanowire can be controlled. The width of the nanowire, which is a field enhancement factor for electron emission, is relatively reduced in the present embodiment, so that the threshold voltage for electron emission from the nanowire is lowered. By way of example, the nanowires may be silicon nanowires, germanium nanowires, or silicon germanium nanowires.

In the second embodiment, the second silicon substrate 160 is bonded to the stacked structure 120. An SOI substrate containing nanowires 140 can be formed as in step S160 described previously, as shown in fig. 7B. In this embodiment, the distance between the top end of the nanowire and the second silicon substrate is less than 100 nm.

Thereafter, a vacuum channel transistor as shown in fig. 8B can be obtained as in the foregoing steps S170 to S180.

The present invention also provides a novel vacuum channel transistor having a structure similar to a field effect transistor. Referring to fig. 8A, the vacuum channel transistor includes: a silicon substrate 310 having a drain electrode 390 formed thereon, a drain contact formed thereon, and a stack 120 including a vacuum cavity 332 formed thereon, the stack including a first dielectric layer 122, a polysilicon layer 124, and a second dielectric layer 126, a third dielectric 150 formed on sidewalls of the vacuum cavity 332; a top layer of silicon 360, the top layer of silicon forming a source 370 with a source contact formed thereon, the source further comprising a nanowire 140 passing from the top layer of silicon 360 through the first dielectric layer 122 into the vacuum cavity 332, the nanowire having a vacuum channel formed between its tip and the drain; and a gate 380 having a polysilicon layer fabricated as a conductive structure and located at one side of the vacuum channel, wherein a bias voltage is applied to the gate to achieve regulation of electron density and barrier for electron emission in the nanowire by varying electric field intensity between the source and the drain. The nanowires may include, by way of example, silicon nanowires, germanium nanowires, or silicon-germanium nanowires. In the vacuum channel transistor shown, the emission of vacuum electrons is achieved via field emission in the following manner: when a bias voltage is applied to the grid electrode, the electric field intensity between the source electrode and the drain electrode is changed, so that the electron concentration in the nanowire and the potential barrier of electron emission can be regulated, the grid electrode plays a role in switching electron emission, and the current density of a vacuum channel can be regulated and controlled through the voltage of the grid electrode.

In the vacuum transistor structure shown in fig. 8B, a gap is formed between the nanowire and the third dielectric sidewall in the vacuum cavity, and accordingly, the width of the formed nanowire is relatively smaller. In a vacuum channel transistor, a nanowire is used as an emitter, the field enhancement factor of the emitter being a function of the width of the nanowire, and a reduction of the width thereof may increase the field enhancement factor of electron emission, such that the threshold voltage of electron emission from the nanowire is reduced. On the other hand, due to the existence of the space between the nanowire and the side wall of the third dielectric, electron tunneling from the nanowire through the gate dielectric can be avoided, and therefore leakage current of the gate can be reduced, and reliability of the vacuum device is improved.

In summary, the present invention provides a method for manufacturing a vacuum channel transistor, which has the following advantages: positioning and growing the nanowire from the first silicon substrate, and accurately controlling the growth height of the nanowire through an epitaxial process; bonding the laminated structure containing the nanowires with a second silicon substrate by using a bonding technology, so that a source contact can be formed on the second silicon substrate, and further, the distance between the source and the drain of the final device can be accurately controlled by controlling the growth height of the nanowires; on the other hand, the manufacturing method can be completely compatible with the existing integrated circuit manufacturing technology, and has the prospect of large-scale mass production. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A method of fabricating a vacuum channel transistor, the method comprising:

forming a laminated structure on a first silicon substrate, the laminated structure comprising a first dielectric layer, a polysilicon layer and a second dielectric layer, the second dielectric layer being located on the polysilicon layer;

patterning the laminated structure to form a patterned region including a cavity and a trench at the bottom, the patterned region being formed to penetrate the laminated structure so that the first silicon substrate is exposed at the bottom of the trench;

forming sidewalls of a third dielectric in the patterned region;

locating a growing nanowire within the trench formed with third dielectric sidewalls, the nanowire extending from the first silicon substrate toward the cavity and protruding into the cavity;

bonding the second dielectric layer with a second silicon substrate at one side of the cavity to form an SOI substrate containing the nanowire;

patterning the first silicon substrate and the polysilicon layer; and

and respectively forming a source electrode contact on the first patterned silicon substrate, forming a drain electrode contact on the second silicon substrate, and manufacturing a grid electrode contact of a grid electrode on the patterned polycrystalline silicon layer.

2. The method of claim 1, wherein forming sidewalls of the third dielectric in the patterned region further comprises:

depositing the third dielectric on the surface of the stacked structure and in the patterned area;

and removing the third dielectric medium on the surface of the laminated structure and at the bottom of the groove by an etching process so as to expose the first silicon substrate at the bottom of the patterning area.

3. The method of manufacturing a vacuum channel transistor according to claim 1, wherein: the second dielectric layer is either silicon oxide or silicon nitride, or a double-layer structure of silicon oxide and silicon nitride.

4. The method of manufacturing a vacuum channel transistor according to claim 1, wherein: the first dielectric layer is a silicon oxide layer disposed between the polysilicon layer and the first silicon substrate such that a trench of the patterned region is defined by sidewalls of the first silicon substrate and first dielectric.

5. The method of manufacturing a vacuum channel transistor according to claim 1, wherein: the width of the groove is equal to the width of the cavity.

6. The method of manufacturing a vacuum channel transistor according to claim 1, wherein: the width of the trench is less than the width of the cavity such that a gap is formed between the nanowire within the cavity and a sidewall of the third dielectric.

7. The method of manufacturing a vacuum channel transistor according to claim 1, wherein: the nanowires are silicon nanowires, germanium nanowires, or silicon germanium nanowires grown from the first silicon substrate by an epitaxial process.

8. The method of manufacturing a vacuum channel transistor according to claim 1, wherein: the distance between the top end of the nanowire and the second silicon substrate is less than 100 nm.

9. The method of manufacturing a vacuum channel transistor according to claim 1, wherein: the third dielectric is any one of silicon oxide and silicon nitride, or a double-layer structure of silicon oxide and silicon nitride.

10. The method of fabricating a vacuum channel transistor according to claim 1, further comprising: before the first silicon substrate is patterned, the first silicon substrate is thinned by adopting a back grinding technology or an ion implantation stripping technology, and the thickness of the thinned first silicon substrate is less than or equal to 1 mu m.

11. A vacuum channel transistor, comprising:

the semiconductor device comprises a silicon substrate, a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein a drain electrode is formed on the silicon substrate, a drain electrode contact is formed on the drain electrode, a laminated structure containing a vacuum cavity is further formed on the silicon substrate, the laminated structure comprises a first dielectric layer, a polycrystalline silicon layer and the second dielectric layer, and the third dielectric layer is formed on the side wall of the vacuum cavity;

the top layer silicon is provided with a source electrode, a source electrode contact is formed on the source electrode, the source electrode further comprises a nanowire which penetrates through the first dielectric layer from the top layer silicon and enters the vacuum cavity, and a vacuum channel is formed between the top end of the nanowire and the source electrode; and

and the grid electrode comprises the polycrystalline silicon layer surrounding the vacuum cavity and a grid electrode contact positioned on the polycrystalline silicon layer, wherein a bias voltage is applied to the grid electrode so as to realize the regulation and control of the electron density in the nanowire and the potential barrier of electron emission by changing the electric field intensity between the source electrode and the drain electrode.

12. The vacuum channel transistor of claim 11, wherein: the length of the vacuum channel is less than 100 nm.

13. The vacuum channel transistor of claim 11, wherein: the nanowires include silicon nanowires, germanium nanowires, or silicon germanium nanowires.

14. The vacuum channel transistor of claim 11, wherein: a gap is formed between the nanowire and the sidewall of the vacuum cavity.