CN1070287A - 具有平面构图表面的多片组件和集成电路衬底 - Google Patents
具有平面构图表面的多片组件和集成电路衬底 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 44
- 239000000203 mixture Substances 0.000 title claims abstract description 21
- 239000004020 conductor Substances 0.000 claims abstract description 86
- 238000000034 method Methods 0.000 claims abstract description 82
- 238000011049 filling Methods 0.000 claims abstract description 13
- 239000011248 coating agent Substances 0.000 claims abstract description 10
- 238000000576 coating method Methods 0.000 claims abstract description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 45
- 239000010949 copper Substances 0.000 claims description 45
- 229910052802 copper Inorganic materials 0.000 claims description 45
- 239000004642 Polyimide Substances 0.000 claims description 28
- 229920001721 polyimide Polymers 0.000 claims description 28
- 238000005260 corrosion Methods 0.000 claims description 18
- 230000007797 corrosion Effects 0.000 claims description 18
- 238000002161 passivation Methods 0.000 claims description 16
- 239000003518 caustics Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 239000000126 substance Substances 0.000 claims description 12
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052804 chromium Inorganic materials 0.000 claims description 9
- 239000011651 chromium Substances 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 238000001020 plasma etching Methods 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 238000004544 sputter deposition Methods 0.000 claims description 7
- 239000000945 filler Substances 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 230000008020 evaporation Effects 0.000 claims description 2
- 238000001704 evaporation Methods 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000005507 spraying Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 2
- 230000008021 deposition Effects 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 230000001737 promoting effect Effects 0.000 claims 1
- 238000000992 sputter etching Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 20
- 239000003989 dielectric material Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 90
- 238000004519 manufacturing process Methods 0.000 description 12
- 238000009713 electroplating Methods 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 9
- 238000007747 plating Methods 0.000 description 6
- 230000003628 erosive effect Effects 0.000 description 5
- 238000012545 processing Methods 0.000 description 4
- 238000001878 scanning electron micrograph Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 238000007645 offset printing Methods 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003082 abrasive agent Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- BGTOWKSIORTVQH-UHFFFAOYSA-N cyclopentanone Chemical compound O=C1CCCC1 BGTOWKSIORTVQH-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- FDPIMTJIUBPUKL-UHFFFAOYSA-N pentan-3-one Chemical compound CCC(=O)CC FDPIMTJIUBPUKL-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229920002160 Celluloid Polymers 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 240000005373 Panax quinquefolius Species 0.000 description 1
- QOSMNYMQXIVWKY-UHFFFAOYSA-N Propyl levulinate Chemical compound CCCOC(=O)CCC(C)=O QOSMNYMQXIVWKY-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000011438 cord wood Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- XZWYZXLIPXDOLR-UHFFFAOYSA-N metformin Chemical compound CN(C)C(=N)NC(N)=N XZWYZXLIPXDOLR-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
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Abstract
本发明为一种填充衬底的形貌而使该衬底上产
生平面构图表面的方法,包括:提供一个包含形貌图
形的衬底;在其上淀积一层导体,导体层的第一部分
覆盖电介质材料,第二部分填充形貌,第三侧壁部分
与第一和第二部分相连;用光致抗蚀剂涂覆衬底,使
光致抗蚀剂具有与形貌图形相似的图形;在防止导体
层侧壁部分横向腐蚀的条件下,腐蚀掉该导体层的除
第二部分以外的所有部分;再除去光致抗蚀剂。
Description
本发明涉及具有平面表面的多片组件和集成电路衬底、由此构成的多层互连结构、以及它们的制造方法。
在高密度互连技术领域中,把很多集成电路芯片物理地和电气地连接到一个单独的衬底,通常称为多片组件(MCM)。为实现高的布线和封装密度,需要在衬底上制造多层结构,以使各集成电路互相连接。通常,衬底中的金属电源线层和地线层,由象聚酰亚胺那样的电介质层分开。嵌入其它电介质层中的是具有通路(孔)的金属导线(大约8至25μ宽),这些导线在信号线间或者向金属电源线层和地线层提供电连接。通常,邻近层是这样形成以致于初始信号传送方向相互正交。因为,通常导体形貌在宽度上是窄的,在垂直方向是厚的(厚度在5到10μ范围内),并且必须通过微印刷技术构图,因此,产生基本上平坦和光滑的(即平面的)各构图层用作下一层的基底是重要的。
如果表面不是平坦和光滑的,就会产生很多制造问题。在多层结构中,一个平坦的表面,对于层与层之间保持均匀工艺参数是非常重要的。一个非平坦的表面会导致光致抗蚀剂的厚度产生变化,这就需要与图形或层相关联的工艺条件。这种与层相关联的工艺,大大地增加了工艺复杂性,导致线宽变化,产量减少。于是,在制造多层结构时,在制造每一层后,保持平坦的表面,可允许进行相同的层与层间的工艺处理。
过去,制造平面形表面的很多方法已被结合到制造高密度互连结构和集成电路芯片的方法中。制造MCMs的最原始方法之一,被称为Honeywell方法,其中用等离子体腐蚀将通路蚀成电介质,沿侧壁溅射导电金属(如铜)。这会产生一个非平面的通路,该通路不能层层重叠,因此损耗了布线密度。采用Honeywell方法,通过电镀或负腐蚀制造导线。通过多次涂覆用于实现合格的平整度的聚酰亚胺,使导线和通路平面化。采用多次涂覆和厚的聚酰亚胺不但费时而且会在衬底上产生很大的应力。
在美国专利4,705,606号公开的另一种方法中,在电介质中形成通路或沟槽后,再通过选择性电镀填充它们。这种方法会受到限制,即需要把全部的导线和通路电连接到基片的边缘,以便用来输送电镀电流。这就给该电路提出了不实用的设计约束条件。若采用无电镀,则工序是缓慢的,并且选择性淀积难以实现。在工序中的一个阶段,与电镀的形貌相连并在均匀的或选择性加热后变成绝缘的附加电路元件,象美国专利4,661,214号公开的那样,增加了工艺复杂性并且不允许导线形貌中的侧壁钝化。
另一种现有的方法,包括在光致抗蚀剂图形中电镀形貌,用很厚的聚酰亚胺电介质涂覆它们,利用机械磨光使复合的结构平面化。采用这种方法的问题包括:缺乏研磨终点的检测方法,在工艺处理中磨料的结合,划伤,由于研磨产生的机械剪切应力,以及在清洁房间中的磨料污染。在任何实际的此类工艺的实施过程中,这些问题都会是严重的限制条件。
利用无机电介质材料(例如SiO2)和比多片组件所用线宽小得多的线宽制造的集成电路,为了产生平面表面,使用了不同的方法。这些方法包括电介质的化学汽相淀积和旋转淀积。在精细间隔的线条之间,化学汽相淀积会留下空洞,旋转淀积的电介质需要多次复杂的涂覆。
由于存在与现有的在MCMs和集成电路芯片上形成平面表面的尝试相联系的诸多问题,如上面描述的那些问题,因而需要一种用于在电介质中形成平面导体的高效、迅速和简单的方法。
总的说来,本发明的目的是克服现有技术方法的缺点,所述方法是在高密度互连(MCMs)和集成电路上形成平面表面的方法。
更具体地说,本发明的一个目的是提供一种方法,即,在衬底上用导体填充电介质的形貌,形成一个平面的构图表面。重复这种方法形成多层的高密度互连衬底。此外,使用该方法还可以形成具有平面表面的集成电路。
本发明的另一目的是提供具有平面的导体和电介质表面的集成电路芯片和MCMs。
本发明提供一种用于在衬底上填充电介质的形貌产生平面表面的方法,它包括以下步骤:
提供具有表面的衬底,该表面具有在电介质材料中限定的沟槽或凹面图形;
在构图的表面上淀积一层导体,该导体层的第一部分覆盖电介质材料,该导体层的第二部分填充形貌,第一和第二部分由该导体层薄的侧壁部分连接;
用光致抗蚀剂涂覆基片,并使其具有下面的衬底图形相同的图形;
在防止导体层侧壁部分横向腐蚀的条件下,腐蚀掉导体层,由此,所述的填充面貌的导体层的第二部分基本上是无损伤的;
除掉光致抗蚀剂,产生一个具有基本上平面的构图表面的衬底。
本发明还提供用上述方法制备的具有平面构图表面的集成电路芯片。
本发明进一步提供多层互连结构,它包括多个构图的导体层,这些层具有按上述方法制备的基本上平面的表面。
本发明的方法也可以与已知的方法相结合,用于改善电路芯片构图表面的平整度,如下文详述的那样。
图1A-1F用剖面图显示为制备具有平面构图表面的MCMs而用来形成导体/电介质层的各步骤。
图2是在聚酰亚胺层中多次加工的铜导线层的扫描电子显微照片,所述层基本上是平面的。
图3是一个轮廓曲线测定仪扫过一个通路结构的扫描轨迹,它显示出该结构的良好平面性和导线厚度。用下文描述的聚酰亚胺层,可以使加工好的线/通路结构连续地钝化和平面化。
图4A-4E显示本发明的另一个实施例,其中,本发明的方法被设计成代替现有方法中的电镀。
图5A是一个已制成的填充通路孔的扫描电子显微照片,该孔具有位于聚酰亚胺层上面的相连的铜导线和导线层(面),该聚酰亚胺层具有5μm厚的通路孔。
图5B是图5A的一通路的近距观视图,它显示出高的平整度。
图1A-1F以简图形式显示出包括制造具有平面构图表面的导体和电介质层的本发明方法的各步骤。
图1A显示出其上具有形貌4的图形的衬底2,形貌4是在一层电介质材料6中形成的。衬底2可以由任何在多片组件或集成电路技术领域中被视为标准的材料制成。一种优选的衬底是氧化硅片。
本发明的电介质的特性不是临界的(critical)。对于高密度互连,优选光敏聚酰亚胺;然而,用其它方法构图的非光敏聚酰亚胺或无机电介质(例如,氮化硅、氧化硅、或玻璃)也可被使用。用于使电介质构图的其它方法包括化学湿选方法、活性离子方法、或激光腐蚀方法。未曝光的光敏聚酰亚胺是容易在光刻构图工艺使用的显影液中溶解的,显影液可以是如γ-丁丙酯、环戊酮、环乙酮和类似物。由显影液溶解光敏聚酰亚胺的阻力,由于用紫外光照射聚酰亚胺可能被大大增加了。
优选的光敏聚酰亚胺的例子是可买到的、Ciba-Geigy公司的商标为PROBIMIDTM400的系列产品。其它的例子包括由Hitachi Chemicals生产的PAL、由E.I.Dupont de Nemous & Co.生产的PYRALINTMPD、以及由Toray Industries生产的PHOTONEECETM和类似产品。
聚酰亚胺形貌4包括通路、沟槽或凹面。这些形貌可能由等离子体腐蚀或如上所述的利用光敏聚酰亚胺的微平板印刷制造。沟槽限定各线,当用导电材料填充沟槽时,该线在一个平面内传输信号,该平面与MCM衬底和集成电路的平面相一致。通路是一些孔,当用导电材料填充这些孔时,这些孔与不同导体层上的各线互连。凹面是任何希望用导电材料填充的其它区域。露出这些形貌的或者在其中原始形成有这些形貌的衬底表面,在下文中被称为“构图表面”。
包含形貌图形的MCM或集成电路芯片在下步工序中被覆盖,至少在它的构图表面上被一层导体材料覆盖。参见图1B。在衬底2的表面上,在电介质层6中确定的形貌4,被导体12覆盖。通常用溅射淀积形成导体层。也可以采用蒸发技术,特别是,如果在淀积前利用离子枪进行预清洁处理,则有利于附着。导体可以是本领域技术人员公知的任何导电材料。优选的导体是金属,特别优选的导体是铜。
构图表面的形貌通过淀积一层导体材料填充,导体材料层的厚度近似等于电介质层的厚度。可以这样控制溅射淀积过程,即,由导体淀积的侧壁覆盖厚度大大地小于该形貌(沟槽或通路)底部的厚度。可以通过溅射参数控制侧壁的厚度,特别是气压和基片相对于溅射淀积阴极的取向。如在图1B所看到的那样,导体层采用三部分结构:第一部分8直接地铺在电介质层的上面,第二部分10填充形貌,第三部分12构成薄的侧壁。
在本发明的一个优选方法中,在构图表面上淀积导体层之前,一般先淀积一层薄的附着金属层(例如5-200nm),最好选铬或钛,以保证导体对衬底的良好附着。附着金属14也作为导体10(例如铜)形貌的侧面和底面的特有的钝化层。钝化能够增强聚酰亚胺中铜导体的抗蚀性,从而产生一种高可靠性的互连结构。
参见图1C,在下步工序,导体层被覆盖一层抗蚀材料,并且用与所用的电介质图形相类似的掩蔽图使之构图。使用“类似”一词,意指基本上相同或相同的掩蔽图。优选的抗蚀剂是光致抗蚀剂。如图1C所示的那样,构图后,导体层的侧壁部分和在该形貌中的导体层部分仍然被抗蚀材料16所覆盖。抗蚀材料将延伸覆盖电介质上面导体层的一小部分。抗蚀材料的延伸,采用机翼状结构18的形式,其大小可以通过适当选择光掩蔽尺寸(掩蔽偏移)进行控制。
参见图1D,在下步工序,利用腐蚀步骤去掉电介质材料上面不想要区域的导体材料。为实现本发明的平面结构,腐蚀步骤是重要的。它必会导致填充形貌的导体材料22的最小损耗。
当使用铜作为填充形貌的导体材料22时,优选采用各向异性铜腐蚀剂。喷涂各向异性的铜腐蚀剂,从电介质6上面把不想要区域上的铜除掉。同时,腐蚀剂从机翼状结构18的下面去除铜,直到导体材料22。在电路板工业中使用的是各向异性铜腐蚀剂,并常称之为“细线铜腐蚀剂”。这些腐蚀剂的卖主,通常要求这些腐蚀剂包含一种专用的表面活化添加剂或者所谓的“填充剂”,它一般涂覆到要被腐蚀的形貌的侧壁上(在本发明中,这些区域在机翼状结构的下面)。这种涂覆可防止结构16下面导体的横向腐蚀。
由于两种原因,在导体22的边缘处腐蚀速率显著降低。第一,由于沿着窄的侧壁区域20,所溅射的导体(铜)的截面狭窄,腐蚀剂必须透入很深的缝隙。在这狭窄的缝隙中,腐蚀剂被消耗并且不能迅速补给,特别是在采用喷涂方向施加腐蚀剂的情况下。第二,由于填充剂的积累,下切的横向腐蚀速率也被减小。因此,在区域20的边缘腐蚀工艺减速或中止。这种中止产生一个几乎平面的表面,该表面包括电介质6的上表面和导体22的上表面。在区域20形貌的边缘处存在最小的沟。这种自限制特性提供了一个腐蚀终点,并使过腐蚀具有大的工艺容限。
特别优选的各向异性铜腐蚀剂是Olin Hunt′s Ac-Cu-Fine
和Ac-Cu-Guard
Plus。Ac-Cu-Fine
和Ac-Cu-Guard
Plus是高缓冲的以碱/氨为基体的腐蚀剂。其它可能采用的铜腐蚀剂是在美国专利4,952,275中描述或引用的那些腐蚀剂。
如果使用铝做导体,也可用等离子体腐蚀除掉不想要的导体区域。不过,如上所述,铜是优选的导体,至少部分原因是,铜比铝有更好的导电性。
也可能采用其它种类的腐蚀剂或那些无填充剂的腐蚀剂。例如,把不含填充剂的腐蚀剂喷涂到如图1C所示的表面,可以产生如图1D所示的所希望的结构。因为,机翼状结构18将至少部分地阻挡腐蚀剂流近图1D中所示的区域20中的导体。该腐蚀剂仍将被消耗在“中止”区域20中。
在上述步骤完成后,光致抗蚀剂16,包括机翼状结构18,用标准的清除抗蚀剂步骤除掉,产生一个如图1E所示的基本上平面的结构。如上所述,在腐蚀作用中止时,在区域20中铜导线22有最小的沟。
在引入导体层(图1B中的8、10、12)之前,在淀积附着层14(见图1B)后,通过施加一个与附着金属层14相同的薄层到导线22的顶部,导线22(参见图1E)可以充分隐埋在钝化层中。于是把一个附加的薄附着金属层溅射在衬底上,然后在该线上层限定抗蚀剂图形作为腐蚀掩蔽。尔后,同时腐蚀掉两个附着金属层,制成如图1F所示的充分钝化的导线。图1F中隐埋的附着金属层26,充分钝化该导线,并且用作粘附下一层聚酰亚胺层。如上所述,优选的附着金属层是一薄的铬层。
图3是轮廓曲线测定仪对一个通路结构的测定轨迹,它显示出良好的结构平整性和导线厚度。
图1A-1F所示的各步骤组成的工序可以重复,重复是通过在如图1F所示的结构上淀积的新电介质层中形成的形貌进行的。重复的结果是形成一个完整的多层互连结构,该结构具有导线、电源线层、地线层和互连通路。图2是一个扫描电子显微照片,其显示出在聚酰亚胺层中用这种方法制成的一层铜导线,该层基本上是平面的。在下述意义上,生产图2所示的结构的图1A-1F所示的全部工艺步骤是简单的和积木式的,即,在制造各层时,多次使用包含少数步骤的相同加工工序(或加工组件)。在每一次制造加工组件后,都形成一个基本上平坦的表面,它作为好的起始表面用于平板印刷下一层。另外,在这种方法中,钝化导线是很容易的。因为,如果在淀积导体层之前淀积一附着层,则底部和侧面已经被固有地钝化。以前的导体钝化方法,包括在淀积电介质之前,或者用电镀或用溅射制造导线,需要在严重起伏不平的表面上进行平板印刷和腐蚀,该表面的外形高度等于导体厚度。这使平板印刷遇到困难,如果光致抗蚀剂覆盖层在导体侧壁处不完整,在钝化层被无意识地除去的位置,将形成一个易腐蚀的区域。这可能限制多层互连结构的寿命和效果。
总结以上公开的内容,本发明方法的最佳实施例,包括下述步骤:
(1)提供一个MCM或集成电路的衬底,该衬底由涂覆光敏聚酰亚胺电介质的氧化硅制成,并且用等离子体腐蚀或者微平板印刷在聚酰亚胺中形成形貌;
(2)在聚酰亚胺和氧化硅衬底上淀积铬或钛的薄附着层;
(3)通过溅射淀积将铜层覆盖在聚酰亚胺和硅衬底上,铜层具有填满通路和沟槽的厚度;
(4)用光致抗蚀剂涂覆铜层,涂覆时采用与在聚酰亚胺中形成通路和沟槽时相同的掩模和相同的对准方式;
(5)用各向异性的铜腐蚀法腐蚀掉通路和沟槽以外的铜;
(6)除掉光致抗蚀剂;
(7)用铬或者钛层钝化铜形貌的顶部,由此将铜形貌完全埋在附着层中(铜形貌的侧面和底面已用以前淀积的附着层钝化);
(8)用光致抗蚀剂涂覆附着金属层,涂覆时采用与腐蚀铜时相似的掩蔽图和相同的对准方式;
(9)腐蚀掉光致抗蚀剂区域以外的附着金属层;
(10)除掉光致抗蚀剂。
为了生产平面的铜导体和通路,上述的方法也可以与现有的工艺结合。在一个特殊的例子中,通过在整个衬底上淀积一导电镀层而在电介质中形成通路的方法已被公知。在适当的腐蚀步骤后,在光致抗蚀剂中开一个沟槽,沟槽的一端越过通路并延伸到要被电镀的连接导线处。在通路孔中的电镀和在沟槽中的电镀同时进行,由于通路中的电镀是各向同性的淀积过程,在通路侧壁上的电镀使得大小不同的通路以不同的速率电镀。这导致大小不同的通路具有不均匀的通路高度,例如电源通路和较小的信号通路。在下文中把这种方法称为“电镀方法”。
在该电镀方法中,还有许多步骤,用于限定电镀沟槽的厚光致抗蚀剂,必须从衬底上的深的通路孔中或者凹陷处清除掉。由于表面张力和重力,在基片上的任何沟槽或通路处,光致抗蚀剂趋于积累,而且,由于在这样的位置处厚度的增加,难以完全使光致抗蚀剂显影。这是一个实际困难,它需要经常的检查或彻底的等离子体除渣(descumming)步骤,以保证在通路孔的底部不存在光致抗蚀剂残渣。
为了避免上述制造问题,上述的如图1A-1F所示的本发明的方法,可用作改进的铜导体制造方法,以代替上述的电镀方法。类似图1A所示的那样,按前述方式用等离子体腐蚀或微平板印刷光敏聚酰亚胺形成通路后,在聚酰亚胺表面上,可能制造出通路和导线的组合结构。该方法的各步骤如下文所述。
参见图4A,用四层结构覆盖电介质30和通路40,该四层结构是溅射到衬底上的。四层结构由钛(或铬)层32、铜层34、钛或铬层36以及铜层38组成。把最下面的铜层34淀积到所要求的导线厚度。上面的铜层38的厚度近似等于电介质30的厚度。
参见图4B,用产生通路用的掩模使光致抗蚀剂构图,在通路内和靠近通路处,留下一小块抗蚀剂42。与图1A-1F相应的上述相同类型的腐蚀技术,可以被用作除去上面的铜层38。
最终结构如图4C所示。通过腐蚀除去上面的铜层的过程在“中止”区44停止。这里部分原因是在横向腐蚀方向上腐蚀速率减至最小。第二层铬或钛在垂直方向限制腐蚀,该金属层对铜腐蚀剂起阻止作用。然后除去抗蚀剂46,形成的第二光致抗蚀剂图形用作腐蚀掩模,该掩模具有要求的附着在通路上的导线的形状。在起阻止腐蚀作用的铬或钛层36被腐蚀后,该结构如图4D所示。再利用同样的喷射腐蚀,除去多余的铜。当除掉光致抗蚀剂后,填充的通路就制成了,该通路具有与其相连的连接线。这个结构有一个基本上平的顶面(见图4E)。
图5A是一个已填充好的通路孔的扫描电子显微照片,该孔具有连接的铜导线和导线层(面),它们位于带5μ厚的通路孔的聚酰亚胺上面。图5B是这些通路中的一个通路的近距观视图,它显示出高的平整度。如上所讨论的,制成的线/通路结构可以接着被钝化,并再用附加的聚酰亚胺层覆盖,该层可通过本发明的方法被构图和平面化。
与电镀工艺比较,这种代替电镀方法中通路和导线的电镀的溅射工艺具有制造工艺简单之优点,即,制造工艺步骤较少,控制厚度较大,导体和通路均匀。上述方法具有固有的优点,即把光致抗蚀剂留在片中通路或导线凹陷处,因为它是一种减除(subtractive)方法,这就消除了用附加的方法从深的凹陷处清除抗蚀剂的困难。因此,为保证通路的充分开放,就不需要彻底的等离子体除渣和检查。
尽管以各种实施例的形式描述了本发明,包括最佳实施例和各种参量,但在阅读前面的说明书后,一个本领域的普通技术人员,在没有离开本发明公开的主要概念的情况下,将能够实现各种变化、等同物替代和其它替换。因此,所期望的专利证书授予的保护范围,将只能由附属的权利要求书及其等同物所包含的定义来限定。
Claims (19)
1、一种填充衬底中的电介质形貌而使所述衬底上产生平面构图表面的方法,包括下列步骤:
提供一个衬底,该衬底具有一个包含由电介质限定的形貌的图形的表面;
在所述衬底的表面上淀积一导体层,所述导体层的第一部分覆盖所述的电介质材料,所述导体层的第二部分填充所述的形貌,所述导体层的薄的侧壁部分连接所述的第一和第二部分;
用抗蚀剂涂覆所述的芯片,并使所述的抗蚀剂具有与所述形貌的图形相似的抗蚀剂图形;
在防止所述导体层的所述侧壁部分横向腐蚀的条件下,腐蚀掉除填充所述形貌的所述第二部分以外的所述导体层;以及
除去所述的抗蚀剂,产生一个由电介质材料和导体层的第二部分形成的基本上平的构图表面。
2、根据权利要求1的方法,其中所述的形貌包括凹面、沟槽或通路。
3、根据权利要求1或2的方法,进一步包括,在所述的淀积步骤之前,用促进粘合和钝化的材料涂覆所述的集成电路基片,所述材料粘合所述的导体和所述的衬底,在去掉抗蚀剂步骤后,用较多的促进粘合和钝化的材料,涂覆所述的平面构图表面,并且使该表面构图,由此,隐埋和钝化导体层。
4、根据权利要求3的方法,其中所述的促进粘合和钝化的材料包含由铬和钛中选择的一种金属。
5、根据权利要求3的方法,进一步包括:
在使所述的平面构图表面涂覆和构图后,用较多的所述电介质材料覆盖所述的平面构图表面,用一个电路形貌图形使所述的电介质材料构图;
实施所述填充形貌的各步骤;
然后多次重复全部的所述步骤,由此产生多层互连结构。
6、根据权利要求1或2的方法,其中所述的衬底由氧化硅组成,所述的电介质材料由聚酰亚胺组成,所述的导体由铜组成。
7、根据权利要求1或2的方法,其中所述的形貌通过对所述的电介质材料的等离子体腐蚀或光刻产生。
8、根据权利要求1或2的方法,其中,利用溅射淀积所述的导体。
9、根据权利要求1或2的方法,其中,利用蒸发淀积所述的导体。
10、根据权利要求1或2的方法,其中,所述的导体由铜组成,并且用各向异性铜腐蚀剂实现所述的腐蚀。
11、根据权利要求10的方法,其中,所述的各向异性铜腐蚀剂包含一种填充剂。
12、根据权利要求1或2的方法,其中,所述的导体由铜组成,并且通过喷涂腐蚀剂实现所述的腐蚀。
13、根据权利要求1或2的方法,其中每一所述的导体层的所述第二部分具有等于所填充形貌的深度的厚度。
14、根据权利要求1或2的方法,其中在所述腐蚀步骤后,所述的抗蚀剂有一个相连的机翼状结构。
15、根据权利要求1或2的方法,其中所述的导体材料是铝,并且利用等离子体腐蚀实现所述的各向异性腐蚀。
16、根据权利要求15的方法,其中所述的等离子体腐蚀是活性的离子腐蚀。
17、根据权利要求1或2的方法,其中所述的电介质材料由氧化硅、氮化硅、或玻璃组成。
18、一种集成电路芯片,具有一个基本上平面的构图表面,该表面包括按照权利要求1的方法填充的形貌。
19、一种采用权利要求5的方法制备的多片组件。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/654,880 US5187119A (en) | 1991-02-11 | 1991-02-11 | Multichip module and integrated circuit substrates having planarized patterned surfaces |
US654,880 | 1991-02-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1070287A true CN1070287A (zh) | 1993-03-24 |
CN1029274C CN1029274C (zh) | 1995-07-05 |
Family
ID=24626612
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN92101596A Expired - Fee Related CN1029274C (zh) | 1991-02-11 | 1992-02-11 | 具有平面构图表面的多片组件和集成电路衬底 |
Country Status (8)
Country | Link |
---|---|
US (1) | US5187119A (zh) |
EP (1) | EP0571547A1 (zh) |
JP (1) | JPH06505833A (zh) |
KR (1) | KR930703699A (zh) |
CN (1) | CN1029274C (zh) |
CA (1) | CA2101426A1 (zh) |
TW (1) | TW226052B (zh) |
WO (1) | WO1992014261A1 (zh) |
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1991
- 1991-02-11 US US07/654,880 patent/US5187119A/en not_active Expired - Lifetime
-
1992
- 1992-02-10 EP EP92907235A patent/EP0571547A1/en not_active Withdrawn
- 1992-02-10 JP JP4507047A patent/JPH06505833A/ja active Pending
- 1992-02-10 KR KR1019930702379A patent/KR930703699A/ko not_active Application Discontinuation
- 1992-02-10 WO PCT/US1992/001140 patent/WO1992014261A1/en not_active Application Discontinuation
- 1992-02-10 CA CA002101426A patent/CA2101426A1/en not_active Abandoned
- 1992-02-11 CN CN92101596A patent/CN1029274C/zh not_active Expired - Fee Related
- 1992-02-11 TW TW081100926A patent/TW226052B/zh active
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN1081390C (zh) * | 1992-02-26 | 2002-03-20 | 国际商业机器公司 | 难熔金属覆盖的低阻金属导体线与通路 |
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CN112533395B (zh) * | 2020-12-21 | 2021-12-24 | 北京同方信息安全技术股份有限公司 | 印制电路板中埋入电阻的方法及其印制电路板 |
CN114190002A (zh) * | 2021-12-09 | 2022-03-15 | 上达电子(深圳)股份有限公司 | 一种柔性封装基板半埋入式厚铜精细线路的成型方法 |
Also Published As
Publication number | Publication date |
---|---|
CN1029274C (zh) | 1995-07-05 |
EP0571547A4 (zh) | 1994-02-09 |
KR930703699A (ko) | 1993-11-30 |
JPH06505833A (ja) | 1994-06-30 |
CA2101426A1 (en) | 1992-08-12 |
TW226052B (zh) | 1994-07-01 |
EP0571547A1 (en) | 1993-12-01 |
WO1992014261A1 (en) | 1992-08-20 |
US5187119A (en) | 1993-02-16 |
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