CN106991956A - 一种像素电路及其驱动方法和其制备方法、显示装置 - Google Patents
一种像素电路及其驱动方法和其制备方法、显示装置 Download PDFInfo
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Abstract
本发明提供一种像素电路及其驱动方法和其制备方法、显示装置。该像素电路包括排布呈阵列的多个子像素,每个子像素对应连接一个碳纳米管开关管,每行子像素分成多个子像素组,每个子像素组均包括第一子像素和第二子像素,第一子像素连接N型碳纳米管开关管,第二子像素连接P型碳纳米管开关管,每个子像素组中的第一子像素和第二子像素连接同一条栅线和同一条数据线。该像素电路能在不增加数据线数量的情况下使栅线的数量减半,从而降低了该像素电路的制备和运行成本;提升了采用该像素电路的显示装置的显示效果;该像素电路的制备工艺更加简单,从而降低了像素电路的制备成本并提高了像素电路的制备效率。
Description
技术领域
本发明涉及显示技术领域,具体地,涉及一种像素电路及其驱动方法和其制备方法、显示装置。
背景技术
目前,为了提升显示器件的显示效果,显示器件采用双栅驱动,显示器件要实现双栅驱动通常需要使其栅线的数量增长一倍,同时数据线的数量减半,这使得显示器件的像素电路的制作和运行成本都较高。
因此,如何在实现显示器件的双栅驱动效果的同时不增加像素电路的制备和运行成本已成为目前亟待解决的技术问题。
发明内容
本发明针对现有技术中存在的上述技术问题,提供一种像素电路及其驱动方法和其制备方法、显示装置。该像素电路能够在每行子像素连接一条栅线、且相邻两列子像素连接一条数据线的情况下实现像素电路的驱动,相对于现有的像素电路,该像素电路能在不增加数据线数量的情况下使栅线的数量减半,从而降低了该像素电路的制备和运行成本;另外,该像素电路能够在列驱动方式下实现点反转的驱动效果,提升了采用该像素电路的显示装置的显示效果;同时,采用碳纳米管开关管的像素电路通过使制备形成P型碳纳米管开关管和N型碳纳米管开关管的源漏极的材料不同,通过简单的构图工艺就能实现P型碳纳米管开关管和N型碳纳米管开关管的制备,无需进行掺杂工艺,因此使P型碳纳米管开关管和N型碳纳米管开关管的制备工艺更加简单,从而降低了像素电路的制备成本并提高了像素电路的制备效率。
本发明提供一种像素电路,包括排布呈阵列的多个子像素,每个所述子像素对应连接一个碳纳米管开关管,每行所述子像素分成多个子像素组,每个所述子像素组均包括第一子像素和第二子像素,所述第一子像素连接N型碳纳米管开关管,所述第二子像素连接P型碳纳米管开关管,每个所述子像素组中的所述第一子像素和所述第二子像素连接同一条栅线和同一条数据线。
优选地,每个所述子像素组中的所述第一子像素和所述第二子像素均相邻。
优选地,奇数行所述子像素中,所述第一子像素为奇数个所述子像素,所述第二子像素为偶数个所述子像素;
偶数行所述子像素中,所述第二子像素为奇数个所述子像素,所述第一子像素为偶数个所述子像素。
优选地,奇数行所述子像素中,所述第二子像素为奇数个所述子像素,所述第一子像素为偶数个所述子像素;
偶数行所述子像素中,所述第一子像素为奇数个所述子像素,所述第二子像素为偶数个所述子像素。
优选地,每个所述子像素组中,所述第一子像素和所述第二子像素各自连接的所述P型碳纳米管开关管和所述N型碳纳米管开关管分别位于其所连接的所述数据线的两侧。
优选地,每个所述子像素组中,所述第一子像素和所述第二子像素各自连接的所述P型碳纳米管开关管和所述N型碳纳米管开关管以其所连接的所述数据线为对称轴镜像对称。
优选地,每行所述子像素所连接的所述碳纳米管开关管连接一条所述栅线,相邻两列所述子像素所连接的所述碳纳米管开关管连接一条所述数据线。
本发明还提供一种上述像素电路的制备方法,包括形成多个碳纳米管开关管;形成排布呈阵列的多个子像素,所述碳纳米管开关管与所述子像素一一对应连接,每行所述子像素分成多个子像素组,每个所述子像素组均包括第一子像素和第二子像素,所述第一子像素连接N型碳纳米管开关管,所述第二子像素连接P型碳纳米管开关管,连接所述第一子像素的所述N型碳纳米管开关管和和连接所述第二子像素的所述P型碳纳米管开关管的有源层同时形成,所述P型碳纳米管开关管和所述N型碳纳米管开关管的源漏极分别采用不同材料形成。
本发明还提供一种上述像素电路的驱动方法,每行子像素的驱动均包括正向驱动阶段和负向驱动阶段;
在每行所述子像素的所述正向驱动阶段,连接N型碳纳米管开关管的栅线输入正向电压,所述N型碳纳米管开关管开启,连接所述N型碳纳米管开关管的数据线输入正电压,所述N型碳纳米管开关管驱动所述第一子像素进行显示;
在每行所述子像素的所述负向驱动阶段,连接P型碳纳米管开关管的所述栅线输入负向电压,所述P型碳纳米管开关管开启,连接所述P型碳纳米管开关管的所述数据线输入负电压,所述P型碳纳米管开关管驱动所述第二子像素进行显示。
优选地,奇数行中的奇数个所述子像素和偶数行中的偶数个所述子像素在所述正向驱动阶段驱动;
奇数行中的偶数个所述子像素和偶数行中的奇数个所述子像素在所述负向驱动阶段驱动。
优选地,奇数行中的偶数个所述子像素和偶数行中的奇数个所述子像素在所述正向驱动阶段驱动;
奇数行中的奇数个所述子像素和偶数行中的偶数个所述子像素在所述负向驱动阶段驱动。
本发明还提供一种显示装置,包括上述像素电路。
本发明的有益效果:本发明所提供的像素电路,通过使子像素组中的第一子像素和第二子像素分别连接N型碳纳米管开关管和P型碳纳米管开关管,能够在每行子像素连接一条栅线、且相邻两列子像素连接一条数据线的情况下实现像素电路的驱动,相对于现有的像素电路,该像素电路能在不增加数据线数量的情况下使栅线的数量减半,从而降低了该像素电路的制备和运行成本;另外,该像素电路能够在列驱动方式下实现点反转的驱动效果,提升了采用该像素电路的显示装置的显示效果;同时,采用碳纳米管开关管的像素电路通过使制备形成P型碳纳米管开关管和N型碳纳米管开关管的源漏极的材料不同,通过简单的构图工艺就能实现P型碳纳米管开关管和N型碳纳米管开关管的制备,无需进行掺杂工艺,因此使P型碳纳米管开关管和N型碳纳米管开关管的制备工艺更加简单,从而降低了像素电路的制备成本并提高了像素电路的制备效率。
本发明所提供的显示装置,通过采用上述像素电路,降低了该显示装置的制备和运行成本,提升了该显示装置的显示效果,同时还简化了该显示装置的制备复杂度,提高了其制备效率。
附图说明
图1为本发明实施例1中像素电路的结构示意图;
图2为图1中像素电路以列驱动方式实现点反转驱动的示意图;
图3为图1中像素电路的驱动时序图;
图4为本发明实施例2中像素电路的结构示意图;
图5为图4中像素电路以列驱动方式实现点反转驱动的示意图。
其中的附图标记说明:
1.子像素;10.子像素组;11.第一子像素;12.第二子像素;2.碳纳米管开关管;21.P型碳纳米管开关管;22.N型碳纳米管开关管;3.栅线;4.数据线;5.栅线驱动电路;6.数据线驱动电路;L1.正向驱动阶段;L2.负向驱动阶段。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案,下面结合附图和具体实施方式对本发明所提供的一种像素电路及其驱动方法和其制备方法、显示装置作进一步详细描述。
实施例1:
本实施例提供一种像素电路,如图1所示,包括排布呈阵列的多个子像素1,每个子像素1对应连接一个碳纳米管开关管2,每行子像素1分成多个子像素组10,每个子像素组10均包括第一子像素11和第二子像素12,第一子像素11连接N型碳纳米管开关管22,第二子像素12连接P型碳纳米管开关管21,每个子像素组10中的第一子像素11和第二子像素12连接同一条栅线3和同一条数据线4。
其中,相邻的子像素组10之间没有共用的子像素1。
本实施例中,每个子像素组10中的第一子像素11和第二子像素12均相邻。每行子像素1所连接的碳纳米管开关管2连接一条栅线3,相邻两列子像素1所连接的碳纳米管开关管2连接一条数据线4。需要说明的是,图1中的P11~P16、P21~P26、P31~P36均表示子像素1。
现有的双栅驱动的像素电路,各个子像素均连接N型薄膜晶体管,且在数据线的数量减半的情况下,每行子像素需要连接两条栅线才能实现一行子像素的驱动。本实施例中所提供的上述像素电路,相对于现有的双栅驱动的像素电路,通过使子像素组10中的第一子像素11和第二子像素12分别连接N型碳纳米管开关管22和P型碳纳米管开关管21,能够在每行子像素1连接一条栅线3、且相邻两列子像素1连接一条数据线4的情况下即可实现像素电路的驱动,从而使该像素电路能在不增加数据线4数量的情况下使栅线3的数量减半,进而降低了该像素电路的制备和运行成本;同时,该像素电路能够在碳纳米管开关管2的驱动下正常显示。
本实施例中,如图2所示,奇数行子像素1中,第一子像素11为奇数个子像素1,第二子像素12为偶数个子像素1;偶数行子像素1中,第二子像素12为奇数个子像素1,第一子像素11为偶数个子像素1。其中,由于N型碳纳米管开关管22在其栅极输入高电平信号时开启,并在其栅极输入低电平信号时关闭;P型碳纳米管开关管21在其栅极输入低电平信号时开启,并在其栅极输入高电平信号时关闭;因此,当对应连接奇数行子像素1的栅线3输入高电平信号时,该行中的N型碳纳米管开关管22开启,此时,数据线4上输入高于公共电压的正电压,改行中的第一子像素11在N型碳纳米管开关管22的驱动下进行显示;当对应连接奇数行子像素1的栅线3输入低电平信号时,该行中的P型碳纳米管开关管21开启,此时,数据线4上输入低于公共电压的负电压,该行中的第二子像素12在P型碳纳米管开关管21的驱动下进行显示。相应地,当对应连接偶数行子像素1的栅线3输入高电平信号时,该行中的N型碳纳米管开关管22开启,此时,数据线4上输入高于公共电压的正电压,该行中的第一子像素11在N型碳纳米管开关管22的驱动下进行显示;当对应连接偶数行子像素1的栅线3输入低电平信号时,该行中的P型碳纳米管开关管21开启,此时,数据线4上输入低于公共电压的负电压,该行中的第二子像素12在P型碳纳米管开关管21的驱动下进行显示。如此便实现了该像素电路在列驱动方式下的点反转驱动效果,从而提升了采用该像素电路的显示装置的显示效果。
本实施例中,每个子像素组10中,第一子像素11和第二子像素12各自连接的P型碳纳米管开关管21和N型碳纳米管开关管22分别位于其所连接的数据线4的两侧。
优选的,每个子像素组10中,第一子像素11和第二子像素12各自连接的P型碳纳米管开关管21和N型碳纳米管开关管22以其所连接的数据线4为对称轴镜像对称。如此设置,能使像素电路中的P型碳纳米管开关管21和N型碳纳米管开关管22通过较短的距离就近与相应的栅线3和数据线4连接,从而能使像素电路的走线距离更短,不仅降低了走线成本,而且使像素电路的线路布局更加简单,进而降低了像素电路的设计和制备成本。
另外,本实施例中,像素电路还包括栅线驱动电路5和数据线驱动电路6,栅线驱动电路5连接各条栅线3,用于向各条栅线3中输入栅极驱动信号,以使相应的碳纳米管开关管2开启。数据线驱动电路6连接各条数据线4,用于向各条数据线4提供数据信号,以使相应的子像素1显示图像。
基于像素电路的上述结构,本实施例还提供一种该像素电路的驱动方法,如图3所示,每行子像素的驱动均包括正向驱动阶段L1和负向驱动阶段L2;在每行子像素的正向驱动阶段L1,连接N型碳纳米管开关管的栅线3(栅线包括多条,如栅线31、栅线32、栅线33等)输入正向电压,N型碳纳米管开关管开启,连接N型碳纳米管开关管的数据线4(即每条数据线4)输入正电压,N型碳纳米管开关管驱动第一子像素进行显示。在每行子像素的负向驱动阶段L2,连接P型碳纳米管开关管的栅线3输入负向电压,P型碳纳米管开关管开启,连接P型碳纳米管开关管的数据线4输入负电压,P型碳纳米管开关管驱动第二子像素进行显示。
相应地,本实施例中,奇数行中的奇数个子像素和偶数行中的偶数个子像素在正向驱动阶段驱动;奇数行中的偶数个子像素和偶数行中的奇数个子像素在负向驱动阶段驱动。
即当对应连接奇数行子像素的栅线3输入高电平信号时,该行中的N型碳纳米管开关管开启,此时,数据线4上输入高于公共电压的正电压,该行中的第一子像素在N型碳纳米管开关管的驱动下进行显示;当对应连接奇数行子像素的栅线3输入低电平信号时,该行中的P型碳纳米管开关管开启,此时,数据线4上输入低于公共电压的负电压,该行中的第二子像素在P型碳纳米管开关管的驱动下进行显示。相应地,当对应连接偶数行子像素的栅线3输入高电平信号时,该行中的N型碳纳米管开关管开启,此时,数据线4上输入高于公共电压的正电压,该行中的第一子像素在N型碳纳米管开关管的驱动下进行显示;当对应连接偶数行子像素的栅线3输入低电平信号时,该行中的P型碳纳米管开关管开启,此时,数据线4上输入低于公共电压的负电压,该行中的第二子像素在P型碳纳米管开关管的驱动下进行显示。如此便实现了该像素电路在列驱动方式下的点反转驱动效果,从而提升了采用该像素电路的显示装置的显示效果。
另外,基于像素电路的上述结构,本实施例还提供一种该像素电路的制备方法,包括形成多个碳纳米管开关管;形成排布呈阵列的多个子像素,碳纳米管开关管与子像素一一对应连接,每行子像素分成多个子像素组,每个子像素组均包括第一子像素和第二子像素,第一子像素连接N型碳纳米管开关管,第二子像素连接P型碳纳米管开关管,连接第一子像素的N型碳纳米管开关管和和连接第二子像素的P型碳纳米管开关管的有源层同时形成,P型碳纳米管开关管和N型碳纳米管开关管的源漏极分别采用不同材料形成。
其中,P型碳纳米管开关管和N型碳纳米管开关管的有源层采用相同的碳纳米管材料同时形成。N型碳纳米管开关管的源漏极采用如铜或铝形成,P型碳纳米管开关管的源漏极采用如铅形成。
现有的P型晶体管和N型晶体管要么采用a-Si晶体管或氧化物晶体管,要么采用低温多晶硅晶体管。a-Si晶体管和氧化物晶体管需要通过掺杂工艺才能同时制备P型管和N型管,而低温多晶硅晶体管也需要通过掺杂工艺才能同时制备P型管和N型管,通过掺杂工艺制备P型管和N型管需要进行扩散或离子注入,工艺过程繁琐,复杂,曝光数目多,且制备成本较高,这使其制造成本也偏高。本实施例中像素电路的制备方法,通过采用不同材料分别形成P型碳纳米管开关管和N型碳纳米管开关管的源漏极,能够实现通过构图工艺分别制备形成P型碳纳米管开关管和N型碳纳米管开关管,相对于现有的a-Si晶体管、氧化物晶体管和低温多晶硅晶体管,制备形成P型碳纳米管开关管和N型碳纳米管开关管无需再采用掺杂工艺,从而使P型碳纳米管开关管和N型碳纳米管开关管的制备工艺更加简单,进而降低了像素电路的制备成本并提高了像素电路的制备效率。
该像素电路的制备方法具体包括:
(1)玻璃基板按标准方法清洗。
(2)用溅射镀膜沉积2200nm的钼Mo。
(3)经过光刻,显影,定义出栅极区域。再经过湿法刻蚀工艺,形成开关管栅极层。在该步骤中还同时形成栅线的图形。
(4)采用等离子体增强化学气相沉积法(PECVD)沉积100-200nm的SiOx或SiNx膜层,以形成开关管的栅绝缘层。
(5)在SiNx或SiOx表面通过溶液制程(spin-coating,dip-coating等)涂布一层半导体型碳纳米管薄膜。
(6)经光刻定义出N型碳纳米管开关管的有源层图形和P型碳纳米管开关管的有源层图形,显影后,利用光刻胶掩膜进行氧反应离子刻蚀,去除周围部分的碳纳米管膜层,形成开关管的有源层部分。
(7)然后在基板上沉积200nm的铜Cu,经光刻定义出N型碳纳米管开关管的源漏极图形,显影后,进行湿法刻蚀工艺,完成源漏电极的图案化。在该步骤中还同时形成数据线的图形。
(8)然后在基板上沉积200nm的铅Pb,经光刻定义出P型碳纳米管开关管的源漏极图形,显影后,进行湿法刻蚀工艺,完成源漏电极的图案化。在该步骤中还同时形成数据线的图形。
(9)通过等离子体增强化学气相沉积法(PECVD)沉积300nm SiNx形成表面钝化层膜,经过刻蚀去除多余的钝化层膜,以形成钝化层的图形。
(10)再通过溅射工艺沉积135nm的ITO,最后经过光刻,显影,刻蚀,形成子像素的图形。
实施例2:
本实施例提供一种像素电路,与实施例1不同的是,如图4所示,奇数行子像素1中,第二子像素12为奇数个子像素1,第一子像素11为偶数个子像素1;偶数行子像素1中,第一子像素11为奇数个子像素1,第二子像素12为偶数个子像素1。
本实施例中像素电路的其他结构与实施例1中相同,此处不再赘述。
如图5所示,由于N型碳纳米管开关管22在其栅极输入高电平信号时开启,并在其栅极输入低电平信号时关闭;P型碳纳米管开关管21在其栅极输入低电平信号时开启,并在其栅极输入高电平信号时关闭;因此,当对应连接奇数行子像素1的栅线3输入高电平信号时,该行中的N型碳纳米管开关管22开启,此时,数据线4上输入高于公共电压的正电压,该行中的第一子像素11在N型碳纳米管开关管22的驱动下进行显示;当对应连接奇数行子像素1的栅线3输入低电平信号时,该行中的P型碳纳米管开关管21开启,此时,数据线4上输入低于公共电压的负电压,该行中的第二子像素12在P型碳纳米管开关管21的驱动下进行显示。相应地,当对应连接偶数行子像素1的栅线3输入高电平信号时,该行中的N型碳纳米管开关管22开启,此时,数据线4上输入高于公共电压的正电压,该行中的第一子像素11在N型碳纳米管开关管22的驱动下进行显示;当对应连接偶数行子像素1的栅线3输入低电平信号时,该行中的P型碳纳米管开关管21开启,此时,数据线4上输入低于公共电压的负电压,该行中的第二子像素12在P型碳纳米管开关管21的驱动下进行显示。如此便实现了该像素电路在列驱动方式下的点反转驱动效果,从而提升了采用该像素电路的显示装置的显示效果。
相应地,本实施例中像素电路的驱动方法中,奇数行中的偶数个子像素和偶数行中的奇数个子像素在正向驱动阶段驱动;奇数行中的奇数个子像素和偶数行中的偶数个子像素在负向驱动阶段驱动。
本实施例中像素电路的驱动方法其他部分和制备方法均与实施例1中相同,此处不再赘述。
实施例1-2的有益效果:实施例1-2所提供的像素电路,通过使子像素组中的第一子像素和第二子像素分别连接N型碳纳米管开关管和P型碳纳米管开关管,能够在每行子像素连接一条栅线、且相邻两列子像素连接一条数据线的情况下实现像素电路的驱动,相对于现有的像素电路,该像素电路能在不增加数据线数量的情况下使栅线的数量减半,从而降低了该像素电路的制备和运行成本;另外,该像素电路能够在列驱动方式下实现点反转的驱动效果,提升了采用该像素电路的显示装置的显示效果;同时,采用碳纳米管开关管的像素电路通过使制备形成P型碳纳米管开关管和N型碳纳米管开关管的源漏极的材料不同,通过简单的构图工艺就能实现P型碳纳米管开关管和N型碳纳米管开关管的制备,无需进行掺杂工艺,因此使P型碳纳米管开关管和N型碳纳米管开关管的制备工艺更加简单,从而降低了像素电路的制备成本并提高了像素电路的制备效率。
实施例3:
本实施例提供一种显示装置,包括实施例1或2中的像素电路。
通过采用实施例1或2中的像素电路,降低了该显示装置的制备和运行成本,提升了该显示装置的显示效果,同时还简化了该显示装置的制备复杂度,提高了其制备效率。
本发明所提供的显示面板可以为液晶面板、液晶电视、OLED面板、OLED电视、显示器、手机、导航仪等任何具有显示功能的产品或部件。
可以理解的是,以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本发明的保护范围。
Claims (12)
1.一种像素电路,包括排布呈阵列的多个子像素,每个所述子像素对应连接一个碳纳米管开关管,其特征在于,每行所述子像素分成多个子像素组,每个所述子像素组均包括第一子像素和第二子像素,所述第一子像素连接N型碳纳米管开关管,所述第二子像素连接P型碳纳米管开关管,每个所述子像素组中的所述第一子像素和所述第二子像素连接同一条栅线和同一条数据线。
2.根据权利要求1所述的像素电路,其特征在于,每个所述子像素组中的所述第一子像素和所述第二子像素均相邻。
3.根据权利要求2所述的像素电路,其特征在于,奇数行所述子像素中,所述第一子像素为奇数个所述子像素,所述第二子像素为偶数个所述子像素;
偶数行所述子像素中,所述第二子像素为奇数个所述子像素,所述第一子像素为偶数个所述子像素。
4.根据权利要求2所述的像素电路,其特征在于,奇数行所述子像素中,所述第二子像素为奇数个所述子像素,所述第一子像素为偶数个所述子像素;
偶数行所述子像素中,所述第一子像素为奇数个所述子像素,所述第二子像素为偶数个所述子像素。
5.根据权利要求2-4任意一项所述的像素电路,其特征在于,每个所述子像素组中,所述第一子像素和所述第二子像素各自连接的所述P型碳纳米管开关管和所述N型碳纳米管开关管分别位于其所连接的所述数据线的两侧。
6.根据权利要求5所述的像素电路,其特征在于,每个所述子像素组中,所述第一子像素和所述第二子像素各自连接的所述P型碳纳米管开关管和所述N型碳纳米管开关管以其所连接的所述数据线为对称轴镜像对称。
7.根据权利要求2所述的像素电路,其特征在于,每行所述子像素所连接的所述碳纳米管开关管连接一条所述栅线,相邻两列所述子像素所连接的所述碳纳米管开关管连接一条所述数据线。
8.一种如权利要求1-7任意一项所述的像素电路的制备方法,包括形成多个碳纳米管开关管;形成排布呈阵列的多个子像素,所述碳纳米管开关管与所述子像素一一对应连接,其特征在于,每行所述子像素分成多个子像素组,每个所述子像素组均包括第一子像素和第二子像素,所述第一子像素连接N型碳纳米管开关管,所述第二子像素连接P型碳纳米管开关管,连接所述第一子像素的所述N型碳纳米管开关管和和连接所述第二子像素的所述P型碳纳米管开关管的有源层同时形成,所述P型碳纳米管开关管和所述N型碳纳米管开关管的源漏极分别采用不同材料形成。
9.一种如权利要求1-7任意一项所述的像素电路的驱动方法,其特征在于,每行子像素的驱动均包括正向驱动阶段和负向驱动阶段;
在每行所述子像素的所述正向驱动阶段,连接N型碳纳米管开关管的栅线输入正向电压,所述N型碳纳米管开关管开启,连接所述N型碳纳米管开关管的数据线输入正电压,所述N型碳纳米管开关管驱动所述第一子像素进行显示;
在每行所述子像素的所述负向驱动阶段,连接P型碳纳米管开关管的所述栅线输入负向电压,所述P型碳纳米管开关管开启,连接所述P型碳纳米管开关管的所述数据线输入负电压,所述P型碳纳米管开关管驱动所述第二子像素进行显示。
10.根据权利要求9所述的像素电路的驱动方法,其特征在于,奇数行中的奇数个所述子像素和偶数行中的偶数个所述子像素在所述正向驱动阶段驱动;
奇数行中的偶数个所述子像素和偶数行中的奇数个所述子像素在所述负向驱动阶段驱动。
11.根据权利要求9所述的像素电路的驱动方法,其特征在于,奇数行中的偶数个所述子像素和偶数行中的奇数个所述子像素在所述正向驱动阶段驱动;
奇数行中的奇数个所述子像素和偶数行中的偶数个所述子像素在所述负向驱动阶段驱动。
12.一种显示装置,其特征在于,包括权利要求1-7任意一项所述的像素电路。
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