CN106981514A - 基于纳米沟道的凹槽栅增强型GaN晶体管器件 - Google Patents

基于纳米沟道的凹槽栅增强型GaN晶体管器件 Download PDF

Info

Publication number
CN106981514A
CN106981514A CN201710380274.1A CN201710380274A CN106981514A CN 106981514 A CN106981514 A CN 106981514A CN 201710380274 A CN201710380274 A CN 201710380274A CN 106981514 A CN106981514 A CN 106981514A
Authority
CN
China
Prior art keywords
nano
channel
gan
algan
transistor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710380274.1A
Other languages
English (en)
Other versions
CN106981514B (zh
Inventor
周幸叶
冯志红
吕元杰
谭鑫
王元刚
宋旭波
徐鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CETC 13 Research Institute
Original Assignee
CETC 13 Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CETC 13 Research Institute filed Critical CETC 13 Research Institute
Priority to CN201710380274.1A priority Critical patent/CN106981514B/zh
Publication of CN106981514A publication Critical patent/CN106981514A/zh
Application granted granted Critical
Publication of CN106981514B publication Critical patent/CN106981514B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7788Vertical transistors
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本发明公开了一种基于纳米沟道的凹槽栅增强型GaN晶体管器件,涉及微电子器件技术领域,自下而上包括衬底层、GaN缓冲层、AlGaN势垒层、栅介质层、钝化层、源电极、漏电极和栅电极;将AlGaN/GaN高电子迁移率晶体管器件栅电极下方的异质结刻蚀形成纳米沟道,则纳米沟道两侧区域不存在二维电子气,栅电极包裹在纳米沟道的上方及两侧壁,由于栅电极从三个方向对沟道内的电子进行调制,栅控能力强,能够很好地抑制短沟效应。当纳米沟道的宽度很小时,沟道内的二维电子气被耗尽,器件实现增强型。采用凹槽栅结构,纳米沟道和凹槽栅共同作用,可以保证器件在实现增强型的同时具有较大的纳米沟道宽度,减小导通电阻。

Description

基于纳米沟道的凹槽栅增强型GaN晶体管器件
技术领域
本发明涉及微电子器件技术领域,特别是涉及一种基于纳米沟道的凹槽栅增强型GaN晶体管器件。
背景技术
宽禁带半导体材料GaN具有高临界击穿电场、高电子饱和速度、良好的热稳定性以及较强的抗辐射能力等优点,特别是AlGaN/GaN异质结构材料由于自发极化和压电极化效应具有极高的二维电子气浓度和电子迁移率,被认为是制备耐高温、抗辐射、高频大功率微波功率器件及高速、高压电力开关器件和抗辐射高速数字电路的优良材料。
由于极化效应的存在,AlGaN/GaN高电子迁移率晶体管通常为耗尽型器件,制备增强型器件比较困难,研究进展非常缓慢。耗尽型器件的应用具有局限性。首先,在射频功率应用方面,耗尽型器件必须采用负电压偏置栅极,要求设计独立的电源***。其次,在电力开关应用方面,为了保证***的总体安全性,耗尽型器件还要求负偏压***的运行先于电源通电。此外,在高速数字电路应用方面,增强型器件是构成反相器的必备元件,而反相器是构成复杂数字***的核心单元。因此,研制出高可靠性的增强型GaN晶体管具有非常重要的意义。
目前,国际上对于增强型GaN器件的一种研究思路是通过在栅电极下方挖槽,使栅极下方的沟道二维电子气耗尽,沟道其余部分二维电子气浓度不变,从而实现增强型器件。但是,随着器件尺寸的不断缩小,栅长越来越短,传统平面结构的高电子迁移率晶体管的短沟效应越来越明显。2013年,Ki-Sik Im等人制备出了单纳米沟道的增强型AlGaN/GaNMISFET,阈值电压为2.1V,该器件结构采用普通栅结构,为了实现增强型器件,纳米沟道宽度仅为50nm,而且纳米沟道两端延伸到了源漏电极区,因此,器件导通电阻较大。
发明内容
本发明要解决的技术问题是针对上述现有技术的不足,提供一种基于纳米沟道的凹槽栅增强型GaN晶体管器件,所述晶体管具有栅控能力强、能够抑制短沟效应、实现器件增强型和导通电阻小的特点。
为解决上述技术问题,本发明所采取的技术方案是:一种基于纳米沟道的凹槽栅增强型GaN晶体管器件,自下而上包括衬底层、GaN缓冲层、AlGaN势垒层、栅介质层、钝化层、源电极、漏电极和栅电极;其特征在于:所述AlGaN势垒层和所述GaN缓冲层形成AlGaN/GaN异质结,所述AlGaN势垒层上方有凹槽,栅电极位于凹槽内并且包裹在AlGaN/GaN异质结的上方和两侧,形成三维环栅结构;所述栅电极下的AlGaN/GaN异质结具有纳米图形,形成纳米沟道;所述纳米沟道两端具有沟道扩展区;所述栅介质层位于所述栅电极之下,所述源电极和所述漏电极之间,覆盖在所述AlGaN/GaN异质结顶部并包裹所述纳米沟道的两个侧壁。
优选地,所述衬底层为蓝宝石、SiC或GaN。
优选地,所述GaN缓冲层厚度为0.5-2.5um。
优选地,所述AlGaN势垒层厚度为10-20nm,其中Al含量为15%-30%。
优选地,所述纳米沟道的数目n为n≥1,长度Lch为0<Lch<源电极和漏电极的间距,宽度Wch为10-200nm。
优选地,所述AlGaN势垒层上的凹槽底部与所述AlGaN/GaN异质结的距离Dch1为0-15nm,所述纳米沟道底部与所述AlGaN/GaN异质结的距离Dch2为0-150nm。
优选地,所述栅介质层为SiN、Al2O3、SiO2或多种介质层的堆叠结构,厚度为1-15nm。
优选地,所述钝化层为SiN、Al2O3、SiO2或多种钝化层的堆叠结构,厚度为50-150nm。
优选地,所述栅电极为直栅或T型栅,栅极长度Lg=Lch或Lg>Lch或Lg<Lch
优选地,所述源电极和漏电极为欧姆接触,位于纳米沟道两端的沟道扩展区之上。
采用上述技术方案所产生的有益效果在于:将AlGaN/GaN高电子迁移率晶体管器件栅电极下方的异质结刻蚀形成纳米沟道,则纳米沟道两侧区域不存在二维电子气,栅电极包裹在纳米沟道的上方及两侧壁,由于栅电极从三个方向对沟道内的电子进行调制,栅控能力较强,能够很好地抑制短沟效应。当纳米沟道的宽度很小时,沟道内的二维电子气被耗尽,器件实现增强型。采用凹槽栅结构,纳米沟道和凹槽栅共同作用,可以保证器件在实现增强型的同时具有较大的纳米沟道宽度,减小导通电阻。纳米沟道两端具有扩展区,可进一步减小导通电阻,提高器件频率。
附图说明
图1是本发明实施例一整体结构的俯视图。
图2是图1A-A面的剖视图。
图3是图1B-B面的剖视图。
图4是图1C-C面的剖视图。
图5是本发明实施例二整体结构的俯视图。
图6是本发明实施例三整体结构的俯视图。
图7是本发明实施例四整体结构的剖视图。
图中:1、源电极;2、漏电极;3、栅电极;4、沟道扩展区;5、纳米沟道;6、衬底层;7、GaN缓冲层;8、AlGaN势垒层;9、栅介质层;10、钝化层。
具体实施方式
下面结合附图和具体实施方式对本发明作进一步详细的说明。
如图1、图2、图3和图4所示,本发明器件包括衬底层6、GaN缓冲层7、AlGaN势垒层8、栅介质层9、钝化层10、源电极1、漏电极2和栅电极3。其中最下层是采用蓝宝石、SiC或GaN的衬底层6;衬底层6上面是GaN缓冲层7;缓冲层上面是AlGaN势垒层8;AlGaN势垒层8和GaN缓冲层7形成AlGaN/GaN异质结,AlGaN势垒层8上方有凹槽,栅电极3位于凹槽内,且包裹在异质结的上方及两侧,形成三维环栅结构;栅电极3下的AlGaN/GaN异质结具有纳米图形,形成纳米沟道5;纳米沟道5两端具有沟道扩展区4;栅介质层9位于AlGaN势垒层8和栅电极3之间,覆盖在AlGaN/GaN异质结顶部并包裹纳米沟道5的两个侧壁;源电极1和漏电极2分别位于纳米沟道5扩展区4之上;钝化层10覆盖在整个器件的表面。
下面参照附图,结合具体实施例对本发明作进一步详细说明。
实施例一:基于单纳米沟道的凹槽栅增强型GaN晶体管器件。
图1是本发明实施例一整体结构的俯视图,图2、图3和图4分别是图1中A-A面、B-B面和C-C面的剖视图。本实施例基于单纳米沟道5的凹槽栅增强型GaN晶体管器件自下而上包括衬底层6、GaN缓冲层7、AlGaN势垒层8、栅介质层9、钝化层10和源电极1、漏电极2和栅电极3。
衬底层6使用材料为蓝宝石、SiC或GaN。
衬底层6上面是厚度为0.5-2.5μm的GaN缓冲层7。
缓冲层上面是厚度为10-20nm和Al组分为15%~30%的AlGaN势垒层8。
AlGaN势垒层8和GaN缓冲层7形成AlGaN/GaN异质结,AlGaN势垒层8上方有凹槽,栅电极3位于凹槽内,且包裹在异质结的上方及两侧,形成三维环栅结构。其中所述栅凹槽底部与AlGaN/GaN异质结的距离Dch1为0-15nm。
栅电极3下的AlGaN/GaN异质结具有纳米图形,形成纳米沟道5,其中所述纳米沟道5的数目n为n=1,长度Lch为Lch=栅电极3长度Lg;纳米沟道5宽度Wch为10-200nm,纳米沟道5底部与AlGaN/GaN异质结的距离Dch2为0-150nm。
纳米沟道5两端具有沟道扩展区4。
栅介质层9位于AlGaN势垒层8和栅电极3之间,覆盖在AlGaN/GaN异质结顶部并包裹纳米沟道5的两个侧壁,栅介质层9采用SiN、Al2O3、SiO2或多种介质层的堆叠结构,厚度为1-15nm。
钝化层10位于除电极外的整个器件的表面,钝化层10采用SiN、Al2O3、SiO2或多种钝化层10的堆叠结构,厚度为50-150nm。
源电极1和漏电极2为欧姆接触,位于纳米沟道5两端的沟道扩展区4之上。
实施例二:基于单纳米沟道的凹槽栅增强型GaN晶体管器件。
如图5所示,本实施例的基于单纳米沟道5的凹槽栅增强型GaN晶体管器件具有与实施例一相同的结构,但所述纳米沟道5的长度Lch为Lch>栅长Lg
实施例三:基于多纳米沟道的凹槽栅增强型GaN晶体管器件。
如图6所示,本实施例的基于多纳米沟道的凹槽栅增强型GaN晶体管器件具有与实施例一相同的结构,但所述纳米沟道5的数目n为n>1。
实施例四:基于单纳米沟道的T型凹槽栅增强型GaN晶体管器件。
如图7所示,本实施例的基于单纳米沟道5的T型凹槽栅增强型GaN晶体管器件具有与实施例一相同的结构,但栅电极3采用T型栅结构。
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。

Claims (10)

1.一种基于纳米沟道的凹槽栅增强型GaN晶体管器件,自下而上包括衬底层(6)、GaN缓冲层(7)、AlGaN势垒层(8)、栅介质层(9)、钝化层(10)、源电极(1)、漏电极(2)和栅电极(3);其特征在于:所述AlGaN势垒层(8)和所述GaN缓冲层(7)形成AlGaN/GaN异质结,所述AlGaN势垒层(8)上方有凹槽,栅电极(3)位于凹槽内并且包裹在AlGaN/GaN异质结的上方和两侧,形成三维环栅结构;所述栅电极(3)下的AlGaN/GaN异质结具有纳米图形,形成纳米沟道(5);所述纳米沟道(5)两端具有沟道扩展区(4);所述栅介质层(9)位于所述栅电极(3)之下,所述源电极(1)和所述漏电极(2)之间,覆盖在所述AlGaN/GaN异质结顶部并包裹所述纳米沟道(5)的两个侧壁。
2.根据权利要求1所述的基于纳米沟道的凹槽栅增强型GaN晶体管器件,其特征在于:所述衬底层(6)为蓝宝石、SiC或GaN。
3.根据权利要求1所述的基于纳米沟道的凹槽栅增强型GaN晶体管器件,其特征在于:所述GaN缓冲层(7)厚度为0.5-2.5um。
4.根据权利要求1所述的基于纳米沟道的凹槽栅增强型GaN晶体管器件,其特征在于:所述AlGaN势垒层(8)厚度为10-20nm,其中Al含量为15%-30%。
5.根据权利要求1所述的基于纳米沟道的凹槽栅增强型GaN晶体管器件,其特征在于:所述纳米沟道(5)的数目n为n≥1,长度Lch为0<Lch<源电极(1)和漏电极(2)的间距,宽度Wch为10-200nm。
6.根据权利要求1所述的基于纳米沟道的凹槽栅增强型GaN晶体管器件,其特征在于:所述AlGaN势垒层(8)上的凹槽底部与所述AlGaN/GaN异质结的距离Dch1为0-15nm,所述纳米沟道(5)底部与所述AlGaN/GaN异质结的距离Dch2为0-150nm。
7.根据权利要求1所述的基于纳米沟道的凹槽栅增强型GaN晶体管器件,其特征在于:所述栅介质层(9)为SiN、Al2O3、SiO2或多种介质层的堆叠结构,厚度为1-15nm。
8.根据权利要求1所述的基于纳米沟道的凹槽栅增强型GaN晶体管器件,其特征在于:所述钝化层(10)为SiN、Al2O3、SiO2或多种钝化层(10)的堆叠结构,厚度为50-150nm。
9.根据权利要求1所述的基于纳米沟道的凹槽栅增强型GaN晶体管器件,其特征在于:所述栅电极(3)为直栅或T型栅,栅极长度Lg=Lch或Lg>Lch或Lg<Lch
10.根据权利要求1所述的基于纳米沟道的凹槽栅增强型GaN晶体管器件,其特征在于:所述源电极(1)和漏电极(2)为欧姆接触,位于纳米沟道(5)两端的沟道扩展区(4)之上。
CN201710380274.1A 2017-05-25 2017-05-25 基于纳米沟道的凹槽栅增强型GaN晶体管器件 Active CN106981514B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710380274.1A CN106981514B (zh) 2017-05-25 2017-05-25 基于纳米沟道的凹槽栅增强型GaN晶体管器件

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710380274.1A CN106981514B (zh) 2017-05-25 2017-05-25 基于纳米沟道的凹槽栅增强型GaN晶体管器件

Publications (2)

Publication Number Publication Date
CN106981514A true CN106981514A (zh) 2017-07-25
CN106981514B CN106981514B (zh) 2023-07-18

Family

ID=59344883

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710380274.1A Active CN106981514B (zh) 2017-05-25 2017-05-25 基于纳米沟道的凹槽栅增强型GaN晶体管器件

Country Status (1)

Country Link
CN (1) CN106981514B (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107919397A (zh) * 2017-11-20 2018-04-17 西安电子科技大学 一种高线性场效应晶体管器件及其制作方法
CN108470768A (zh) * 2018-03-02 2018-08-31 华南理工大学 一种hemt器件纳米栅极的制备方法
CN108666216A (zh) * 2018-05-15 2018-10-16 西安电子科技大学 基于叠层钝化结构的hemt器件及其制备方法
US11349003B2 (en) * 2019-05-15 2022-05-31 Cambridge Electronics, Inc. Transistor structure with a stress layer
CN114843187A (zh) * 2021-02-02 2022-08-02 北京大学 一种GaN基多纳米沟道高电子迁移率晶体管的制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009049288A (ja) * 2007-08-22 2009-03-05 Nec Corp 半導体装置
CN104201104A (zh) * 2014-09-09 2014-12-10 电子科技大学 一种氮化镓基增强型器件的制造方法
RU160576U1 (ru) * 2015-10-29 2016-03-27 федеральное государственное автономное образовательное учреждение высшего профессионального образования "Национальный исследовательский ядерный университет МИФИ" (НИЯУ МИФИ) ТРАНЗИСТОРНАЯ ГЕТЕРОСТРУКТУРА ТИПА Р-НЕМТ С ВАРИЗОННЫМ БАРЬЕРОМ AlX(Z)Ga1-X(Z)As
CN206947353U (zh) * 2017-05-25 2018-01-30 中国电子科技集团公司第十三研究所 基于纳米沟道的凹槽栅增强型GaN晶体管器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009049288A (ja) * 2007-08-22 2009-03-05 Nec Corp 半導体装置
CN104201104A (zh) * 2014-09-09 2014-12-10 电子科技大学 一种氮化镓基增强型器件的制造方法
RU160576U1 (ru) * 2015-10-29 2016-03-27 федеральное государственное автономное образовательное учреждение высшего профессионального образования "Национальный исследовательский ядерный университет МИФИ" (НИЯУ МИФИ) ТРАНЗИСТОРНАЯ ГЕТЕРОСТРУКТУРА ТИПА Р-НЕМТ С ВАРИЗОННЫМ БАРЬЕРОМ AlX(Z)Ga1-X(Z)As
CN206947353U (zh) * 2017-05-25 2018-01-30 中国电子科技集团公司第十三研究所 基于纳米沟道的凹槽栅增强型GaN晶体管器件

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107919397A (zh) * 2017-11-20 2018-04-17 西安电子科技大学 一种高线性场效应晶体管器件及其制作方法
CN108470768A (zh) * 2018-03-02 2018-08-31 华南理工大学 一种hemt器件纳米栅极的制备方法
CN108666216A (zh) * 2018-05-15 2018-10-16 西安电子科技大学 基于叠层钝化结构的hemt器件及其制备方法
CN108666216B (zh) * 2018-05-15 2021-05-07 西安电子科技大学 基于叠层钝化结构的hemt器件及其制备方法
US11349003B2 (en) * 2019-05-15 2022-05-31 Cambridge Electronics, Inc. Transistor structure with a stress layer
CN114843187A (zh) * 2021-02-02 2022-08-02 北京大学 一种GaN基多纳米沟道高电子迁移率晶体管的制备方法
CN114843187B (zh) * 2021-02-02 2024-05-17 北京大学 一种GaN基多纳米沟道高电子迁移率晶体管的制备方法

Also Published As

Publication number Publication date
CN106981514B (zh) 2023-07-18

Similar Documents

Publication Publication Date Title
CN106981514A (zh) 基于纳米沟道的凹槽栅增强型GaN晶体管器件
Zhang et al. 1200 V GaN vertical fin power field-effect transistors
CN103367403B (zh) 半导体器件及其制造方法
TWI644429B (zh) 非對稱閉鎖雙向氮化鎵開關
CN105247683B (zh) 半导体装置
US10672896B2 (en) GaN-based bidirectional switch device
CN108807526B (zh) 增强型开关器件及其制造方法
CN103930997B (zh) 具有凹陷电极结构的半导体器件
CN106356405A (zh) 一种异质结碳纳米管场效应晶体管及其制备方法
CN105118830B (zh) 一种集成sbd的增强型hemt
CN104051523A (zh) 一种低欧姆接触电阻的半导体器件及其制作方法
WO2014094362A1 (zh) 使用高介电常数槽结构的低比导通电阻的横向功率器件及其制备方法
CN110326109A (zh) 短沟道沟槽功率mosfet
JP2017123383A (ja) 窒化物半導体トランジスタ装置
CN108598149A (zh) 一种GaN基HEMT器件
CN115668512A (zh) 半导体装置
EP3520142A1 (en) Semiconductor device comprising a three-dimensional field plate
CN206947353U (zh) 基于纳米沟道的凹槽栅增强型GaN晶体管器件
CN110148626A (zh) 极化掺杂InN基隧穿场效应晶体管及其制作方法
CN205564759U (zh) 一种新型增强型iii-v异质结场效应晶体管
CN206322705U (zh) 一种GaN HEMT器件
CN108899369A (zh) 一种石墨烯沟道碳化硅功率半导体晶体管
CN106252404B (zh) 一种具有高k介质槽的纵向增强型mis hemt器件
CN109192780A (zh) 一种横向mosfet器件及其制备方法
CN114300540A (zh) 一种源漏非对称的环栅可重构场效应晶体管

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant